AT720LTS14 [POSEICO]
PHASE CONTROL THYRISTOR;型号: | AT720LTS14 |
厂家: | POWER SEMICONDUCTORS |
描述: | PHASE CONTROL THYRISTOR |
文件: | 总4页 (文件大小:156K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
POSEICO SPA
Via Pillea 42-44, 16153 Genova - ITALY
Tel. + 39 010 8599400 - Fax + 39 010 8682006
Sales Office:
Tel. + 39 010 8599400 - sales@poseico.com
PHASE CONTROL THYRISTOR
AT720LT
Repetitive voltage up to
Mean forward current
Surge current
1400 V
4366 A
60 kA
FINAL SPECIFICATION
Feb. 17 - Issue: 4
Tj
[°C]
Symbol
Characteristic
Conditions
Value
Unit
BLOCKING
V RRM
V RSM
V DRM
Repetitive peak reverse voltage
Non-repetitive peak reverse voltage
Repetitive peak off-state voltage
Repetitive peak reverse current
Repetitive peak off-state current
125
125
125
125
125
1400
1500
1400
200
V
V
V
I
I
RRM
DRM
V=VRRM
V=VDRM
mA
mA
200
CONDUCTING
I
I
I
T (AV)
T (AV)
TSM
Mean forward current
180° sin, 50 Hz, Th=55°C, double side cooled
180° sin, 50 Hz, Tc=85°C, double side cooled
4366
3494
60
A
A
Mean forward current
Surge forward current
I² t
Sine wave, 10 ms
without reverse voltage
125
kA
x 103
I² t
18000
1,18
A²s
V
V T
On-state voltage
Threshold voltage
On-state slope resistance
On-state current =
4000 A
125
125
125
V T(TO)
0,88
V
r
T
0,075
mohm
SWITCHING
From 75% VDRM up to 3000 A; gate 10V, 5W
di/dt
Critical rate of rise of on-state current, min.
Critical rate of rise of off-state voltage, min.
Gate controlled delay time, typical
Circuit commutated turn-off time, typical
Reverse recovery charge
125
125
25
200
1000
3
A/µs
V/µs
µs
dv/dt
Linear ramp up to 75% of VDRM
VD=100V; gate source 25V, 10W , tr=.5 µs
t
t
d
q
dv/dt = 20 V/µs linear up to 80% VDRM
di/dt = -20 A/µs, I= 2000 A
VR= 50 V
320
µs
Q rr
125
µC
A
I
I
I
rr
H
L
Peak reverse recovery current
Holding current, typical
VD=5V, gate open circuit
VD=5V, tp=30µs
25
25
300
700
mA
mA
Latching current, typical
GATE
V GT
Gate trigger voltage
VD=5V
25
25
3,50
350
0,25
30
V
mA
V
I
GT
Gate trigger current
VD=5V
V GD
Non-trigger gate voltage, min.
Peak gate voltage (forward)
Peak gate current
VD=VDRM
125
V FGM
V
I
FGM
10
A
V RGM
P GM
P G
Peak gate voltage (reverse)
Peak gate power dissipation
Average gate power dissipation
5
V
Pulse width 100 µs
150
2
W
W
MOUNTING
R th(j-h)
R th(c-h)
T j
Thermal impedance, DC
Thermal impedance
Operating junction temperature
Mounting force
Junction to heatsink, double side cooled
Case to heatsink, double side cooled
9,5
2
°C/kW
°C/kW
°C
-30 / 125
F
40,0 / 50,0
1150
kN
Mass
g
ORDERING INFORMATION : AT720LT S 14
VRRM/100
standard specification
AT720LT PHASE CONTROL THYRISTOR
FINAL SPECIFICATION Feb. 17 - Issue: 4
DISSIPATION CHARACTERISTICS
SQUARE WAVE
Th [°C]
130
120
110
100
90
80
70
60
50
30°
60°
90°
120°
180°
DC
40
0
1000
2000
3000
4000
5000
6000
IT(AV) [A]
PF(AV) [W]
8000
DC
180°
7000
6000
5000
4000
3000
2000
1000
0
120°
90°
60°
30°
0
1000
2000
3000
4000
5000
6000
IT(AV) [A]
AT720LT PHASE CONTROL THYRISTOR
FINAL SPECIFICATION Feb. 17 - Issue: 4
DISSIPATION CHARACTERISTICS
SINE WAVE
Th [°C]
130
120
110
100
90
80
70
60
50
30°
60°
90°
120°
180°
40
0
1000
2000
3000
4000
5000
IT(AV) [A]
PF(AV) [W]
8000
7000
6000
5000
4000
3000
2000
1000
180°
120°
90°
60°
30°
0
0
1000
2000
3000
4000
5000
IT(AV) [A]
AT720LT PHASE CONTROL THYRISTOR
FINAL SPECIFICATION Feb. 17 - Issue: 4
ON-STATE CHARACTERISTIC
Tj = 125 °C
SURGE CHARACTERISTIC
Tj = 125 °C
14000
12000
10000
8000
6000
4000
2000
0
70
60
50
40
30
20
10
0
0
0,5
1
1,5
2
1
10
100
On-state Voltage [V]
n° cycles
TRANSIENT THERMAL IMPEDANCE
DOUBLE SIDE COOLED
10
9
8
7
6
5
4
3
2
1
0
0,001
0,01
0,1
1
10
100
t[s]
Cathode terminal type DIN 46244 - A 4.8 - 0.8
Gate terminal type AMP 60598 - 1
Distributed by
All the characteristics given in this data sheet are guaranteed only with uniform clamping force,
cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm.
In the interest of product improvement POSEICO SpA reserves the right to change any data
given in this data sheet at any time without previous notice.
If not stated otherwise the maximum value of ratings (simbols over shaded background) and
characteristics is reported.
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