PLL602-03HSC [PLL]

Low Phase Noise CMOS XO (48MHz to 100MHz); 低相位噪声CMOS XO ( 48MHz的至100MHz )
PLL602-03HSC
型号: PLL602-03HSC
厂家: PHASELINK CORPORATION    PHASELINK CORPORATION
描述:

Low Phase Noise CMOS XO (48MHz to 100MHz)
低相位噪声CMOS XO ( 48MHz的至100MHz )

石英晶振
文件: 总4页 (文件大小:200K)
中文:  中文翻译
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PLL602-03  
Low Phase Noise CMOS XO (48MHz to 100MHz)  
FEATURES  
PIN CONFIGURATION  
Low phase noise XO output for the 48MHz to  
100MHz range (-130 dBc at 10kHz offset).  
12 to 25MHz crystal input.  
CLK  
VDD  
OE^  
XIN  
GND  
GND  
N/C  
1
2
3
4
8
7
6
5
Integrated crystal load capacitor: no external  
load capacitor required.  
Low jitter (RMS): 3ps period jitter (1 sigma).  
Selectable High Drive (30mA) or Standard Drive  
(10mA) output.  
XOUT  
Note: ^ denotes internal pull up  
3.3V operation.  
Available in 8-Pin TSSOP or SOIC.  
OUTPUT RANGE  
FREQUENCY  
RANGE  
OUTPUT  
BUFFER  
DESCRIPTION  
MULTIPLIER  
X4  
48 - 100MHz  
CMOS  
The PLL602-03 is a low cost, high performance and  
low phase noise XO, providing less than -130dBc at  
10kHz offset in the 48MHz to 100MHz operating  
range. The very low jitter (3ps RMS period jitter)  
makes this chip ideal for applications requiring clean  
reference frequency sources. Input crystal can range  
from 12 to 25MHz (fundamental resonant mode).  
BLOCK DIAGRAM  
VCO  
Divider  
Reference  
Divider  
Phase  
Charge  
Pump  
Loop  
Filter  
VCO  
OE  
CLK  
Comparator  
XIN  
XOUT  
XTAL  
OSC  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1  
PLL602-03  
Low Phase Noise CMOS XO (48MHz to 100MHz)  
PIN DESCRIPTIONS  
Name  
Number  
Type  
Description  
CLK  
VDD  
1
2
O
P
Output clock.  
power supply.  
Output enable input. Disables (tri-state) output when low. Internal pull-up  
enables output by default if pin is not connected to low.  
OE  
3
I
XIN  
XOUT  
N/C  
4
5
I
I
Crystal input. See Crystal Specification on page 3.  
Crystal output. See Crystal Specification on page 3.  
Not connected.  
6
-
GND  
7, 8  
P
Ground.  
ELECTRICAL SPECIFICATIONS  
1. Absolute Maximum Ratings  
PARAMETERS  
SYMBOL  
MIN.  
MAX.  
UNITS  
Supply Voltage  
VDD  
VI  
4.6  
VDD+0.5  
VDD+0.5  
150  
V
Input Voltage, dc  
-0.5  
-0.5  
-65  
V
Output Voltage, dc  
VO  
TS  
TA  
TJ  
V
Storage Temperature  
°C  
°C  
°C  
°C  
kV  
Ambient Operating Temperature*  
Junction Temperature  
-40  
85  
125  
Lead Temperature (soldering, 10s)  
ESD Protection, Human Body Model  
260  
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the  
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-  
ditions above the operational limits noted in this specification is not implied.  
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.  
2. DC Specifications  
PARAMETERS  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
Supply Current, Dynamic, with  
Loaded Outputs  
FXIN = 12 - 25MHz  
Output load of 10pF  
IDD  
16  
20  
mA  
Operating Voltage  
VDD  
IOH  
IOL  
2.97  
30  
3.63  
V
VOH= VDD-0.4V, VDD=3.3V  
VOL = 0.4V, VDD = 3.3V  
VOH= VDD-0.4V, VDD=3.3V  
VOL = 0.4V, VDD = 3.3V  
mA  
mA  
mA  
mA  
mA  
Output drive current  
(High Drive)  
30  
IOH  
IOL  
10  
Output drive current  
(Standard Drive)  
10  
Short Circuit Current  
±50  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2  
PLL602-03  
Low Phase Noise CMOS XO (48MHz to 100MHz)  
3. AC Specifications  
PARAMETERS  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
Input Crystal Frequency  
12  
25  
MHz  
Output Clock Rise/Fall Time  
(Standard Drive)  
Output Clock Rise/Fall Time  
(High Drive)  
0.3V ~ 3.0V with 15 pF load  
2.4  
ns  
%
0.3V ~ 3.0V with 15 pF load  
Measured @ 50% VDD  
1.2  
50  
Output Clock Duty Cycle  
45  
55  
4. Jitter and Phase Noise Specification  
PARAMETERS CONDITIONS  
RMS Period Jitter  
MIN.  
TYP.  
MAX.  
UNITS  
at 80MHz, with capacitive decoupling  
between VDD and GND.  
3.5  
ps  
(1 sigma – 1000 samples)  
Phase Noise relative to carrier  
80MHz @100Hz offset  
80MHz @1kHz offset  
80MHz @10kHz offset  
80MHz @100kHz offset  
-103  
-122  
-130  
-125  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Phase Noise relative to carrier  
Phase Noise relative to carrier  
Phase Noise relative to carrier  
5. Crystal Specifications  
PARAMETERS  
SYMBOL  
MIN.  
TYP.  
MAX.  
UNITS  
Crystal Resonator Frequency  
Crystal Loading Capacitance Rating  
Driving power  
12  
25  
MHz  
pF  
FXIN  
20  
1
CL  
(xtal)  
mW  
ESR  
RS  
30  
PACKAGE INFORMATION  
8 PIN ( dimensions in mm )  
Narrow SOIC  
TSSOP  
Symbol  
Min.  
Max.  
1.73  
0.25  
0.51  
0.25  
4.95  
4.00  
6.20  
1.27  
Min.  
-
Max.  
E
H
1.20  
0.15  
0.30  
0.20  
3.10  
4.50  
6.60  
0.75  
A
A1  
B
C
D
E
H
L
e
1.47  
0.10  
0.33  
0.19  
4.80  
3.80  
5.80  
0.38  
0.05  
0.19  
0.09  
2.90  
4.30  
6.20  
0.45  
D
A
A1  
C
0.65 BSC  
1.27 BSC  
L
B
e
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3  
PLL602-03  
Low Phase Noise CMOS XO (48MHz to 100MHz)  
ORDERING INFORMATION  
For part ordering, please contact our Sales Department:  
47745 Fremont Blvd., Fremont, CA 94538, USA  
Tel: (510) 492-0990 Fax: (510) 492-0991  
PART NUMBER  
The order number for this device is a combination of the following:  
Device number, Package type and Operating temperature range  
PLL602-03 (H) X C  
PART NUMBER  
TEMPERATURE  
C=COMMERCIAL  
I=INDUSTRAL  
Optional High Drive  
PACKAGE TYPE  
S=SOIC, O=TSSOP  
Order Number  
Marking  
Package Option  
PLL602-03OC-R  
PLL602-03OC  
PLL602-03HOC-R  
PLL602-03HOC  
PLL602-03OC  
PLL602-03OC  
PLL602-03HOC  
PLL602-03HOC  
TSSOP - Tape and Reel  
TSSOP – Tube  
TSSOP - Tape and Reel  
TSSOP – Tube  
PLL602-03SC-R  
PLL602-03SC  
PLL602-03HSC-R  
PLL602-03HSC  
PLL602-03SC  
PLL602-03SC  
PLL602-03HSC  
PLL602-03HSC  
SOIC - Tape and Reel  
SOIC – Tube  
SOIC - Tape and Reel  
SOIC - Tube  
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-  
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said  
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.  
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-  
press written approval of the President of PhaseLink Corporation.  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 03/14/00 Page 4  

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