P580-68QC [PLL]
320-640MHz Low Phase Noise VCXO; 320-640MHz低相位噪声压控石英振荡器
| 型号： | P580-68QC |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | 320-640MHz Low Phase Noise VCXO |
| 文件： | 总10页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
FEATURES
PACKAGE PIN ASSIGNMENT
•
Less than 0.4ps RMS (12KHz-20MHz) phase
jitter for all frequencies.
Low phase noise output (@ 1MHz frequency
offset
VDDANA
XIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
•
SEL1^
∗
∗
-140dBc/Hz for 320.0MHz,
-131dBC/Hz for 622.08MHz
XOUT
GNDBUF
QBAR
SEL2^
OE_CTRL
VCON
GNDANA
LP
•
•
•
•
•
•
•
•
20MHz-40MHz crystal input.
320MHz-640MHz output.
Available in PECL, or LVDS outputs.
No external varicap required.
Output Enable selector.
Wide pull range (+/-200ppm).
3.3V operation.
Available in 3x3 QFN or 16-pin TSSOP
packages.
VDDBUF
Q
GNDBUF
LM
DESCRIPTION
12 11 10
13
9
4
8
7
6
5
XOUT
DNC
GNDBUF
QBAR
VDDBUF
Q
The PL580-6X is a monolithic low jitter and low
phase noise VCXO, capable of 0.4ps RMS phase
jitter and PECL or LVDS outputs, covering a wide
frequency output range up to 640MHz. It allows the
control of the output frequency with an input voltage
(VCON), using a low cost crystal.
14
15
16
PL580-6X
OE_CTRL
VCON
1
2
3
The PL580-6X is designed to address the
demanding requirements of high performance
applications such as SONET, GPS, Video, etc.
Note1: ^ Denotes internal pull up resistor.
BLOCK DIAGRAM
VCON
VCO
Divider
VARICAP
Charge
QBAR
Output
Pump
XIN
Phase
Detector
VCO
(FXiNx16)
XTAL
OSC
+
Divider
Loop
Q
XOUT
Filter
OE
Performance Tuner
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 1
(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default)
Output enabled
Tri-state
PLL580-68 (PECL)
1
0
Tri-state
PLL580-69 (LVDS)
1 (Default)
Output enabled
PIN DESCRIPTIONS
TSSOP
Pin number
3x3mm QFN
Pin number
Name
Type
Description
VDDANA
XIN
1
2
3
4
5
6
7
11
12
13
14
15
16
1
P
I
VDD for analog Circuitry.
Crystal input pin. (See Crystal Specifications on page 4).
Crystal output pin. (See Crystal Specifications on page 4).
Do Not Connect
XOUT
O
-
DNC
OE_CTRL
VCON
I
Output enable control pin. (See OE_CTRL Logic Levels above).
Voltage control input.
I
GNDANA
P
Ground for analog circuitry.
Tuning inductor connection. The inductor is recommended to be
a high Q small size 0402 or 0603 SMD component, and must be
placed between LP and adjacent LM pin. Place inductor as close
to the IC as possible to minimize parasitic effects and to
maintain inductor Q.
LP
8
9
2
3
-
-
LM
GNDBUF
Q
10
11
4
5
P
GND connection for output buffer circuitry.
PECL or LVDS output.
O
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
VDDBUF
12
6
P
QBAR
GNDBUF
DNC
13
14
15
16
7
8
O
P
-
Complementary PECL, LVDS output.
GND connection for output buffer circuitry.
Do Not Connect
9
DNC
10
-
Do Not Connect
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 2
(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
FREQUENCY SELECTION TABLE
SEL2
SEL1
SEL0
Selected Multiplier/Output Frequency
0
0
1
0
0
1
1
VCO Max*
VCO Min*
Fin x 16
0
1
All Other Combinations
Reserved
All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0.
* Special Test Modes to help selecting the inductor value for the target output frequency.
PERFORMANCE TUNING & INDUCTOR VALUE SELECTION
Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor
values for your application. In addition, the chart below could be used as a reference for quick inductor value
selection. Please note that the inductor values mentioned in the table below, or when using ‘PhasorV Tuning
Assistance’ are derived based on the parasitic values of PhaseLink’s evaluation board. For performance
enhancement of your custom board design, please follow the following instruction:
Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max”
represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output
frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are
around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency
is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock
in the middle of its tuning range with maximum margin on either side.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 3
(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
-0.5
-0.5
-65
V
Output Voltage, dc
VO
TS
TA
TJ
V
Storage Temperature
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
FXIN
Parallel Fundamental Mode
at VCON = 0V
at VCON = 1.65V
at VCON = 3.3V
AT cut
20
40
MHz
17.7
9.5
5.4
Crystal Loading Rating
CL (xtal)
pF
Crystal Pullability
C0/C1 (xtal)
RE
250
30
-
Recommended ESR
AT cut
Ω
Note: Crystal Loading rating: The listed numbers are for the IC only. Specify the crystal for the value at VCON = 1.65V and add the PCB & package
parasitic. A round number (i.e. 12pF) can be achieved by adding external capacitors. Try to add the same value to XIN and XOUT, and please note,
that frequency pulling and oscillator gain may decrease.
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
From power valid
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
TVCXOSTB
10
ms
FXIN = 20 – 40MHz;
XTAL C0/C1 < 250
0V ≤ VCON ≤ 3.3V
VCXO Tuning Range
500
150
ppm
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
ppm
ppm/V
%
VCON=1.65V, ±1.65V
±200
10
VCON pin input impedance
VCON modulation BW
60
25
kΩ
kHz
0V ≤ VCON ≤ 3.3V, -3dB
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 4
(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
4. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating Voltage
IDD
PECL/LVDS
320MHz<Fout<640MHz
90/70
3.63
mA
V
VDD
2.97
@ 50% VDD (CMOS)
@ 1.25V (LVDS)
@ VDD – 1.3V (PECL)
45
45
45
50
50
50
55
55
55
Output Clock
Duty Cycle
%
Short Circuit
Current
mA
±50
5. Jitter Specifications
PARAMETERS
CONDITIONS
FREQUENCY
MIN.
TYP.
MAX.
UNITS
320.0MHz
622.08MHz
320.0MHz
0.4
0.4
3
0.5
0.6
5
Integrated jitter RMS
Period jitter RMS
Integrated 12 kHz to 20 MHz
ps
ps
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
622.08MHz
320.0MHz
622.08MHz
6
8
25
40
30
50
Period jitter Peak-to-
Peak
ps
6. Phase Noise Specifications
@10Hz @100Hz @1kHz @10kHz @100kHz
@1M
@10M
PARAMETERS
FREQ.
UNITS
Phase Noise2
relative to
carrier (typical)
320.0MHz
-59
-48
-86
-80
-116
-108
-129
-118
-124
-114
-140
-131
-148
-138
dBc/Hz
622.08MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 5
(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
8. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
∆VOD
VOH
247
-50
355
454
50
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
VOL
0.9
1.125
0
V
VOS
1.375
25
V
Offset Magnitude Change
mV
∆VOS
Vout = VDD or GND
VDD = 0V
Power-off Leakage
IOXD
IOSD
uA
±1
±10
Output Short Circuit Current
-5.7
-8
mA
9. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
RL = 100 Ω
CL = 10 pF
(see figure)
Differential Clock Rise Time
Differential Clock Fall Time
tr
tf
0.2
0.2
0.7
0.7
1.0
1.0
ns
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50
50
Ω
Ω
VOD
VOS
VDIFF
RL = 100Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
80%
80%
VDIFF
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 6
(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
10. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
Output Low Voltage
VOH
VOL
VDD – 1.025
V
V
RL = 50 Ω to (VDD – 2V)
(see figure)
VDD – 1.620
11. PECL Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Clock Rise Time
Clock Fall Time
tr
tf
@20/80% - PECL
@80/20% - PECL
0.2
0.2
0.3
0.3
0.45
0.45
ns
ns
PECL Levels Test Circuit
PECL Output Skew
OUT
VDD
OUT
50
50
Ω
Ω
2.0V
50%
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 7
(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
LAYOUT RECOMMENDATIONS
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design:
- Keep all the PCB traces to PL580 as short as
possible, as well as keeping all other traces as
far away from it as possible.
backside of the PCB. Going through vias will
reduce the signal integrity, causing additional
jitter and phase noise.
- Place the crystal as close as possible to both
crystal pins of the device. This will reduce the
cross-talk between the crystal and the other
signals.
- Separate crystal pin traces from the other signals
on the PCB, but allow ample distance between
the two crystal pin traces.
- It is highly recommended to keep the VDD and
GND traces as short as possible.
- Please contact PhaseLink for the application note
on how to design outputs driving long traces or
the Gerber files for the PL580 layout.
- Place a 0.01µF~0.1µF decoupling capacitor
between VDD and GND, on the component side
of the PCB, close to the VDD pin. It is not
recommended to place this component on the
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 8
(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
PACKAGE INFORMATION
16-PIN SSOP
16 PIN TSSOP ( mm )
Symbol
Min.
-
Max.
1.20
0.15
0.30
0.20
5.10
4.50
E
H
A
A1
B
C
D
E
0.05
0.19
0.09
4.90
4.30
D
A
H
L
e
A1
C
L
B
e
16-PIN 3x3 QFN
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 9
(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PL580-6X X C L R
PART NUMBER
R= TAPE & REEL
NONE= TUBE
L= GREEN PACKAGE
NONE= REGULAR PACKAGE
PACKAGE TYPE
O=TSSOP
Q= QFN 4x4
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
Order Number
PL580-68OC
PL580-68OC-R
PL580-68OCL
PL580-68OCL-R
PL580-68QC
PL580-68QC-R
PL580-68QCL
PL580-68QCL-R
PL580-69OC
PL580-69OC-R
PL580-69OCL
PL580-69OCL-R
PL580-69QC
Marking
Package Option
TSSOP - Tube
TSSOP - Tape & Reel
TSSOP - Tube (GREEN Package)
TSSOP - Tape & Reel (GREEN Package)
QFN - Tube
P580-68OC
P580-68OC
P580-68OCL
P580-68OCL
P580-68QC
P580-68QC
P580-68QCL
P580-68QCL
P580-69OC
P580-69OC
P580-69OCL
P580-69OCL
P580-69QC
P580-69QC
P580-69QCL
P580-69QCL
QFN - Tape & Reel
QFN - Tube (GREEN Package)
QFN - Tape & Reel (GREEN Package)
TSSOP - Tube
TSSOP - Tape & Reel
TSSOP - Tube (GREEN Package)
TSSOP - Tape & Reel (GREEN Package)
QFN - Tube
QFN - Tape & Reel
QFN - Tube (GREEN Package)
QFN - Tape & Reel (GREEN Package)
PL580-69QC-R
PL580-69QCL
PL580-69QCL-R
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 10
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