PAS109BBB-32 [PIXART]
PAS109BC QQVGA COLOR CMOS IMAGE SENSOR PAS109BB QQVGA MONO CMOS IMAGE SENSOR; PAS109BC QQVGA彩色CMOS图像传感器PAS109BB QQVGA MONO CMOS图像传感器
| 型号： | PAS109BBB-32 |
| 厂家： | 
PIXART IMAGING INC. |
| 描述： | PAS109BC QQVGA COLOR CMOS IMAGE SENSOR PAS109BB QQVGA MONO CMOS IMAGE SENSOR |
| 文件： | 总15页 (文件大小：542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PAS109B
PAS109BC QQVGA COLOR CMOS IMAGE SENSOR
PAS109BB QQVGA MONO CMOS IMAGE SENSOR
General Description
The PAS109B is a color and monochrome digital CMOS image sensor with resolution of 164(H) x 124(V). The
PAS109B outputs 8, 4 , 2 or 1-bit digital raw data or 8-bit formatted data per pixel.
The PAS109B performs automatic gain control, automatic exposure control and automatic de-flicker. The
PAS109B can also be programmed via I2CTM serial control bus. By programming the internal register settings, it
performs on-chip frame rate adjustment, exposure control, offset correction DAC, programmable gain control as
well as output formatting. By proprietary technology, FPN, smear and blooming are drastically reduced.
The PAS109 is available in color or monochrome in 32-pin LCC or 32-pin chip-with-lens package.
Features
Key Specification
ꢀ 164x124 pixels, 1/11” Lens
ꢀ Automatic/Manual exposure-gain control
ꢀ On chip 10-bit ADC
Wide operating supply range
2.4V ~ 3.6V
Power Supply
Array Elements
Optical Format
Pixel Size
164 x 124
1/11 ”
ꢀ On chip PGA
ꢀ On chip 9-bit DAC
ꢀ User selectable output data formats:
7.25µm x 7.25µm
Up to 48MHz
1.5MHz
•
•
8-bit formatted data
8/4/2/1-bit raw data
System Clock
Max. Pixel Rate
FPN
ꢀ Output tri-state through /CSB pin or register
ꢀ AE report
< 0.2% of saturation
2.0V/Lux-sec
16X (24dB)
60fps
ꢀ Horizontal mirror output
ꢀ Flash light application allowable
ꢀ Automatic de-flicker
Sensitivity
PGA Gain
ꢀ External oscillator
ꢀ I2C Interface
Frame Rate
ꢀ Wide operating supply range: 2.4 – 3.6V
ꢀ Low power dissipation: 16mW @ 60fps
ꢀ Low power down dissipation: 200µW
Scan Mode
S/N ratio
Progressive
>40dB
32-pin LCC or 32-pin LCC
chip with lens
Package
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PixArt Imaging Inc.
PAS109B
CMOS Image Sensor IC
1. Pin Assignment
Pin#
Name
Type
Description
Power Supply
28
27
3
2
19
18
1
VDDD
GNDD
VDDA
GNDA
VDDQ
GNDQ
GNDE
P
P
P
P
P
P
P
Digital VDD
Digital Ground
Analog VDD
Analog Ground
Digital VDD
Digital Ground
Ground
Data Interface
17
16
15
12
11
10
9
8
22
23
24
D0
D1
D2
D3
D4
D5
D6
D7
PXCK
O
O
O
O
O
O
O
O
O
O
O
Pixel data output, LSB
Pixel data output
Pixel data output
Pixel data output
Pixel data output
Pixel data output
Pixel data output
Pixel data output, MSB
Pixel clock output
HSYNC
VSYNC
Horizontal Synchronization clock
Vertical Synchronization clock
Analog pin
6
4
5
7
VRT
VCM
VRB
I/O
I/O
I/O
ADC reference voltage, top level
Common mode voltage reference
ADC reference voltage, bottom level
Reference voltage
VDDY1
BYPASS
I2C
25
SCL
SDA
I
I2C interface clock
I2C interface bi-direction data
26
I/O
Misc. Pins
30
CSB
I
Chip select bar, active low
20
14
13
21
29
31
32
SYSCLK
VLRST
NC
I
System clock input pin
Fixed bias input voltage
Not connected
BIAS
-
-
-
-
-
NC
NC
NC
NC
Not connected
Not connected
Not connected
Not connected
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PAS109B
CMOS Image Sensor IC
2. Block Diagram
Voltage
Reference
DAC 9-bit
Imager
D0..D7
Edge detect
Data packing
Data companding
(164x124)
b0..b9
CDS +
ReadOut
10- Bit
ADC
PGA
Column &
Row drive
Gain code
Interface
control
AEC/AGC
Decision
Ex posure
Time
HSYNC
VSYNC
Timing
Control
Clock
Gen.
PXCK
CS
SCL
SDA
I2C
Control register
Block Diagram
Fig 2.1 – Block diagram of PAS109
As the block diagram of PAS109 is shown in Figure 1. By pulling the CSB pin to low, the 164x124 sensor
starts to produce a signal according to the amount of the light integrated in pixels. An entire raw data is then fed
to a CDS readout array to reduce FPN noise and reset noise. A differential signal is then read out serially and fed
to a programmable gain amplifier (PGA) followed by a 10-bit A/D converter.
Voltage reference block generates all necessary voltage and current for sensor array and analog circuit.
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PAS109B
CMOS Image Sensor IC
3. Pixel Array And Pixel Color Pattern
3.1. Pixel array and pixel color pattern
The output image format of PAS109B is QQVGA (164x124 pixel array). To provide the co-processor with the
extra information it needs for interpolation at the edges of the pixel array, an border of 2 pixels on all 4 sides
of the array are available. Fig 3.1. illustrates the pixel array and pixel color pattern.
Dummy row
Row 125
G R G R
G B
G R G R
G R G R
G B
G R G R
Row 124
B
G
B
G
Array: 164(H) x 124(V)
124 rows
B
G B
G
B
G B
G
Row 3
Row 2
G R G R
B
G R G R
B
G B
G
G B
G
Dummy row
Dummy row
Dummy row
Row 0
Row 1
Dark line
Dark line
Dummy row
164 columns
1 column
1column
Fig 3.1. Pixel array and pixel color pattern
Note:
1. Pixel color pattern does not apply to monochrome sensor.
2. Pixel read-out proceeds from left to right, and from bottom row to top row.
3. Pixel array not drawn to scale.
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PAS109B
CMOS Image Sensor IC
4 Output timing:
line time = Hs +4+2+160+2+4 = 194 pixclks
Hsync=22 PXCK
Hsync
B B B
B B B B
2+160+2 raw data
B B B B
B B B B
2+160+2 raw data
PXCLK
Fig. 4.1 Inter-line timing
Vsync.
Frame time (=126 lines)
Vsync
Hsync
Black
Black
Black
Hsync.
Valid frame data (124 lines)
Fig. 4.2 Inter-frame timing (frame time=126 lines)
Frame time (>126 lines)
Vsync
Hsync
Black
Black
Black
Hsync
Valid frame data (124 lines)
Fig. 4.3 Inter-frame timing(frame time>126 lines)
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PAS109B
CMOS Image Sensor IC
5. I2C Bus
PAS109B supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique slave address is
1000000 and supports receiving / transmitting speed up to 400kHz.
5.1 I2C bus overview
ꢀOnly two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected
to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external
pull-up resistors.
ꢀOnly the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop).
ꢀStart and stop condition: A high to low transition of the SDA line while SCL is high defines a start
condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please
refer to Fig 5.1.
ꢀValid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each
byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to
Fig 5.2.
ꢀBoth the master and slave can transmit and receive data from the bus.
ꢀAcknowledge: The receiving device should pull down the SDA line during high period of the SCL clock
line when a complete byte was transferred by transmitter. In the case of a master received data from a
slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master
read cycle.
SDA
SCL
S
P
Start
Condition
Stop
Condition
Fig 5.1 Start and Stop Conditions
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PAS109B
CMOS Image Sensor IC
SDA
SCL
DATA
CHANGE
ALLOWED
DATA
STABLE
Fig 5.2 Valid Data
5.2 Data Transfer Format
5.2.1 Master transmits data to slave (write cycle)
ꢀ S : Start
ꢀ A : Acknowledge by slave
ꢀ P : Stop
ꢀ RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle.
RW=1 read cycle, RW=0 write cycle.
ꢀ SUBADDRESS : The address values of PAS109B internal control registers
(Please refer to PAS109B register description)
1ST BYTE
2ND BYTE
n BYTEs + A
S
SLAVE ID (7 BIT)
RW
A
SUBADDRESS (8 BIT)
A
DATA
A
DATA
A
P
MSB
LSB=0
During write cycle, the master generates start condition and then places the 1st byte data that are combined
slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS109B) issues acknowledgment,
the master places 2nd byte (sub-address) data on SDA line. Again follow the PAS109B acknowledgment, the
master places the 8 bits data on SDA line and transmit to PAS109B control register (address was assigned by
2nd byte). After PAS109B issue acknowledgment, the master can generate a stop condition to end of this write
cycle. In the condition of multi-byte write, the PAS109B sub-address is automatically increment after each
DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value
inside PAS109B can be programming via this way. (Please refer to Fig 5.3.)
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CMOS Image Sensor IC
5.2.2 Slave transmits data to master (read cycle)
ꢀThe sub-address was taken from previous write cycle
ꢀThe sub-address is automatically increment after each byte read
ꢀAm : Acknowledge by master
ꢀNote there is no acknowledgment from master after last byte read
1ST BYTE
2ND BYTE
n BYTE
SLAVE ADDRESS
(7 BITS)
S
RW
A
DATA (8 BIT)
Am DATA
Am
DATA
1
P
NO ACK IN LAST
BYTE
During read cycle, the master generates start condition and then place the 1st byte data that are combined
slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was
also placed on SDA line by PAS109B. The 8 bit data was read from PAS109B internal control register that
address was assigned by previous write cycle. Follow the master acknowledgment, the PAS109B place the next 8
bits data (address is increment automatically) on SDA line and then transmit to master serially. The DATA and
Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead
by keep SDA line high. The slave (PAS109B) must releases SDA line to master to generate STOP condition.
(Please refer to Fig 5.3.)
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
P
S
ACK
from
Receiver
ACK
from
Receiver
Stop
Condition
ACK
from
Receiver
Address
R/W
Data
Data
Start
Condition
Fig 5.3 Data Transfer Format
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PAS109B
CMOS Image Sensor IC
5.3 I2C Bus Timing
SDA
t
BUF
t
HD;STA
tr
t
f
t
t
SP
t
f
t
r
tSU;DAT
t
LOW
SCL
SU;STO
P
S
S
Sr
t
HD;STA
t
SU;STA
t
HD;DAT
t
HIGH
Fig 5.4 I2C Bus Timing
5.4 I2C Bus Timing Specification
STANDARD-MODE
UNIT
PARAMETER
SYMBOL
MIN.
10
MAX.
400
-
SCL clock frequency
kHz
us
f
scl
Hold time (repeated) START condition.
After this period, the first clock pulse is generated.
Low period of the SCL clock
4.0
t
HD:STA
4.7
0.75
4.7
0
-
us
us
us
us
ns
t
t
t
t
t
t
t
t
t
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
r
HIGH period of the SCL clock
-
Set-up time for a repeated START condition
Data hold time. For I2C-bus device
Data set-up time
-
3.45
250
30
-
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START
Capacitive load for each bus line
N.D.
ns(note1)
30
N.D.
ns(note1)
f
4.0
4.7
1
-
-
us
us
pF
V
SU;STO
BUF
15
-
C
b
Noise margin at LOW level for each connected
device (including hysteresis)
Noise margin at HIGH level for each connected
device (including hysteresis)
V
nL
nH
0.1 VDD
0.2 VDD
-
V
V
Note: It depends on the "high" period time of SCL.
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PAS109B
CMOS Image Sensor IC
6. Specifications
Absolute Maximum Ratings
Symbol
Parameter
Min
-0.5
0.5
-0.5
-10
0
Max
3.8
Unit
V
Vdd
DC supply voltage
DC input voltage
Vin
Vdd+0.5
Vdd+0.5
70
V
Vout
V
DC output voltage
℃
℃
Topt1
Topt2
Operating temperature (chip functional)
Operating temperature (guaranteed performance)
40
DC Electrical Characteristics (VDD=3.0V±20%, Ta=10°C~40°C )
Symbol
Parameter
Min.
Typ.
Max. Unit
Type :PWR
VDD
Analog and digital operating voltage
Operating Current
2.4
3.0
8
3.6
V
IDD
mA
uA
Istby
Standby current
100
Type :IN & I/O Reset and SYSCLK
VIH
VIL
Cin
Input voltage HIGH
Input voltage LOW
Input capacitor
2.0
0
VDD
0.8
V
V
10
pF
uA
Ilkg
Input leakage current
TBD
Type : OUT & I/O for PXD0:7, PXCK, H/VSYNC & SDA, load 10pf, 1.2kΩ, 3.0volts
VOH
VOL
Output voltage HIGH
Output voltage LOW
Vdd-0.2
V
V
0.2
AC Operating Condition
Symbol
Parameter
Min.
Typ.
Unit
Max.
48
SYSCLK
PXCK
Master clock frequency
4.5
MHz
MHz
Pixel clock output frequency
1.5
Sensor Characteristics
Parameter
Symbol Min. Typ.
Max.
Unit
%
Note
Photo response non-uniformity
Saturation output voltage
Dark output voltage
PRNU
Vsat.
Vdark
DSNU
R
1.18
1.35
35
V
mV/sec
%
Dark signal non-uniformity
Sensitivity ( Red channel )
Sensitivity ( Green channel )
Sensitivity ( Blue channel )
2.52
2.0
V/Lux-sec
V/Lux-sec
V/Lux-sec
G
2.0
B
1.35
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PAS109B
CMOS Image Sensor IC
7. Package Information
7.1. 32-pin LCC
7.1.1. Pin Connection Diagram
29
30
31
32
1
2
3
4
5
6
VRB
VDDD
28
VRT
GNDD
SDA
27
26
7
8
VDDY1
25
24
SCL
D7
D6
9
VSYNC
HSYNC
23
10
D5
D4
D3
11
12
PXCK
NC
22
21
20
19
18
17
16
15
14
13
-- Bottom View --
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PAS109B
CMOS Image Sensor IC
7.1.2. Package Outline
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PAS109B
CMOS Image Sensor IC
7.2. 32-pin LCC chip with lens package
7.2.1. Pin Connection Diagram
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PAS109B
CMOS Image Sensor IC
7.2.2. Lens Specification & Package Outline
Lens specification:
1.7mm
1.65mm
2.2
EFL
BFL
F no.
52°
Diagonal Field of View
Distortion
IR filter cutoff
-3%
648nm+10nm
Note: Customized lens is available upon request.
Package Outline:
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PAS109B
CMOS Image Sensor IC
8. Ordering Information
Part Number
PAS109BCB-32
PAS109BBB-32
PAS109BCL-32
PAS109BBL-32
Color/Monochrome
Package
32-pin LCC (plastic)
32-pin LCC (plastic)
32-pin LCC chip with lens
32-pin LCC chip with lens
Color
Monochrome
Color
Monochrome
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