PCK2509SADH-T_技术文档

INTEGRATED CIRCUITS

PCK2509S

50–150 MHz 1:9 SDRAM clock driver

Product specification

1999 Oct 19

Philips

Semiconductors

Philips Semiconductors

Product specification

50–150 MHz 1:9 SDRAM clock driver

PCK2509S

adjusted to 50 percent, independent of the duty cycle at CLK. Each

bank of outputs can be enabled or disabled separately via the

control (1G and 2G) inputs. When the G inputs are high, the outputs

switch in phase and frequency with CLK; when the G inputs are low,

the outputs are disabled to the logic–low state.

FEATURES

• Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM

applications

• Spread Spectrum clock compatible

• Operating frequency 50 to 150 MHz

Unlike many products containing PLLs, the PCK2509S does not

require external RC networks. The loop filter for the PLL is included

on-chip, minimizing component count, board space, and cost.

• (t

– jitter) at 100 to133 MHz = ±50 ps

phase error

Because it is based on PLL circuitry, the PCK2509S requires a

stabilization time to achieve phase lock of the feedback signal to the

reference signal. This stabilization time is required, following power up

and application of a fixed-frequency, fixed-phase signal at CLK, and

following any changes to the PLL reference or feedback signals. The

• Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps

• Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps

• Pin-to-pin skew < 200 ps

PLL can be bypassed for test purposes by strapping AV to ground.

CC

• Available in plastic 24-Pin TSSOP

The PCK2509S is characterized for operation from 0°C to +70°C.

• Distributes one clock input to one bank of ten outputs

• External Feedback (FBIN) terminal Is used to synchronize the

PIN CONFIGURATION

outputs to the clock input

• On-Chip series damping resistors

• No external RC network required

• Operates at 3.3 V

CLK

1

2

24

23

22

21

20

19

18

17

16

15

14

13

AGND

V

AV

CC

3

1Y0

1Y1

V

CC

4

2Y0

2Y1

GND

2Y2

• Inputs compatible with 2.5 V and 3.3 V ranges

5

1Y2

6

GND

1Y3

7

DESCRIPTION

8

The PCK2509S is a high-performance, low-skew, low-jitter,

phase-locked loop (PLL) clock driver. It uses a PLLto precisely align,

in both frequency and phase, the feedback (FBOUT) output to the

clock (CLK) input signal. It is specifically designed for use with

9

1Y4

2Y3

V

10

11

CC

V

CC

2G

1G

synchronous DRAMs. The PCK2509S operates at 3.3 V V and is

CC

FBOUT 12

FBIN

input compatible with both 2.5 V and 3.3 V input voltage ranges. It

also provides integrated series-damping resistors that make it ideal

for driving point-to-point loads.

SW00389

One bank of five outputs and one bank of four outputs provide nine

low-skew, low-jitter copies of CLK. Output signal duty cycles are

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

PCK2509S PW

DRAWING NUMBER

24-Pin Plastic TSSOP

0°C to +70°C

SOT355-1

2

1999 Oct 19

853–2180 22544

Philips Semiconductors

Product specification

50–150 MHz 1:9 SDRAM clock driver

PCK2509S

PIN DESCRIPTIONS

PIN NUMBER SYMBOL

TYPE

GND

PWR

NAME, FUNCTION, and DIRECTION

Analog ground. AGND provides the ground reference for the analog circuitry.

Power supply

1

AGND

2, 10, 15, 22

V

CC

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0–4) is enabled

via the1G input. These outputs can be disabled to a logic LOW state by de-asserting the 1G control

input. Each output has an integrated 25 Ω series-damping resistor.

3, 4, 5, 8, 9

6, 7, 18, 19

11

1Y (0–4)

GND

OUT

GND

IN

Ground

Output bank enable. 1G is the output enable for outputs 1Y(0–4). When 1G is LOW, outputs

1Y(0–4) are disabled to a logic LOW state. When 1G is HIGH, all outputs 1Y(0–4) are enabled and

switch at the same frequency as CLK.

1G

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as

CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has

an integrated 25 Ω series-damping resistor.

12

FBOUT

FBIN

OUT

IN

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired

to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is

nominally zero phase error between CLK and FBIN.

13

Output bank enable. 2G is the output enable for outputs 2Y(0–3). When 2G is LOW, outputs

2Y(0–3) are disabled to a logic LOW state. When 2G is HIGH, all outputs 2Y(0–3) are enabled and

switch at the same frequency as CLK.

14

16, 17, 20, 21

23

2G

IN

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0–3) is enabled

via the 2G input. These outputs can be disabled to a logic LOW state by de-asserting the 2G

control input. Each output has an integrated 25 Ω series-damping resistor.

2Y (0–3)

OUT

PWR

Analog power supply. AV provides the power reference for the analog circuitry. In addition,

CC

AV can be used to bypass the PLL for test purposes. When AV is strapped to ground, PLL is

AV

CC

bypassed and CLK is buffered directly to the device outputs.

Clock input. CLK provides the clock signal to be distributed by the PCK2509S clock driver. CLK is

used to provide the reference signal to the integrated PLL that generates the clock output signals.

CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit

is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase

lock the feedback signal to its reference signal.

24

CLK

IN

FUNCTION TABLE

INPUTS

OUTPUTS

1G

X

2G

X

CLK

L

1Y (0–4) 2Y (0–3) FBOUT

L

H

L

H

L

H

L

H

L

H

3

1999 Oct 19

Philips Semiconductors

Product specification

50–150 MHz 1:9 SDRAM clock driver

PCK2509S

FUNCTIONAL BLOCK DIAGRAM

11

1G

3

4

1Y0

1Y1

1Y2

5

8

9

1Y3

1Y4

14

2G

21

20

2Y0

2Y1

24

CLK

17

16

PLL

2Y2

13

FBIN

2Y3

23

AV

CC

12

FBOUT

SW00388

168-pin SDR SDRAM DIMM

BACK SIDE

FRONT SIDE

A[L]VC

PCK2509S

The PLL clock distribution device and A[L]VC registered drivers reduce

signal loads on the memory controller and prevent timing delays and

waveform distortions that would cause unreliable operation

SW00410

4

1999 Oct 19

Philips Semiconductors

Product specification

50–150 MHz 1:9 SDRAM clock driver

PCK2509S

1

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)

LIMITS

MAX

SYMBOL

AV

PARAMETER

CONDITION

UNIT

MIN

–0.5

–65

Supply voltage range

Note 2

< V + 0.7

V

CC

V

CC

I

IK

+4.6

–50

6.5

Input clamp current

V < 0

I

mA

V

I

Input voltage range

Note 3

I

Output clamp current

V

O

> V or V < 0

±50

mA

V

OK

CC

O

V

O

Output voltage range

Notes 3, 4

= 0 to V

CC

V

CC

+ 0.5

I

O

DC output source or sink current

Storage temperature range

Power dissipation per package

V

O

±50

mA

°C

mW

T

STG

+150

700

P

TOT

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. AV must not exceed V

CC

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

4. This value is limited to 4.6 V maximum.

1

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

CONDITIONS

UNIT

MIN

3

MAX

V

CC

, AV

Supply voltage

HIGH level input voltage

3.6

V

CC

V

IH

2

V

IL

LOW level input voltage

0.8

V

Input voltage

0

V

I

CC

T

amb

Operating ambient temperature range in free air

+70

°C

NOTE:

1. Unused inputs must be held high or low to prevent them from floating.

ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range (unless otherwise specified)

TEST CONDITIONS

LIMITS

SYMBOL

PARAMETER

UNIT

AV , V (V)

OTHER

I = –18mA

MIN

TYP

MAX

CC

V

IK

Input clamp voltage

3

–1.2

V

I

MIN to MAX

I

= – 100µA

V

– 0.2

OH

CC

3

I

= – 12mA

2.1

2.4

–

V

OH

HIGH level output voltage

LOW level output voltage

OH

3

I

= – 6mA

= 100µA

= 12mA

OH

MIN to MAX

I

0.2

0.8

0.55

±5

OL

3

I

–

V

OL

V

OL

I

OL

= 6mA

–

I

Input current

3.6

V = V or GND

µA

I

CC

V = V or GND;

= 0, outputs: LOW or HIGH

I

CC

I

Quiescent supply current

3.6

10

50

CC

I

O

I

AV power supply current

AV = 3.3

30

CCA

CC

Additional supply current per

input pin

One input at V – 0.6V;

CC

other inputs at V or GND

∆I

CC

3.3 to 3.6

500

CC

C

Input capacitance

Output capacitance

3.3

V = V or GND

2.8

5.4

pF

I

CC

C

V = V or GND

O CC

O

5

1999 Oct 19

Philips Semiconductors

Product specification

50–150 MHz 1:9 SDRAM clock driver

PCK2509S

TIMING REQUIREMENTS

Over recommended ranges of supply voltage and operating free-air temperature.

SYMBOL

PARAMETER

MIN

50

MAX

150

60

UNIT

MHz

%

f

Clock frequency

CLK

Input clock duty cycle

40

1

Stabilization time

1

ms

NOTE:

1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,

a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation

delay, skew, and jitter parameters given in the switching characteristics table are not applicable.

SWITCHING CHARACTERISTICS

1

Over recommended ranges of supply voltage and operating free-air temperature, C = 30 pF

L

V

, AV = 3.3 V ±0.3 V

CC

FROM

(INPUT)/CONDITION

TO

(OUTPUT)

PARAMETER

UNIT

MIN

–100

–125

–50

TYP

MAX

100

125

50

CLKIN↑ = 100 MHz to 133 MHz

CLKIN↑ = 66 MHz

ps

2

t

FBIN↑

phase error

3

t

, – jitter

phase error

CLKIN↑ = 100 MHz to 133 MHz

Any Y or FBOUT

FBIN↑

4

t

jitter

Any Y or FBOUT

200

80

SK(0)

–80

(peak-peak)

(cycle-cycle)

CLKIN = 66 MHz to 133 MHz

Any Y or FBOUT

ps

|65|

Duty cycle reference

F(CLKIN > 60 MHz)

Any Y or FBOUT

47

2.5

53

1

%

t

r

V

O

V

O

= 0.4 to 2 V

V/ns

t

f

1

NOTES:

1. These parameters are not production tested.

2. This is considered as static phase error.

3. Phase error does not include jitter. (t

= static t

jitter

).

(cycle-cycle)

phase error

phase error –

4. The t

specification is only valid for equal loading of all outputs.

SK(0)

PARAMETER MEASUREMENT INFORMATION

3V

0V

50% V

2V

CC

INPUT

t

pe

FROM OUTPUT

UNDER TEST

V

OH

OL

2V

50% V

CC

OUTPUT

500Ω

0.4V

t

30pF

t

r

f

LOAD CIRCUIT FOR OUTPUTS

NOTES:

VOLTAGE WAVEFORMS & PHASE ERROR TIMES

1.

C includes probe and jig capacitance.

L

2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz, Z = 50Ω , t ≤ 1.2ns, t ≤ 1.2ns.

O

r

f

3. The outputs are measured one at a time with one transition per measurement.

SW00384

Figure 1. Load Circuit and Voltage Waveforms

6

1999 Oct 19

Philips Semiconductors

Product specification

50–150 MHz 1:9 SDRAM clock driver

PCK2509S

CLKIN

FBIN

t

phase error

FBOUT

ANY Y

t

SK(0)

ANY Y

t

SK(0)

SW00385

Figure 2. Phase Error and Skew Calculations

7

1999 Oct 19

Philips Semiconductors

Product specification

50–150 MHz 1:9 SDRAM clock driver

PCK2509S

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

8

1999 Oct 19

Philips Semiconductors

Product specification

50–150 MHz 1:9 SDRAM clock driver

PCK2509S

NOTES

9

1999 Oct 19

Philips Semiconductors

Product specification

50–150 MHz 1:9 SDRAM clock driver

PCK2509S

Data sheet status

[1]

Data sheet

status

Product

status

Definition

Objective

specification

Development

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

Preliminary

specification

Qualification

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make changes at any time without notice in order to

improve design and supply the best possible product.

Product

specification

Production

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 1999

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Date of release: 10-99

Document order number:

9397–750–06505

Philips

Semiconductors

10

1999 Oct 19


型号：	PCK2509SADH-T
厂家：	NXP
描述：	IC PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, PLASTIC, SOT-355, TSSOP-24, Clock Driver 时钟驱动器动态存储器
文件：	总10页 (文件大小：74K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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