PCA9632DP1-T 概述
IC,LASER DIODE/LED DRIVER,TSSOP,8PIN,PLASTIC 显示驱动器
PCA9632DP1-T 规格参数
是否Rohs认证: | 符合 | 生命周期: | Obsolete |
包装说明: | TSSOP, TSSOP8,.19 | Reach Compliance Code: | unknown |
风险等级: | 5.84 | JESD-30 代码: | R-PDSO-G8 |
端子数量: | 8 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | TSSOP | 封装等效代码: | TSSOP8,.19 |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
电源: | 2.5/5 V | 认证状态: | Not Qualified |
子类别: | Display Drivers | 表面贴装: | YES |
温度等级: | INDUSTRIAL | 端子形式: | GULL WING |
端子节距: | 0.635 mm | 端子位置: | DUAL |
Base Number Matches: | 1 |
PCA9632DP1-T 数据手册
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PDF下载PCA9632
4-bit Fm+ I2C-bus low power LED driver
Rev. 03 — 15 July 2008
Product data sheet
1. General description
The PCA9632 is an I2C-bus controlled 4-bit LED driver optimized for
Red/Green/Blue/Amber (RGBA) color mixing applications. The PCA9632 is a drop-in
upgrade for the PCA9633 with 40× power reduction. In Individual brightness control mode,
each LED output has its own 8-bit resolution (256 steps) fixed frequency Individual PWM
controller that operates at 1.5625 kHz with a duty cycle that is adjustable from 0 % to
99.6 % to allow the LED to be set to a specific brightness value. In group dimming mode,
each LED output has its own 6-bit resolution (64 steps) fixed frequency Individual PWM
controller that operates at 6.25 kHz with a duty cycle that is adjustable from 0 % to 98.4 %
to allow the LED to be set to a specific brightness value. A fifth 4-bit resolution (16 steps)
Group PWM controller has a fixed frequency of 190 Hz that is used to dim all the LEDs
with the same value.
While operating in the Blink mode, each LED output has its own 8-bit resolution
(256 steps) fixed frequency Individual PWM controller that operates at 1.5625 kHz with a
duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific
brightness value. Blink rate is controlled by the Group frequency setting that has 8-bit
resolution (256 steps). The blink rate is adjustable between 24 Hz and once every
10.73 seconds. For Group frequency settings between 6 Hz and 24 Hz, the Group PWM
has a 6-bit resolution (64 steps) with a duty cycle that is adjustable from 0 % to 98.4 %.
For Group frequency settings between 6 Hz and 0.09 Hz (once in 10.73 seconds), the
Group PWM has an 8-bit resolution (256 steps) with a duty cycle that is adjustable from
0 % to 99.6 %.
Each LED output can be off, on (no PWM control), set at its Individual PWM controller
value or at both Individual and Group PWM controller values. The LED output driver is
programmed to be either open-drain with a 25 mA current sink capability at 5 V or
totem pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9632 operates with
a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be
directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external
drivers and a minimum amount of discrete components for larger current or higher voltage
LEDs.
The PCA9632 is in the new Fast-mode Plus (Fm+) family. Fm+ devices offer higher
frequency (up to 1 MHz) and more densely populated bus operation (up to 4000 pF).
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCA9632 devices to respond to a common I2C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time or marquee chasing
effect, thus minimizing I2C-bus commands.
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9632
through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to
their default state causing the outputs to be set high-impedance. This allows an easy and
quick way to reconfigure all device registers to the same condition.
2. Features
I 40× power reduction compared to PCA9633
I 4 LED drivers. Each output programmable at:
N Off
N On
N Programmable LED brightness
N Programmable group dimming/blinking mixed with individual LED brightness
I 1 MHz Fast-mode Plus I2C-bus interface with 30 mA high drive capability on SDA
output for driving high capacitive buses
I 256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 1.5625 kHz PWM signal in Individual
brightness mode
I 64-step (6-bit) linear programmable brightness for each LED output varying from fully
off (default) to maximum brightness using a 6.25 kHz PWM signal in group dimming
mode
I In group dimming mode, 16-step group brightness control allows global dimming
(using a 190 Hz PWM signal) from fully off to maximum brightness (default)
I 256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 1.5625 kHz PWM signal in group blinking
mode
I 64-step group blinking with frequency programmable from 24 Hz to 6 Hz and
duty cycle from 0 % to 98.4 %
I 256-step group blinking with frequency programmable from 6 Hz to 0.09 Hz (10.73 s)
and duty cycle from 0 % to 99.6 %
I Four totem pole outputs (sink 25 mA and source 10 mA at 5 V) with software
programmable open-drain LED outputs selection (default at high-impedance). No input
function.
I 10-pin package option provides two hardware address pins allowing four devices to
operate on the same bus
I Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).
I Software Reset feature (SWRST Call) allows the device to be reset through the
I2C-bus
I 400 kHz internal oscillator requires no external components
I Internal power-on reset
I Noise filter on SDA/SCL inputs
I Edge rate control on outputs
I No glitch on power-up
I Supports hot insertion
I Low standby current of < 1 µA
I Operating power supply voltage range of 2.3 V to 5.5 V
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
2 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
I 5.5 V tolerant inputs
I −40 °C to +85 °C operation
I ESD protection exceeds 5000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: TSSOP8, TSSOP10, HVSON8, HVSON10
3. Applications
I RGB or RGBA LED drivers for color mixing
I LED status information
I LED displays
I LCD backlights
I Keypad backlights for cellular phones or handheld devices
4. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA9632DP1
PCA9632DP2
PCA9632TK
PCA9632TK2
9632
9632
9632
9632
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
TSSOP10 plastic thin shrink small outline package; 10 leads;
body width 3 mm
SOT552-1
SOT908-1
SOT650-1
HVSON8
plastic thermal enhanced very thin small outline package;
no leads; 8 terminals; body 3 × 3 × 0.85 mm
HVSON10 plastic thermal enhanced very thin small outline package;
no leads; 10 terminals; body 3 × 3 × 0.85 mm
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
3 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
5. Block diagram
10-pin version
A0 A1
PCA9632
SCL
INPUT FILTER
SDA
2
I C-BUS
CONTROL
POWER-ON
RESET
V
V
DD
DD
V
SS
LED
STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
LEDn
24 Hz
to
0.09 Hz
6.25 kHz/
1.56 kHz
MUX/
CONTROL
GRPFREQ
REGISTER
GRPPWM
400 kHz
OSCILLATOR
REGISTER
190 Hz
'0' – permanently OFF
'1' – permanently ON
002aad039
Fig 1. Block diagram of PCA9632
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
4 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
6. Pinning information
6.1 Pinning
1
2
3
4
5
10
9
LED0
LED1
LED2
LED3
A0
V
DD
1
2
3
4
8
7
6
5
LED0
LED1
LED2
LED3
V
DD
SDA
SCL
A1
SDA
SCL
8
PCA9632DP2
PCA9632DP1
7
V
SS
6
V
SS
002aad040
002aad637
Fig 2. Pin configuration for TSSOP8
Fig 3. Pin configuration for TSSOP10
terminal 1
index area
terminal 1
index area
1
2
3
4
5
10
9
LED0
LED1
LED2
LED3
A0
V
DD
1
2
3
4
8
7
6
5
LED0
LED1
LED2
LED3
V
DD
SDA
SCL
A1
SDA
SCL
8
PCA9632TK2
PCA9632TK
7
V
6
V
SS
SS
002aad638
002aad041
Transparent top view
Transparent top view
Fig 4. Pin configuration for HVSON8
Fig 5. Pin configuration for HVSON10
6.2 Pin description
Table 2.
Symbol
LED0
LED1
LED2
LED3
VSS
Pin description for TSSOP8 and HVSON8
Pin
1
Type
Description
LED driver 0
LED driver 1
LED driver 2
LED driver 3
O
2
O
3
O
4
O
5[1]
power supply
supply ground
serial clock line
serial data line
supply voltage
SCL
6
I
SDA
7
I/O
VDD
8
power supply
[1] HVSON8 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
5 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
Table 3.
Pin description for TSSOP10 and HVSON10
Symbol
LED0
LED1
LED2
LED3
A0
Pin
1
Type
Description
LED driver 0
LED driver 1
LED driver 2
LED driver 3
O
2
O
3
O
4
O
5
6[1]
I
address input 0
supply ground
address input 1
serial clock line
serial data line
supply voltage
VSS
power supply
A1
7
I
SCL
SDA
VDD
8
I
9
I/O
10
power supply
[1] HVSON10 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
7. Functional description
Refer to Figure 1 “Block diagram of PCA9632”.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
There are a maximum of 4 possible programmable addresses using the 2 hardware
address pins for the 10-pin version and just one fixed address for the 8-pin version.
7.1.1 Regular I2C-bus slave address
The I2C-bus slave address of the PCA9632 is shown in Figure 6. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW (10-pin versions only).
Remark: Using reserved I2C-bus addresses will interfere with other devices, but only if the
devices are on the bus and/or the bus will be open to other I2C-bus systems at some later
date. In a closed system where the designer controls the address assignment these
addresses can be used since the PCA9632 treats them like any other address. The
LED All Call, Software Reset and PCA9564 or PCA9665 slave address (if on the bus) can
never be used for individual device addresses.
• PCA9632 LED All Call address (1110 000) or Software Reset (0000 0110) which are
active on start-up
• PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on
start-up
• ‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX)
• slave devices that use the 10-bit addressing scheme (1111 0XX)
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
6 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
• slave devices that are designed to respond to the General Call address (0000 000)
• High-speed mode (Hs-mode) master code (0000 1XX)
slave address
slave address
1
1
0
0
0
A1 A0 R/W
1
1
0
0
0
1
0
R/W
fixed
hardware
selectable
fixed
002aab318
002aab295
a. 8-pin version
b. 10-pin version
Fig 6. Slave address
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
7.1.2 LED All Call I2C-bus address
• Default power-up value (ALLCALLADR register): E0h or 1110 000
• Programmable through I2C-bus (volatile programming)
• At power-up, LED All Call I2C-bus address is enabled. PCA9632 sends an ACK when
E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.
See Section 7.3.8 “LED All Call I2C-bus address, ALLCALLADR” for more detail.
Remark: The default LED All Call I2C-bus address (E0h or 1110 000) must not be used
as a regular I2C-bus slave address since this address is enabled at power-up. All the
PCA9632s on the I2C-bus will acknowledge the address if sent by the I2C-bus master.
7.1.3 LED Sub Call I2C-bus addresses
• 3 different I2C-bus addresses can be used
• Default power-up values:
– SUBADR1 register: E2h or 1110 001
– SUBADR2 register: E4h or 1110 010
– SUBADR3 register: E8h or 1110 100
• Programmable through I2C-bus (volatile programming)
• At power-up, Sub Call I2C-bus addresses are disabled. PCA9632 does not send an
ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or
E8h (R/W = 0) or E9h (R/W = 1) is sent by the master.
See Section 7.3.7 “I2C-bus subaddress 1 to 3, SUBADRx” for more detail.
Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus
slave addresses as long as they are disabled.
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
7 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
7.1.4 Software reset I2C-bus address
The address shown in Figure 7 is used when a reset of the PCA9632 needs to be
performed by the master. The Software Reset address (SWRST Call) must be used with
R/W = 0. If R/W = 1, the PCA9632 does not acknowledge the SWRST. See Section 7.5
“Software reset” for more detail.
R/W
0
0
0
0
0
1
1
0
002aab416
Fig 7. Software reset address
Remark: The Software Reset I2C-bus address is a reserved address and cannot be used
as a regular I2C-bus slave address or as an LED All Call or LED Sub Call address.
7.2 Control register
Following the successful acknowledgement of the slave address, LED All Call address or
LED Sub Call address, the bus master will send a byte to the PCA9632, which will be
stored in the Control register.
The lowest 4 bits are used as a pointer to determine which register will be accessed
(D[3:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options
(AI[2:0]). Bit 4 is unused and must be programmed with zero (0) for proper device
operation.
register address
AI2 AI1 AI0
0
D3 D2 D1 D0
002aab296
Auto-Increment options
Auto-Increment flag
reset state = 80h
Remark: The Control register does not apply to the Software Reset I2C-bus address.
Fig 8. Control register
When the Auto-Increment flag is set (AI2 = 1), the four low order bits of the Control
register are automatically incremented after a read or write. This allows the user to
program the registers sequentially. Four different types of Auto-Increment are possible,
depending on AI1 and AI0 values.
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
8 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
Table 4.
Auto-Increment options
AI2
0
AI1
0
AI0
0
Function
no Auto-Increment
1
0
0
Auto-Increment for all registers. D3, D2, D1, D0 roll over to ‘0000’ after
the last register (1100) is accessed.
1
1
1
0
1
1
1
0
1
Auto-Increment for Individual brightness registers only. D3, D2, D1, D0
roll over to ‘0010’ after the last register (0101) is accessed.
Auto-Increment for global control registers only. D3, D2, D1, D0 roll over
to ‘0110’ after the last register (0111) is accessed.
Auto-Increment for individual and global control registers only. D3, D2,
D1, D0 roll over to ‘0010’ after the last register (0111) is accessed.
Remark: Other combinations not shown in Table 4 (AI[2:0] = 001, 010, and 011) are
reserved and must not be used for proper device operation.
AI[2:0] = 000 is used when the same register must be accessed several times during a
single I2C-bus communication, for example, changes the brightness of a single LED. Data
is overwritten each time the register is accessed during a write operation.
AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example,
power-up programming.
AI[2:0] = 101 is used when the four LED drivers must be individually programmed with
different values during the same I2C-bus communication, for example, changing color
setting to another color setting.
AI[2:0] = 110 is used when the LED drivers must be globally programmed with different
settings during the same I2C-bus communication, for example, global brightness or
blinking change.
AI[2:0] = 111 is used when individual and global changes must be performed during the
same I2C-bus communication, for example, changing a color and global brightness at the
same time.
Only the 4 least significant bits D[3:0] are affected by the AI[2:0] bits.
When the Control register is written, the register entry point determined by D[3:0] is the
first register that will be addressed (read or write operation), and can be anywhere
between 0000 and 1100 (as defined in Table 5). When AI[2] = 1, the Auto-Increment flag
is set and the rollover value at which the point where the register increment stops and
goes to the next one is determined by AI[2:0]. See Table 4 for rollover values. For
example, if the Control register = 1110 1000 (E8h), then the register addressing sequence
will be (in hex):
08 → … → 0C → 00 → … → 07 → 02 → … → 07 → 02 → … → 07 → 02 → … as long
as the master keeps sending or reading data.
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
9 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
7.3 Register definitions
Table 5.
Register summary
Only D[3:0] = 0000 to 1100 are allowed and will be acknowledged. D[3:0] = 1101, 1110, or 1111 are reserved and will not be
acknowledged.
When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation.
Register number (hex) D3
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
Name
Type
Function
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0
0
0
0
0
0
0
0
1
1
1
1
1
MODE1
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
Mode register 1
MODE2
Mode register 2
PWM0
brightness control LED0
brightness control LED1
brightness control LED2
brightness control LED3
group duty cycle control
group frequency
PWM1
PWM2
PWM3
GRPPWM
GRPFREQ
LEDOUT
SUBADR1
SUBADR2
SUBADR3
ALLCALLADR
LED output state
I2C-bus subaddress 1
I2C-bus subaddress 2
I2C-bus subaddress 3
LED All Call I2C-bus address
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
10 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
7.3.1 Mode register 1, MODE1
Table 6.
MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
0
Description
7
AI2
read only
Register Auto-Increment disabled
1*
0*
1
Register Auto-Increment enabled
6
5
4
3
2
1
0
AI1
read only
read only
R/W
Auto-Increment bit 1 = 0
Auto-Increment bit 1 = 1
AI0
0*
1
Auto-Increment bit 0 = 0
Auto-Increment bit 0 = 1
Normal mode[1].
Low power mode. Oscillator off[2].
SLEEP
SUB1
SUB2
SUB3
ALLCALL
0
1*
0*
1
R/W
PCA9632 does not respond to I2C-bus subaddress 1.
PCA9632 responds to I2C-bus subaddress 1.
PCA9632 does not respond to I2C-bus subaddress 2.
PCA9632 responds to I2C-bus subaddress 2.
PCA9632 does not respond to I2C-bus subaddress 3.
PCA9632 responds to I2C-bus subaddress 3.
PCA9632 does not respond to LED All Call I2C-bus address.
PCA9632 responds to LED All Call I2C-bus address.
R/W
0*
1
R/W
0*
1
R/W
0
1*
[1] It takes 500 µs max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not
guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 µs window.
[2] When the oscillator is off (Sleep mode), the LED outputs cannot be turned on, off or dimmed/blinked.
7.3.2 Mode register 2, MODE2
Table 7.
MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit
7
Symbol
Access
read only
read only
R/W
Value
0*
0*
0*
1
Description
-
reserved
6
-
reserved
5
DMBLNK
Group control = dimming
Group control = blinking
4
3
2
INVRT[1]
OCH
R/W
R/W
R/W
0*
1
Output logic state not inverted. Value to use when no external driver used.
Output logic state inverted. Value to use when external driver used.
Outputs change on STOP command.[2]
Outputs change on ACK.
0*
1
OUTDRV[1]
0*
1
The 4 LED outputs are configured with an open-drain structure.
The 4 LED outputs are configured with a totem pole structure.
unused
1 to 0 OUTNE[1:0] R/W
01*
[1] See Section 7.6 “Using the PCA9632 with and without external drivers” for more details. Normal LEDs can be driven directly in either
mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI, protect the LEDs, and these must be
driven only in the open-drain mode to prevent overheating the IC.
[2] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9632. Applicable to registers from
02h (PWM0) to 08h (LEDOUT) only.
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
11 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
7.3.3 PWM registers 0 to 3, PWMx — Individual brightness control registers
Table 8.
PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description
Legend: * default value.
Address Register Bit
Symbol
Access Value
Description
02h
03h
04h
05h
PWM0
PWM1
PWM2
PWM3
7:0
7:0
7:0
7:0
IDC0[7:0]
IDC1[7:0]
IDC2[7:0]
IDC3[7:0]
R/W
R/W
R/W
R/W
0000 0000* PWM0 Individual Duty Cycle
0000 0000* PWM1 Individual Duty Cycle
0000 0000* PWM2 Individual Duty Cycle
0000 0000* PWM3 Individual Duty Cycle
While operating in Individual brightness mode (LDRx = 10), a 1.5625 kHz fixed frequency
signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum
brightness). In this mode, all the 8 bits are used.
IDCx[7:0]
duty cycle =
(1)
---------------------------
256
E.g., if IDCx[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %.
While operating in group dimming mode, a 6.25 kHz fixed frequency signal is used for
each output. Duty cycle is controlled through 64 linear steps from 00h (0 % duty cycle =
LED output off) to 3Fh (98.4 % duty cycle = LED output at maximum brightness). In this
mode only the 6 MSBs are used (IDCx[7:2]). The 2 LSBs IDCx[1:0] are ignored.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
IDCx[7:2],00
duty cycle =
(2)
-----------------------------------
256
E.g., if IDCx[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %.
While operating in blink mode, a 1.5625 kHz fixed frequency signal is used for each
output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED
output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). In this mode,
all the 8 bits are used.
IDCx[7:0]
duty cycle =
(3)
---------------------------
256
E.g., if IDCx[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
PCA9632_3
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Product data sheet
Rev. 03 — 15 July 2008
12 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
7.3.4 Group duty cycle control, GRPPWM
Table 9.
GRPPWM - Group duty cycle control register (address 06h) bit description
Legend: * default value.
Address Register
Bit Symbol
Access Value
Description
06h
GRPPWM
7:0 GDC[7:0]
R/W 1111 1111 GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency
signal is superimposed with the 6.25 kHz Individual brightness control signal. GRPPWM
is then used as a global brightness control allowing the LED outputs to be dimmed with
the same value. The value in GRPFREQ is then a ‘don’t care’.
In the group dimming mode (DMBLNK = 0) global brightness for the 4 outputs is
controlled through 16 linear steps from 00h (0 % duty cycle = LED output off) to F0h
(93.75 % duty cycle = maximum brightness). In this mode only the 4 MSBs of the
GRPPWM[7:4] are used. Bits GRPPWM[3:0] are unused.
GDC[7:4],0000
duty cycle =
(4)
----------------------------------------
256
E.g., if GDC[7:4] = 1111, then duty cycle = 1111 0000 / 256 = 240 / 256 = 93.75 %.
When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define a
global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to
10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
In this mode, when GRPFREQ is programmed to provide a blinking with frequency
programmable from 24 Hz to 6 Hz, GRPPWM[7:2] is used to provide 64-step duty cycle
resolution from 0 % to 98.4 %. GRPPWM[1:0] bits are unused.
GDC[7:2],00
duty cycle =
(5)
----------------------------------
256
E.g., if GDC[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %.
When GRPFREQ is programmed to provide a blinking with frequency programmable from
6 Hz to 0.09 Hz (10.73 s), GRPPWM[7:0] is used to provide a 256-step duty cycle
resolution from 0 % to 99.6 %. In this case, all the 8 bits of the GRPPWM register are
used.
GDC[7:0]
duty cycle =
(6)
--------------------------
256
E.g., If GDC[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
PCA9632_3
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Product data sheet
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PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
7.3.5 Group frequency, GRPFREQ
Table 10. GRPFREQ - Group frequency register (address 07h) bit description
Legend: * default value.
Address Register
Bit Symbol
Access Value
Description
07h GRPFREQ 7:0 GFRQ[7:0] R/W
0000 0000* GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to logic 1. Value in this register is a ‘don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 seconds).
GFRQ[7:0] + 1
global blinking period =
(in seconds)
(7)
---------------------------------------
24
7.3.6 LED driver output state, LEDOUT
Table 11. LEDOUT - LED driver output state register (address 08h) bit description
Legend: * default value.
Address Register
08h LEDOUT
Bit Symbol
7:6 LDR3
5:4 LDR2
3:2 LDR1
1:0 LDR0
Access Value
Description
R/W
R/W
R/W
R/W
00*
00*
00*
00*
LED3 output state control
LED2 output state control
LED1 output state control
LED0 output state control
LDRx = 00 — LED driver x is off (default power-up state).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled).
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
7.3.7 I2C-bus subaddress 1 to 3, SUBADRx
Table 12. SUBADR1 to SUBADR3 - I2C-bus subaddress registers 0 to 3 (address 09h to
0Bh) bit description
Legend: * default value.
Address Register
Bit
7:1
0
Symbol
A1[7:1]
A1[0]
Access Value
Description
1110 001* I2C-bus subaddress 1
0* reserved
1110 010* I2C-bus subaddress 2
0* reserved
1110 100* I2C-bus subaddress 3
0* reserved
09h
0Ah
0Bh
SUBADR1
SUBADR2
SUBADR3
R/W
R only
R/W
7:1
0
A2[7:1]
A2[0]
R only
R/W
7:1
0
A3[7:1]
A3[0]
R only
Subaddresses are programmable through the I2C-bus. Default power-up values are E2h,
E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up
(the corresponding SUBx bit in MODE1 register is equal to logic 0).
PCA9632_3
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Product data sheet
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PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
Once subaddresses have been programmed to their right values, SUBx bits need to be
set to 1 in order to have the device acknowledging these addresses (MODE1 register).
Only the 7 MSBs representing the I2C-bus subaddress are valid. The LSB in SUBADRx
register is a read-only bit (0).
When SUBx is set to 1, the corresponding I2C-bus subaddress can be used during either
an I2C-bus read or write sequence.
7.3.8 LED All Call I2C-bus address, ALLCALLADR
Table 13. ALLCALLADR - LED All Call I2C-bus address register (address 0Ch) bit
description
Legend: * default value.
Address Register
Bit
Symbol Access Value
Description
0Ch
ALLCALLADR 7:1
AC[7:1]
R/W
1110 000* ALLCALL I2C-bus
address register
0
AC[0]
R only
0*
reserved
The LED All Call I2C-bus address allows all the PCA9632s in the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default
state). This address is programmable through the I2C-bus and can be used during either
an I2C-bus read or write sequence. The register address can be programmed as a
sub call.
Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register
ALLCALLADR.
7.4 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9632 in a reset
condition until VDD has reached VPOR. At this point, the reset condition is released and the
PCA9632 registers and I2C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below
0.2 V to reset the device.
7.5 Software reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to
the power-up state value through a specific formatted I2C-bus command. To be performed
correctly, it implies that the I2C-bus is functional and that there is no device hanging the
bus.
The SWRST Call function is defined as the following:
1. A START command is sent by the I2C-bus master.
2. The reserved SWRST I2C-bus address ‘0000 011’ with the R/W bit set to 0 (write) is
sent by the I2C-bus master.
3. The PCA9632 device(s) acknowledge(s) after seeing the SWRST Call address
‘0000 0110’ (06h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to
the I2C-bus master.
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Product data sheet
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PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
4. Once the SWRST Call address has been sent and acknowledged, the master sends
2 bytes with 2 specific values (SWRST data byte 1 and byte 2):
a. Byte 1 = A5h: the PCA9632 acknowledges this value only. If byte 1 is not equal to
A5h, the PCA9632 does not acknowledge it.
b. Byte 2 = 5Ah: the PCA9632 acknowledges this value only. If byte 2 is not equal to
5Ah, then the PCA9632 does not acknowledge it.
If more than 2 bytes of data are sent, the PCA9632 does not acknowledge any more.
5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and
correctly acknowledged, the master sends a STOP command to end the SWRST Call:
the PCA9632 then resets to the default value (power-up value) and is ready to be
addressed again within the specified bus free time (tBUF).
The I2C-bus master must interpret a non-acknowledge from the PCA9632 (at any time) as
a ‘SWRST Call Abort’. The PCA9632 does not initiate a reset of its registers. This
happens only when the format of the SWRST Call sequence is not correct.
7.6 Using the PCA9632 with and without external drivers
The PCA9632 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5 V.
If the device needs to drive LEDs to a higher voltage and/or higher current, use of an
external driver is required.
• INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the
same (PWMx and GRPPWM values directly calculated from their respective formulas
and the LED output state determined by LEDOUT register value) independently of the
type of external driver.
• OUTDRV bit (MODE2 register) allows minimizing the amount of external components
required to control the external driver (N-type or P-type device).
Table 14. Use of INVRT and OUTDRV based on connection to the LEDn outputs
INVRT OUTDRV Direct connection to LEDn
External N-type driver
External P-type driver
Firmware External
Firmware
External
Firmware External
pull-up
pull-up
pull-up
resistor
resistor
resistor
0
0
1
1
0
1
0
1
formulas and LED
output state values
apply[1]
LED current formulas and LED required
limiting R[1] output state
values inverted
formulas and LED required
output state values
apply
formulas and LED
output state values
apply[1]
LED current formulas and LED not required formulas and LED not
limiting R[1] output state
values inverted
output state values required[3]
apply[3]
formulas and LED
output state values
inverted
LED current formulas and LED required
formulas and LED required
output state values
inverted
limiting R
output state
values apply
formulas and LED
output state values
inverted
LED current formulas and LED not
formulas and LED not required
output state values
inverted
limiting R
output state
values apply[2]
required[2]
[1] Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through current limiting resistor).
[2] Optimum configuration when external N-type (NPN, NMOS) driver used.
[3] Optimum configuration when external P-type (PNP, PMOS) driver used.
PCA9632_3
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Product data sheet
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PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
Table 15. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits
LEDOUT
INVRT OUTDRV Upper transistor Lower transistor (LEDn to
LEDn state
(VDD to LEDn)
VSS
off
off
on
on
on
on
off
off
)
00
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
off
on
off
off
off
off
off
on
off
high-Z[1]
VDD
LED driver off
VSS
VSS
01
VSS
LED driver on
VSS
high-Z[1]
VDD
10
Individual PWM (non-inverted) VSS or high-Z[1] = PWMx value
Individual
brightness
control
Individual PWM
(non-inverted)
Individual PWM (non-inverted) VSS or VDD = PWMx value
1
1
0
1
off
Individual PWM (inverted)
Individual PWM (inverted)
high-Z[1] or VSS = 1 − PWMx value
VDD or VSS = 1 − PWMx value
Individual PWM
(inverted)
11
0
0
1
1
0
1
0
1
off
Individual + Group PWM
(non-inverted)
VSS or high-Z[1]
PWMx/GRPPWM values
=
Individual +
group
dimming/
blinking
Individual PWM
(non-inverted)
Individual PWM (non-inverted) VSS or VDD = PWMx/GRPPWM
values
off
Individual + Group PWM
(inverted)
high-Z[1] or VSS = (1 − PWMx) or
(1 − GRPPWM) values
Individual PWM
(inverted)
Individual PWM (inverted)
VDD or VSS = (1 − PWMx) or
(1 − GRPPWM) values
[1] External pull-up or LED current limiting resistor connects LEDn to VDD
.
7.7 Individual brightness control with group dimming/blinking
A 1.5625 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is
used to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 4 LED outputs):
• A lower 190 Hz fixed frequency signal with programmable duty cycle (4 bits, 16 steps)
is used to provide a global brightness control.
• A programmable frequency signal from 24 Hz to 1⁄10.73 Hz (8 bits, 256 steps) with
programmable duty cycle (6 bits, 64 steps) is used to provide a global blinking control
for (24 Hz to 6 Hz) and (8 bits, 256 steps) for (6 Hz to 1⁄10.73 Hz).
PCA9632_3
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Product data sheet
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17 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
508
510
512
1
2
3
4
5
6
7
8
9
10 11 12
507
509
511
1
2
3
4
5
6
7
8
9
10 11
brightness control signal (LEDn)
N × 2.5 µs
with N = (0 to 256)
(PWMx Register)
256 × 2.5 µs = 640 µs
(1.5625 kHz)
002aad101
Minimum pulse width for LEDn brightness control is 2.5 µs.
Fig 9. Individual LED brightness control signals
508
510
512
1
2
3
4
5
6
7
8
9
10 11 12
507
509
511
1
2
3
4
5
6
7
8
9 10 11
brightness control signal (LEDn)
N × 2.5 µs
with N = (0 to 64)
(PWMx Register)
M × 16 × 2 × 2.5 µs
with M = (1 to 16)
(GRPPWM Register)
64 × 2.5 µs = 160 µs
(6.25 kHz)
group dimming signal
16 × 2 × 256 × 2.5 µs = 5.24 ms (190.7 Hz)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
002aad042
resulting brightness + group dimming signal
Minimum pulse width for LEDn brightness control is 2.5 µs.
Minimum pulse width for group dimming is 80 µs.
When M = 1 (GRPPWM register value), the resulting LEDn brightness control + group dimming signal will have 2 pulses of the
LED brightness control signal (pulse width = N × 2.5 µs, with ‘N’ defined in PWMx register).
Fig 10. Brightness + group dimming signals
Table 16. Dimming and blinking resolution
Type of control
LDRx DMBLNK GRPPWM GRPFREQ Frequency
PWMx
Individual LED brightness 10
without dimming
X
0
1
X
X
1.5625 kHz
256 steps
Individual LED brightness 11
with global dimming
16 steps
64 steps
X
190 Hz with 6.25 kHz modulation 64 steps
Blinking (fast)
11
256 steps
blink frequency = 6 Hz to 24 Hz
PWMx frequency = 1.5625 kHz
256 steps
Blinking (slow)
11
1
256 steps
256 steps
blink frequency = 0.09 Hz to 6 Hz 256 steps
PWMx frequency = 1.5625 kHz
PCA9632_3
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Product data sheet
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18 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 11).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 11. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 12).
SDA
SCL
SDA
SCL
S
P
STOP condition
START condition
mba608
Fig 12. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 13).
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Product data sheet
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PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
SDA
SCL
SLAVE
TRANSMITTER/
RECEIVER
MASTER
2
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
I C-BUS
TRANSMITTER/
MULTIPLEXER
RECEIVER
SLAVE
002aaa966
Fig 13. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
8
9
S
clock pulse for
START
condition
acknowledgement
002aaa987
Fig 14. Acknowledgement on the I2C-bus
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PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
9. Bus transactions
(1)
(2)
slave address
control register
D3 D2 D1 D0
data for register D3, D2, D1, D0
S
1
1
0
0
0
A1 A0
0
A
X
X
X
0
A
A
P
Auto-Increment options
Auto-Increment flag
START condition
R/W
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
STOP
condition
002aad043
(1) 10-pin version only.
(2) See Table 5 for register definition.
Fig 15. Write to a specific register
(1)
slave address
control register
MODE1 register
MODE2 register
(cont.)
S
1
1
0
0
0
A1 A0
0
A
1
0
0
0
0
0
0
0
A
A
A
MODE1
register
selection
Auto-Increment
on all registers
acknowledge
from slave Auto-Increment on
START condition
R/W
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
SUBADR3 register
ALLCALLADR register
(cont.)
A
A
P
acknowledge
from slave
acknowledge
from slave
STOP
condition
002aad044
(1) 10-pin version only.
Fig 16. Write to all registers using the Auto-Increment feature
PCA9632_3
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Product data sheet
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PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
(1)
slave address
control register
PWM0 register
PWM1 register
(cont.)
S
1
1
0
0
0
A1 A0
0
A
1
0
1
0
0
0
1
0
A
A
A
PWM0
register
selection
increment
START condition
R/W
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
on Individual
brightness
acknowledge
from slave
registers only
Auto-Increment on
PWM3 register
PWM2 register
PWM0 register
PWMx register
(cont.)
A
A
A
A
P
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
STOP
condition
002aad045
(1) 10-pin version only.
Fig 17. Multiple writes to Individual brightness registers only using the Auto-Increment feature
ReSTART
condition
(1)
slave address
control register
slave address
data from MODE1 register
(cont.)
S
1
1
0
0
0
A1 A0
0
A
1
0
0
0
0
0
0
0
A
Sr A6 A5 A4 A3 A2 A1 A0
1
A
A
MODE1
register
selection
Auto-Increment
on all registers
acknowledge
from slave Auto-Increment on
START condition
R/W
acknowledge
from slave
R/W
acknowledge
from master
acknowledge
from slave
data from
ALLCALLADR register
data from
MODE1 register
data from MODE2 register
data from PWM0
(cont.)
A
(cont.)
A
A
A
acknowledge
from master
acknowledge
from master
acknowledge
from master
acknowledge
from master
data from last read byte
(cont.)
A
P
not acknowledge STOP
from master condition
002aad046
(1) 10-pin version only.
Fig 18. Read all registers using the Auto-Increment feature
PCA9632_3
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Product data sheet
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PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
(1)
2
(2)
slave address
control register
new LED All Call I C-bus address
sequence (A)
S
1
1
0
0
0
A1 A0
0
A
X
X
X
0
1
1
0
0
A
1
0
1
0
1
0
1
X
A
P
ALLCALLADR
START condition
R/W
acknowledge
from slave
acknowledge
from slave
register selection
acknowledge
from slave
Auto-Increment on
STOP
condition
(3)
the 16 LEDs are on at the acknowledge
LEDOUT register (LED fully ON)
2
LED All Call I C-bus address
control register
sequence (B)
S
1
0
1
0
1
0
1
0
A
X
X
X
0
1
0
0
0
A
0
1
0
1
0
1
0
1
A
P
LEDOUT
register selection
START condition
R/W
acknowledge
from the
4 devices
acknowledge
from the
acknowledge
from the
4 devices
STOP
condition
4 devices
002aad047
(1) 10-pin version is used for this figure. Four PCA9632DP2 or PCA9632TK2 and same sequence (A) (above) is sent to each of
them. A[1:0] = 00 to 11.
(2) ALLCALL bit in MODE1 register is equal to logic 1 for this example.
(3) OCH bit in MODE2 register is equal to logic 1 for this example.
Fig 19. LED All Call I2C-bus address programming and LED All Call sequence example
SWRST data
Byte 1 = A5h
SWRST data
Byte 2 = 5Ah
2
SWRST Call I C address
S
0
0
0
0
0
1
1
0
A
1
0
1
0
0
1
0
1
A
0
1
0
1
1
0
1
0
A
P
START condition
R/W
acknowledge
from slave(s)
acknowledge
from slave(s)
acknowledge
from slave(s)
PCA9632 is(are) reset.
Registers are set to default power-up values.
002aad048
Fig 20. Software Reset (SWRST) Call sequence
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
23 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
10. Application design-in information
5 V
12 V
V
= 2.5 V, 3.3 V or 5.0 V
DD
10 kΩ
10 kΩ
2
I C-BUS/SMBus
MASTER
SDA
V
DD
SDA
SCL
LED0
SCL
LED1
LED2
A0
A1
PCA9632
LED3
V
SS
002aad049
I2C-bus address = 1100 001X.
All of the 4 LED outputs configurable as either open-drain or totem pole. Mixing of configurations is
not possible.
Fig 21. Typical application
Question 1: What kind of edge rate control is there on the outputs?
• The typical edge rates depend on the output configuration, supply voltage, and the
applied load. The outputs can be configured as either open-drain NMOS or totem pole
outputs. If the customer is using the part to directly drive LEDs, they should be using it
in an open-drain NMOS, if they are concerned about the maximum ISS and ground
bounce. The edge rate control was designed primarily to slow down the turn-on of the
output device; it turns off rather quickly (~ 1.5 ns). In simulation, the typical turn-on
time for the open-drain NMOS was ~ 14 ns (VDD = 3.6 V; CL = 50 pF; RPU = 500 Ω).
Question 2: Is ground bounce possible?
• Ground bounce is a possibility, especially if all 16 outputs transition at full current
(25 mA each). There is a fair amount of decoupling capacitance on chip (~ 50 pF),
which is intended to suppress some of the ground bounce. The customer will need to
determine if additional decoupling capacitance externally placed as close as
physically possible to the device is required.
Question 3: Can I really sink 400 mA through the single ground pin on the package and
will this cause any ground bounce problem due to the PWM of the LEDs?
• Yes, you can sink 400 mA through a single ground pin on the package. Although the
package only has one ground pin, there are two ground pads on the die itself
connected to this one pin. Although some ground bounce is likely, it will not disrupt the
operation of the part and would be reduced by the external decoupling capacitance.
Question 4: I can’t turn the LEDs on or off, but their registers are set properly. Why?
• Check the Mode register 1 bit 4 (MODE1[4]) SLEEP setting. The value needs to be a
logic 0 so that the OSC is turned on. If the OSC is turned off, the LEDs cannot be
turned on or off and also can’t be dimmed or blinked.
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
24 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
Question 5: I’m using LEDs with integrated Zener diodes and the IC is getting very hot.
Why?
• The IC outputs can be set to either open-drain or push-pull and default to push-pull
outputs. In this application with the Zener diodes, they need to be set to open-drain
since in the push-pull architecture there is a low resistance path to ground through the
Zener and this is causing the IC to overheat. The PCA9632/33/34/35 ICs all power-up
in the push-pull output mode and with the logic state HIGH, so one of the first things
that need to be done is to set the outputs to open-drain.
11. Limiting values
Table 17. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
Parameter
Conditions
Min
Max
+6.0
5.5
Unit
V
supply voltage
−0.5
VI/O
voltage on an input/output pin
output current on pin LEDn
ground supply current
total power dissipation
storage temperature
ambient temperature
V
SS − 0.5
V
IO(LEDn)
ISS
-
25
mA
mA
mW
°C
-
100
400
+150
+85
Ptot
-
Tstg
−65
−40
Tamb
operating
°C
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
25 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
12. Static characteristics
Table 18. Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Supply
Conditions
Min
Typ
Max
Unit
VDD
IDD
supply voltage
supply current
2.3
-
5.5
V
operating mode; no load; fSCL = 0 MHz
VDD = 2.3 V
-
-
-
38
150
150
150
µA
µA
µA
VDD = 3.3 V
53
VDD = 5.5 V
108
Istb
standby current
no load; fSCL = 0 Hz; I/O = inputs; VI = VDD
VDD = 5.5 V
-
-
0.005
1.70
1
µA
[1]
VPOR
power-on reset voltage
no load; VI = VDD or VSS
2.0
V
Input SCL; input/output SDA
VIL
VIH
IOL
LOW-level input voltage
HIGH-level input voltage
−0.5
0.7VDD
20
-
+0.3VDD
V
-
5.5
-
V
LOW-level output current VOL = 0.4 V; VDD = 2.3 V
VOL = 0.4 V; VDD = 5.0 V
-
mA
mA
µA
pF
30
-
-
IL
leakage current
VI = VDD or VSS
VI = VSS
−1
-
+1
10
Ci
input capacitance
-
6
LED driver outputs
[2]
[2]
[2]
[2]
IOL
LOW-level output current VOL = 0.5 V; VDD = 2.3 V
VOL = 0.5 V; VDD = 3.0 V
12
17
25
-
-
-
-
-
-
mA
mA
mA
mA
-
VOL = 0.5 V; VDD = 4.5 V
-
IOL(tot)
VOH
total LOW-level output
current
VOL = 0.5 V; VDD = 4.5 V
100
HIGH-level output
voltage
IOH = −10 mA; VDD = 2.3 V
IOH = −10 mA; VDD = 3.0 V
IOH = −10 mA; VDD = 4.5 V
1.6
2.3
4.0
-
-
-
V
-
-
V
-
-
V
Co
output capacitance
2.5
5
pF
[1] VDD must be lowered to 0.2 V in order to reset part.
[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits.
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
26 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
13. Dynamic characteristics
Table 19. Dynamic characteristics
Symbol Parameter
Conditions
Standard- mode
I2C-bus
Fast-mode
I2C-bus
Fast-mode
Plus I2C-bus
Unit
Min
0
Max
100
-
Min
0
Max
Min
0
Max
1000 kHz
[1]
fSCL
tBUF
SCL clock frequency
400
-
bus free time between a
STOP and START condition
4.7
1.3
0.5
-
-
-
-
-
µs
µs
µs
µs
ns
tHD;STA
tSU;STA
hold time (repeated) START
condition
4.0
4.7
4.0
-
-
-
0.6
0.6
0.6
-
-
-
0.26
0.26
0.26
set-up time for a repeated
START condition
tSU;STO set-up time for STOP
condition
tHD;DAT
data hold time
0
-
3.45
3.45
-
0
-
0.9
0.9
-
0
[2]
[3]
tVD;ACK data valid acknowledge time
0.3
0.3
250
4.7
0.1
0.1
100
1.3
0.05
0.05
50
0.45 µs
0.45 µs
tVD;DAT
tSU;DAT
tLOW
data valid time
data set-up time
-
-
ns
LOW period of the SCL
clock
-
-
0.5
µs
tHIGH
tf
HIGH period of the SCL
clock
4.0
-
0.6
-
0.26
-
µs
ns
ns
ns
[4][5]
[6]
[6]
fall time of both SDA and
SCL signals
-
-
-
300
20 + 0.1Cb
300
300
50
-
-
-
120
120
50
tr
rise time of both SDA and
SCL signals
1000 20 + 0.1Cb
[7]
tSP
pulse width of spikes that
must be suppressed by the
input filter
50
-
[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
[2] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to Table 18, VIL of the SCL signal) in order
to bridge the undefined region of SCL’s falling edge.
[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[6] Cb = total capacitance of one bus line in pF.
[7] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
27 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
SDA
t
t
t
t
t
r
f
HD;STA
SP
BUF
t
LOW
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
002aaa986
Fig 22. Definition of timing
START
condition
(S)
bit 7
MSB
(A7)
STOP
condition
(P)
bit 6
(A6)
bit 1
(D1)
bit 0
(D0)
acknowledge
(A)
protocol
t
t
t
HIGH
SU;STA
LOW
1 / f
SCL
SCL
SDA
t
t
BUF
f
t
r
t
t
t
SU;STO
t
t
t
HD;DAT
VD;DAT
VD;ACK
HD;STA
SU;DAT
002aab285
Rise and fall times refer to VIL and VIH
.
Fig 23. I2C-bus timing diagram
14. Test information
V
open
DD
V
SS
V
R
500 Ω
DD
L
V
V
O
I
PULSE
GENERATOR
DUT
C
50 pF
L
R
T
002aab880
RL = Load resistor for LEDn. RL for SDA and SCL > 1 kΩ (3 mA or less current).
CL = Load capacitance includes jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 24. Test circuitry for switching times
Rev. 03 — 15 July 2008
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
28 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
15. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
A
(A )
2
A
3
A
1
pin 1 index
θ
L
p
L
1
4
detail X
e
w M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.05
0.95
0.80
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
5.1
4.7
0.7
0.4
0.70
0.35
6°
0°
mm
1.1
0.65
0.25
0.94
0.1
0.1
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-04-09
03-02-18
SOT505-1
Fig 25. Package outline SOT505-1 (TSSOP8)
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
29 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
HVSON8: plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3 x 3 x 0.85 mm
SOT908-1
0
1
2 mm
scale
X
D
B
A
E
A
A
1
c
detail X
terminal 1
index area
e
1
terminal 1
index area
C
M
M
v
C
C
A
B
e
b
y
y
w
C
1
1
4
L
exposed tie bar (4×)
E
h
exposed tie bar (4×)
8
5
D
h
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
(1)
(1)
UNIT
A
b
E
e
e
y
c
D
D
E
L
v
w
y
1
1
h
1
h
0.05
0.00
0.3
0.2
3.1
2.9
2.25
1.95
3.1
2.9
1.65
1.35
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
1.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
05-09-26
05-10-05
SOT908-1
MO-229
Fig 26. Package outline SOT908-1 (HVSON8)
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
30 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm
SOT552-1
D
E
A
X
c
y
H
v
M
A
E
Z
6
10
A
(A )
2
A
3
A
1
pin 1 index
θ
L
p
L
1
5
detail X
e
w M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
UNIT
v
w
y
Z
θ
1
2
3
p
E
p
max.
0.15
0.05
0.95
0.80
0.30
0.15
0.23
0.15
3.1
2.9
3.1
2.9
5.0
4.8
0.7
0.4
0.67
0.34
6°
0°
mm
1.1
0.5
0.25
0.95
0.1
0.1
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-07-29
03-02-18
SOT552-1
Fig 27. Package outline SOT552-1 (TSSOP10)
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
31 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
HVSON10: plastic thermal enhanced very thin small outline package; no leads;
10 terminals; body 3 x 3 x 0.85 mm
SOT650-1
0
1
2 mm
scale
X
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
e
1
terminal 1
index area
y
y
v
M
e
C
C
A
B
b
C
1
1
5
w
M
L
E
h
6
10
D
h
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
(1)
(1)
UNIT
A
b
E
e
e
y
c
D
D
E
L
v
w
y
1
1
h
1
h
0.05 0.30
0.00 0.18
3.1
2.9
2.55
2.15
3.1
2.9
1.75
1.45
0.55
0.30
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-01-22
02-02-08
SOT650-1
- - -
MO-229
- - -
Fig 28. Package outline SOT650-1 (HVSON10)
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
32 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
16. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
integrated circuits.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
© NXP B.V. 2008. All rights reserved.
PCA9632_3
Product data sheet
Rev. 03 — 15 July 2008
33 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 29) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 20 and 21
Table 20. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 21. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 29.
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
34 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 29. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Abbreviations
Table 22. Abbreviations
Acronym
CDM
DUT
Description
Charged-Device Model
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
I2C-bus
Inter-Integrated Circuit bus
Liquid Crystal Display
LCD
LED
Light Emitting Diode
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
NMOS
PCB
Negative-channel Metal-Oxide Semiconductor
Printed-Circuit Board
PMOS
PWM
RGB
Positive-channel Metal-Oxide Semiconductor
Pulse Width Modulation
Red/Green/Blue
RGBA
SMBus
Red/Green/Blue/Amber
System Management Bus
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
35 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
19. Revision history
Table 23. Revision history
Document ID
PCA9632_3
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20080715
Product data sheet
-
PCA9632_2
• Section 7.1.1 “Regular I2C-bus slave address”: added “Remark” and bulleted list
• Table 5 “Register summary”: changed table notes to descriptive paragraphs following table title
• Figure 20 “Software Reset (SWRST) Call sequence”:
–
changed “Byte 1 = 0xA5” to “Byte 1 = A5h”
–
changed “Byte 2 = 0x5A” to “Byte 2 = 5Ah”
• Figure 24 “Test circuitry for switching times”: changed from “GND” to “VSS
”
PCA9632_2
PCA9632_1
20080401
Product data sheet
-
PCA9632_1
-
20070928
Objective data sheet
-
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
36 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
to result in personal injury, death or severe property or environmental
20.2 Definitions
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
20.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9632_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 15 July 2008
37 of 38
PCA9632
NXP Semiconductors
4-bit Fm+ I2C-bus low power LED driver
22. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
17.1
17.2
17.3
17.4
Introduction to soldering. . . . . . . . . . . . . . . . . 33
Wave and reflow soldering . . . . . . . . . . . . . . . 33
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 33
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 34
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
18
19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . 36
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
20
Legal information . . . . . . . . . . . . . . . . . . . . . . 37
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37
20.1
20.2
20.3
20.4
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
Functional description . . . . . . . . . . . . . . . . . . . 6
Device addresses . . . . . . . . . . . . . . . . . . . . . . . 6
Regular I2C-bus slave address. . . . . . . . . . . . . 6
LED All Call I2C-bus address . . . . . . . . . . . . . . 7
LED Sub Call I2C-bus addresses . . . . . . . . . . . 7
Software reset I2C-bus address . . . . . . . . . . . . 8
Control register . . . . . . . . . . . . . . . . . . . . . . . . . 8
Register definitions . . . . . . . . . . . . . . . . . . . . . 10
Mode register 1, MODE1 . . . . . . . . . . . . . . . . 11
Mode register 2, MODE2 . . . . . . . . . . . . . . . . 11
PWM registers 0 to 3, PWMx — Individual
21
22
Contact information . . . . . . . . . . . . . . . . . . . . 37
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3
7.3.1
7.3.2
7.3.3
brightness control registers . . . . . . . . . . . . . . 12
Group duty cycle control, GRPPWM . . . . . . . 13
Group frequency, GRPFREQ . . . . . . . . . . . . . 14
LED driver output state, LEDOUT . . . . . . . . . 14
I2C-bus subaddress 1 to 3, SUBADRx . . . . . . 14
LED All Call I2C-bus address, ALLCALLADR. 15
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 15
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 15
Using the PCA9632 with and without external
drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Individual brightness control with group
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.4
7.5
7.6
7.7
dimming/blinking. . . . . . . . . . . . . . . . . . . . . . . 17
8
Characteristics of the I2C-bus. . . . . . . . . . . . . 19
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
START and STOP conditions . . . . . . . . . . . . . 19
System configuration . . . . . . . . . . . . . . . . . . . 19
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.1
8.1.1
8.2
8.3
9
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 21
Application design-in information . . . . . . . . . 24
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 25
Static characteristics. . . . . . . . . . . . . . . . . . . . 26
Dynamic characteristics . . . . . . . . . . . . . . . . . 27
Test information. . . . . . . . . . . . . . . . . . . . . . . . 28
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29
Handling information. . . . . . . . . . . . . . . . . . . . 33
Soldering of SMD packages . . . . . . . . . . . . . . 33
10
11
12
13
14
15
16
17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 July 2008
Document identifier: PCA9632_3
PCA9632DP1-T 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
PCA9632DP2 | NXP | 4-bit Fm+ I2C-bus low power LED driver | 获取价格 | |
PCA9632DP2,118 | NXP | PCA9632 - 4-bit Fm+ I2C-bus low power LED driver TSSOP 10-Pin | 获取价格 | |
PCA9632DP2-T | NXP | IC,LASER DIODE/LED DRIVER,TSSOP,10PIN,PLASTIC | 获取价格 | |
PCA9632TK | NXP | 4-bit Fm+ I2C-bus low power LED driver | 获取价格 | |
PCA9632TK2 | NXP | 4-bit Fm+ I2C-bus low power LED driver | 获取价格 | |
PCA9632TK2-T | NXP | IC,LASER DIODE/LED DRIVER,LLCC,10PIN,PLASTIC | 获取价格 | |
PCA9633 | NXP | 4-bit Fm+ I2C-bus LED driver | 获取价格 | |
PCA9633BS | NXP | 4-bit Fm+ I2C-bus LED driver | 获取价格 | |
PCA9633BS,115 | NXP | PCA9633 - 4-bit Fm+ I2C-bus LED driver QFN 16-Pin | 获取价格 | |
PCA9633BS-T | NXP | 4-bit Fm I2C-bus LED driver - # of Addresses: 126 ; Enable: yes ; I2C-bus: 1000 kHz; I2C-bus interface: Fast Mode Plus 30 mA SDA outputs for 4000 pF bus ; Max Sink Current per bit: 25 mA; Max Sink Current, per package: 100 mA; Number of bits: 4 ; Operating temperature: -40~85 Cel; Operating voltage: 2.3~5.5 VDC; PWMs: 5 (4 x 97 kHz dim and 1 x 97 kHz dim or 24 Hz to 10.73 sec blink) | 获取价格 |
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