PCA9629PW,118_技术文档

PCA9629

Fm+ I²C-bus stepper motor controller

Rev. 1 — 29 February 2012

Product data sheet

1. General description

The PCA9629 is an I²C-bus controlled low-power CMOS device that provides all the logic

and control required to drive a four phase stepper motor. PCA9629 is intended to be used

with external high current drivers to drive the motor coils. The PCA9629 supports three

stepper motor drive formats: one-phase (wave drive), two-phase, and half-step. In

addition, when used as inputs, four General Purpose Input/Outputs (GPIOs) allow sensing

of logic level output from optical interrupter modules and generate active LOW interrupt

signal on the INT pin of PCA9629. This is a useful feature in sensing home position of

motor shaft or reference for step pulses. Upon interrupt, the PCA9629 can be

programmed to automatically stop the motor or reverse the direction of rotation of motor.

Output wave train is programmable using control registers. The control registers are

programmed via the I²C-bus. Features built into the PCA9629 provide highly flexible

control of stepper motor, off-load bus master/micro and significantly reduce I²C-bus traffic.

These include control of step size, number of steps per single command, number of full

rotations and direction of rotation. A ramp-up on start and/or ramp-down on stop is also

provided.

The PCA9629 is available in a 16-pin TSSOP package and is specified over the 40 C to

+85 C industrial temperature range.

2. Features and benefits

 Generate motor coil drive phase sequence signals with four outputs for use with

external high current drivers to off-load CPU

 Four balanced push-pull type outputs capable of sinking 25 mA or sourcing 25 mA for

glueless connection to external high current drivers needed to drive motor coils

 Up to 1000 pF loads with 100 ns rise and fall times

 Built-in oscillator requires no external components

 Stepper motor drive control logic

 One-phase (wave drive), two-phase, and half-step drive format logic level outputs

 Programmable step rate: 344.8 kpps to 0.3 pps with 5 % accuracy

 Programmable ramp-up on start and ramp-down to stop

 Programmable steps and rotation control

 Sensor enabled drive control: linked to interrupt from I/O pins

 Direction control of motor shaft

 Selectable active hold, power off or released states for motor shaft

PCA9629

NXP Semiconductors

Fm+ I²C-bus stepper motor controller

 Four general purpose I/Os:

 Configured to sense logic level outputs from optical interrupter photo transistor

circuit

 Configured as outputs to drive (source/sink) LEDs or other loads up to 25 mA

 Programmable interrupt Mask Control for input pins

 4.5 V to 5.5 V operation

 1 MHz Fast-mode Plus (Fm+) I²C-bus serial interface with 30 mA high drive capability

on SDA output for driving high capacitive buses

 Compliant with I²C-bus Standard-mode (100 kHz) and Fast-mode (400 kHz) speeds

 Active LOW open-drain interrupt output

 Active LOW reset (RESET) input pin resets device to power-up default state: can be

used to recover from bus stuck condition

 Programmable watchdog timer

 All Call address allows programming of more than one device at the same time with

the same parameters

 16 programmable slave addresses using two address pins

 40 C to +85 C operation

 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22C101

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

 Package offered: TSSOP16

3. Applications

 Amusement machines

 Gaming and slot machines

 Consumer home appliances or toys

 Industrial automation

 HVAC and building climate control systems

 Robotics

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCA9629PW

TSSOP16

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

4.1 Ordering options

Table 2.

Ordering options

Type number

PCA9629PW

Topside mark

Temperature range

PCA9629

T_amb= 40 C to +85 C

PCA9629

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Product data sheet

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PCA9629

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Fm+ I²C-bus stepper motor controller

5. Block diagram

AD0 AD1

PCA9629

INPUT

REGISTER

P0

SCL

INPUT FILTER

GPIO

SDA

GPIO AND

P3

INTERRUPT

2

I C-BUS

CONTROL

OUTPUT

CONTROL

POWER-ON

RESET

V

DD

200 kΩ

INT

RESET

V

SS

WATCHDOG

TIMER

CONTROL

REGISTERS

OSCILLATOR

MOTOR CONTROLLER

INTERRUPT

HANDLER

OUT0

STEPS,

ROTATIONS

AND

PULSE WIDTH

COUNTERS

OUTPUT

COIL

EXCITATION

LOGIC

RAMP

CONTROL

PHASE

SEQUENCE

GENERATOR

LOOP DELAY

TIMER

OUT3

002aad902

Remark: All I/Os are set to inputs at power-up and reset.

Fig 1. PCA9629 block diagram

PCA9629

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PCA9629

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Fm+ I²C-bus stepper motor controller

6. Pinning information

6.1 Pinning

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

P0

P1

V

DD

SDA

P2

SCL

P3

INT

PCA9629PW

AD0

AD1

RESET

OUT0

OUT1

OUT2

OUT3

V

SS

002aad903

Fig 2. Pin configuration for TSSOP16

6.2 Pin description

Table 3.

Symbol

Pin description

1

Type

Description

P0

I/O

input/output 0 (output is 25 mA push-pull)

input/output 1 (output is 25 mA push-pull)

input/output 2 (output is 25 mA push-pull)

input/output 3 (output is 25 mA push-pull)

address input 0

P1

2

I/O

P2

3

I/O

P3

4

I/O

AD0

AD1

RESET

V_SS

5

I

6

I

address input 1

7

I

active LOW reset input with 1 s filter

supply ground

8

ground

OUT3

OUT2

OUT1

OUT0

INT

9

O

control 25 mA push-pull output 3

control 25 mA push-pull output 2

control 25 mA push-pull output 1

control 25 mA push-pull output 0

active LOW interrupt output; open-drain

serial clock line

10

11

12

13

14

15

16

O

SCL

SDA

V_DD

I

I/O

serial data line; open-drain capable of sinking 30 mA

supply voltage

power supply

PCA9629

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Product data sheet

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PCA9629

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Fm+ I²C-bus stepper motor controller

7. Functional description

Refer to Figure 1 “PCA9629 block diagram”.

7.1 Device address

Following a START condition, the bus master must send the target slave address followed

by a read or write operation. The slave address of the PCA9629 is shown in Figure 3.

Slave address pins AD1 and AD0 choose one of 16 slave addresses. To conserve power,

no internal pull-up resistors are incorporated on AD1 and AD0. Table 4 shows all 16 slave

addresses by connecting the AD0 and AD1 to V_DD, V_SS, SCL or SDA.

slave address

0

1

0

A3 A2 A1 A0 R/W

fixed

programmable

002aad905

Fig 3. PCA9629 device address

The last bit of the first byte defines the reading from or writing to the PCA9629. When set

to logic 1 a read is selected, while logic 0 selects a write operation.

Table 4.

AD1

PCA9629 address map

AD0 Device family high-order Variable portion of address

address bits

Address

A6

0

A5

1

A4

0

A3

0

1

A2

0

1

0

1

A1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V_SS

40h

42h

44h

46h

48h

4Ah

4Ch

4Eh

50h

52h

54h

56h

58h

5Ah

5Ch

5Eh

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

SCL

SDA

SCL

SDA

V_SS

V_DD

SCL

SDA

SCL

SDA

SCL

SDA

V_SS

V_DD

SCL

SDA

SCL

SDA

PCA9629

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Product data sheet

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PCA9629

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Fm+ I²C-bus stepper motor controller

7.2 Command register

Following the successful acknowledgement of the slave address and a write bit, the bus

master sends a byte to the PCA9629. This byte is stored in the Command register.

AI

1

-

D5 D4 D3 D2 D1 D0

default at power-up

or after RESET

0

register number

Auto-Increment

002aad906

Fig 4. Command register

At power-up, the Command register defaults to 80h, with the AI bit set to ‘1’ and the lowest

seven bits set to ‘0’. The lowest six bits are used as a pointer to determine which register

will be accessed. Only a command register code with the six least significant bits equal to

the 39 allowable values as defined in Table 5 “Register summary” are acknowledged.

Reserved or undefined command codes are not acknowledged.

The most significant bit of the Command register is for Auto-Increment. If the

Auto-Increment flag is set, the six low-order bits of the Control register are automatically

incremented after a read or write. This allows the user to program the registers

sequentially. The contents of these bits will roll over to ‘00 0000’ after the last register

(address = 26h) is accessed. Only the six least significant bits are affected by the AI flag.

Unused bits must be programmed with zeroes.

7.3 Register definitions

Table 5.

Register summary

Register D5 D4 D3 D2 D1 D0 Name

number

Type

Function

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MODE

read/write

read only

read/write

write only

read/write

Mode register

I²C-bus subaddress 1

I²C-bus subaddress 2

I²C-bus subaddress 3

All Call I²C-bus address

Watchdog time-out interval register

Watchdog control register

Input Port register

SUBADR1

SUBADR2

SUBADR3

ALLCALLADR

WDTOI

WDCNTL

IP

INTSTAT

OP

Interrupt status register

Output Port register

IOC

I/O Configuration register

Mask interrupt register

Clear interrupts

MSK

CLRINT

INTMODE

Interrupt mode register

Interrupt action setup control register

Interrupt motor setup control register

INT_ACT_SETUP read/write

INT_MTR_SETUP read/write

PCA9629

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PCA9629

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Fm+ I²C-bus stepper motor controller

Table 5.

Register summary …continued

Register D5 D4 D3 D2 D1 D0 Name

number

Type

Function

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

INT_ES_SETUP

INT_AUTO_CLR

SETMODE

read/write

Interrupt extra steps setup control register

Interrupt auto clear control register

Output state on STOP

PHCNTL

Phase control register

SROTNL

Steps per rotation low byte

SROTNH

Steps per rotation high byte

CWPWL

Step pulse width for CW rotation low byte

Step pulse width for CW rotation high byte

Step pulse width for CCW rotation low byte

Step pulse width for CCW rotation high byte

Number of steps CW low byte

CWPWH

CCWPWL

CCWPWH

CWSCOUNTL

CWSCOUNTH

CCWSCOUNTL

CCWSCOUNTH

CWRCOUNTL

CWRCOUNTH

CCWRCOUNTL

CCWRCOUNTH

EXTRASTEPS0

Number of steps CW high byte

Number of steps CCW low byte

Number of steps CCW high byte

Number of rotations CW low byte

Number of rotations CW high byte

Number of rotations CCW low byte

Number of rotations CCW high byte

Count value for extra steps or rotations for

INTP0

23h

1

0

1

EXTRASTEPS1

read/write

Count value for extra steps or rotations for

INTP1

24h

25h

26h

1

-

0

-

0

-

1

-

0

1

-

0

1

0

-

RMPCNTL

LOOPDLY

MCNTL

-

read/write

-

Ramp control register

Loop delay time register

Control start/stop motor

Reserved

27h to

FFh

PCA9629

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PCA9629

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Fm+ I²C-bus stepper motor controller

7.3.1 MODE — Mode register

Table 6.

MODE - Mode register (address 00h) bit description

Legend: * default value.

Address

Register

Bit

7

Access

Value Description

00h

MODE

-

0*

1

not used

6

-

not used

5

R/W

Disable INT output pin

0*

1

Enable INT output pin

4

3

R/W

outputs change on I²C-bus ACK

outputs change on I²C-bus STOP command

PCA9629 responds to I²C-bus subaddress 1

0*

1

0*

PCA9629 does not respond to I²C-bus

subaddress 1

2

1

0

R/W

1

PCA9629 responds to I²C-bus subaddress 2

PCA9629 does not respond to I²C-bus

subaddress 2

PCA9629 responds to I²C-bus subaddress 3

PCA9629 does not respond to I²C-bus

subaddress 3

0*

1

0*

1*

0

PCA9629 responds to All Call I²C-bus

address

PCA9629 does not respond to All Call

I²C-bus address

7.3.1.1 Disable interrupt output pin (bit 5)

This feature is useful when the host/micro/master does not want the INT pin to toggle

when interrupts occur. Within PCA9629, when interrupts are enabled and interrupt event

occurs, the actions related to the interrupt event are still carried out. However, if bit 5 = 1,

the INT pin does not show the activation of interrupt because the pin is disabled. If

bit 5 = 0, the micro sees the actual status of the INT pin.

The only exception to this rule is when the watchdog timer is enabled in the ‘Interrupt and

Reset’ mode (see Section 7.3.4.2). In this case, the interrupt line toggles when the

watchdog timer times out (even though bit 5 of this register is a ‘1’). This is because in the

‘Interrupt and Reset mode’ the part gets reset (and hence bit 5 is cleared) when the timer

times out.

7.3.1.2 Outputs change on STOP (bit 4)

This feature can be used to synchronize the starting of the motor across multiple

PCA9629 devices on the bus at approximately the same time (within few microseconds of

one another). The host controller can program all the PCA9629s on the bus and then

issue the I²C-bus STOP command. Upon receiving the STOP command, all the PCA9629

devices on the bus start generating pulse sequences required to turn the motor. This

feature is applicable only to the motor coil outputs of the device namely, OUT0 to OUT3.

It is not applicable to the general purpose I/Os (P0 to P3).

PCA9629

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Fm+ I²C-bus stepper motor controller

7.3.2 SUBADR1 to SUBADR3 — I²C-bus subaddress 1 to 3

Table 7.

SUBADR1 to SUBADR3 - I²C-bus subaddress registers 1 to 3

(addresses 01h, 02h 03h) bit description

Legend: * default value.

Address Register

Bit

7:1

0

Symbol

A1[7:1]

A1[0]

Access Value

Description

I²C-bus subaddress 1

01h

02h

03h

SUBADR1

SUBADR2

SUBADR3

R/W

1110 001*

R only

R/W

0*

reserved

7:1

0

A2[7:1]

A2[0]

1110 010*

0*

I²C-bus subaddress 2

reserved

I²C-bus subaddress 3

R only

R/W

7:1

0

A3[7:1]

A3[0]

1110 100*

0*

R only

reserved

Subaddresses are programmable through the I²C-bus. Default power-up values are E2h,

E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up

(the corresponding bits [3:1] in MODE register is equal to 0).

Once subaddresses have been programmed to their right values, bits [3:1] (MODE

register) must be set to logic 1 in order to have the device acknowledging these

addresses. Only the seven MSBs representing the I²C-bus subaddress are valid. The

LSB in SUBADRx register is a read-only bit (0). When subaddress control bits [3:1] in

MODE register is set to logic 1, the corresponding I²C-bus subaddress can be used

during either an I²C-bus read or write sequence.

7.3.3 ALLCALLADR — All Call I²C-bus address

Table 8.

ALLCALLADR - All Call I²C-bus address register (address 04h) bit description

Legend: * default value.

Address Register

Bit

Symbol Access Value

Description

04h

ALLCALLADR 7:1

AC[7:1]

R/W

1110 000*

ALLCALL I²C-bus

address register

0

AC[0]

R only

0*

reserved

The All Call I²C-bus address allows all the PCA9629s on the bus to be programmed at the

same time (bit 0 in register MODE must be equal to 1 (power-up default state)). This

address is programmable through the I²C-bus and can be used during either an I²C-bus

read or write sequence. Only the seven MSBs representing the All Call I²C-bus address

are valid. The LSB in ALLCALLADR register is a read-only bit (0). If bit 0 in MODE

register = 0, the device does not acknowledge the address programmed in register

ALLCALLADR.

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7.3.4 Watchdog timer

The purpose of the watchdog timer is to recover the PCA9629 if the system it is used in

enters an erroneous state. When the timer times out, the watchdog generates an interrupt

to the host controller and, if programmed for reset, resets PCA9629 if the user program

fails to ‘feed’ the watchdog. To feed the watchdog, the user simply addresses the

PCA9629 ([START + slave address + START] or [START + slave address + STOP]) within

the watchdog time-out interval. Only this sequence resets the watchdog.

Watchdog timer features:

• Can be programmed to reset the PCA9629 to POR state if it is not periodically

addressed

• Enabled by software, but requires a hardware reset or a watchdog reset to be

disabled

• Flag to indicate watchdog reset

• Programmable 8-bit timer with internal prescaler

• Selectable time period from one second to 255 seconds

The watchdog timer should be used in the following manner:

• Set the time-out interval value in WDTOI register

• Set the mode of operation (interrupt only or interrupt and reset) and enable the

watchdog using the WDCNTL register

• Watchdog should be fed by periodically addressing PCA9629 before the watchdog

timer underflows to prevent reset/interrupt

• Watchdog control register, WDCNTL, can be read at any time to determine the status

of the watchdog operation

7.3.4.1 WDTOI — WatchDog Time-Out Interval register

The watchdog time-out interval should be programmed in this register. The default value

is FFh, which indicates a 255 second time-out interval. The smallest value for the time-out

interval is 01h, which indicates a one-second time-out interval. Watchdog operation

cannot be enabled with a zero second time-out interval. If user writes a zero value to this

register, the timer does not start.

Table 9.

WDTOI - Watchdog time-out interval register (address 05h) bit description

Legend: * default value.

Address

Register

Bit

Access

Value Description

FFh* Watchdog time-out interval

05h

WDTOI

7:0

R/W

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7.3.4.2 WDCNTL — WatchDog Control register

Table 10. WDMOD - Watchdog control register (address 06h) bit description

Legend: * default value.

Address Register Bit

Access

Value Description

06h

WDCNTL 7:5

4

read only 000*

Reserved.

write only

read only

R/W

1

Clear WDINT flag.

0*

1

Read value.

3

2

1

WDINT: watchdog interrupt flag set.^[1]

WDINT: watchdog interrupt flag not set.

WDRST: watchdog reset flag.^[2]

WDRST: watchdog reset flag not set.

0*

1

0*

1

WDMOD: watchdog interrupt and reset mode

(set only).

0*

1

WDMOD: watchdog interrupt only mode.

WDEN: watchdog enabled (set only).

WDEN: watchdog disabled.

0

R/W

0*

[1] Use bit 4 to clear this bit.

[2] Reading WDCNTL register clears this bit.

This register controls the operation of the watchdog timer. Watchdog timer can be enabled

by setting the WDEN bit of this register. WDEN is a set-only bit. Once set (enabled), this

bit cannot be cleared by software. It can be cleared only with a hardware reset or

watchdog reset.

The WDMOD bit determines the mode of operation. This bit is a set-only bit. There are

two modes of operation:

• Interrupt only mode: This is the default mode of operation. In this mode, when the

watchdog timer times out, the interrupt flag is set (WDINT) and an interrupt is

generated to the host controller.

• Interrupt and reset mode: In this mode, when the watchdog timer times out, the reset

flag is set (WDRST) and an interrupt is generated to host controller and resets the

chip to POR state.

WDINT flag: This flag can be cleared by writing a ‘1’ to bit 4 of this register.

WDRST flag: This flag indicates that a watchdog reset has occurred. This flag does not

get cleared by the watchdog reset. After a watchdog reset event, the host controller can

read this bit to determine if a reset had occurred. The WDRST flag gets cleared after it is

read or after an external reset is applied.

Before enabling the watchdog timer, the watchdog flags (interrupt flag and reset flag)

must be cleared (if they are set). The interrupt flag is cleared by using bit 4 of the

WDCNTL register and the reset flag is cleared just by reading the WCNTL register.

PCA9629

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PCA9629

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Fm+ I²C-bus stepper motor controller

7.3.5 GPIOs and interrupts

7.3.5.1 IP — Input Port register

This register is read-only. They reflect the incoming logic levels of the port pins P0 to P3,

regardless of whether the pin is defined as an input or an output by the I/O configuration

register. Writes to this register have no effect.

Table 11. IP - Input Port register (address 07h) bit description

Legend: * default value ‘X’ is determined by the externally applied logic level.

Address

Register

Bit

7:4

3:0

Access

Value Description

07h

IP

read only 0h*

read only Xh*

reserved

reflects incoming logic levels of I/O P0 to P3

7.3.5.2 INTSTAT — Interrupt Status register

This register reflects the status of an interrupt. INTSTAT is a read-only register.

INTP0 to INTP3 interrupt caused by input port pins P0 to P3, respectively.

Table 12. INTSTAT - Interrupt status register (address 08h) bit description

Legend: * default value.

Address

Register

Bit

7:4

3:0

Access

-

Value Description

08h

INTSTAT

0*

1

reserved

read only

INTP3 flag set

INTP3 flag clear

INTP2 flag set

INTP2 flag clear

INTP1 flag set

INTP1 flag clear

INTP0 flag set

INTP0 flag clear

0*

1

0*

1

0*

1

0*

Upon power-up or activation of hardware reset by RESET pin, INTSTAT register bits [3:0]

are cleared (= 0), thus clearing the interrupt flags. Change in logic level at GPIO pins

P0 to P3 configured as inputs will cause generation of interrupt when not masked using

MSK register. The corresponding flag bit in this register is set and latched until cleared.

7.3.5.3 OP — Output Port register

This register is an output-only port. It reflects the outgoing logic levels of the pins defined

as outputs by IOC register. Bit values in this register have no effect on pins defined as

inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the

output selection, not the actual pin value. Only the lower four bits are used and P0 to P3

are affected by this register.

Table 13. OP - Output Port register (address 09h) bit description

Legend: * default value.

Address

Register

Bit

7:4

3:0

Access

Value Description

09h

OP

-

0000* reserved

R/W

0000* reflects outgoing logic levels of I/O P0 to P3

PCA9629

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Product data sheet

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PCA9629

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Fm+ I²C-bus stepper motor controller

7.3.5.4 IOC — I/O Configuration register

The lower four bits of this register configures the direction of the I/O pins P0 to P3. If a bit

in [3:0] is set (written with logic 1), the corresponding port pin is enabled as an input with

high-impedance output driver. If the bit is cleared (written with logic 0), the corresponding

port pin is enabled as an output. At reset, the device’s ports P0 to P3 are inputs.

Table 14. IOC - I/O configuration register (address 0Ah) bit description

Legend: * default value.

Address

Register

Bit Access

Value

0*

1*

0

Description

0Ah

IOC

7:4

3

-

reserved

R/W

P3 will be configured as input

P3 will be configured as output

P2 will be configured as input

P2 will be configured as output

P1 will be configured as input

P1 will be configured as output

P0 will be configured as input

P0 will be configured as output

2

1

0

R/W

1*

0

1*

0

1*

0

IOC - I/O CONFIGURATION REGISTER

OP - OUTPUT PORT REGISTER

read/write access

2

from I C-bus

P0 to P3

read only access

IP - INPUT PORT REGISTER

2

from I C-bus

002aaf869

Fig 5. Simplified schematic for GPIO control

7.3.5.5 MSK — Mask interrupt register

Upon power-up, all the internal interrupt latches are reset and interrupt flags cleared and

interrupt mask bits [3:0] are set to logic 1, thus disabling interrupts from input ports P0 to

P3. Interrupts may be enabled by setting corresponding mask bits to logic 0.

Table 15. MSK - Interrupt mask register (address 0Bh) bit description

Legend: * default value.

Address

Register

Bit

7:4

3

Access

Value Description

0Bh

MSK

-

0*

1*

0

reserved

R/W

disables interrupt for I/O P3

enables interrupt for I/O P3

disables interrupt for I/O P2

enables interrupt for I/O P2

disables interrupt for I/O P1

enables interrupt for I/O P1

disables interrupt for I/O P0

enables interrupt for I/O P0

2

1

0

R/W

1*

0

1*

0

1*

0

An additional control to enable or disable the INT pin is provided by MODE control register

bit 5 (MODE[5]). Refer to Table 6.

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7.3.5.6 CLRINT — Clear Interrupts register

Interrupt flags can be cleared by bits [3:0] when set to logic 1.

Table 16. CLRINT - Clear interrupts register (address 0Ch) bit description

Legend: * default value.

Address

Register

Bit

7:4

3

Access

-

Value Description

0Ch

CLRINT

0*

1

reserved

write only

clear INTP3 flag

read value

0*

1

2

1

0

write only

clear INTP2 flag

read value

0*

1

clear INTP1 flag

read value

0*

1

clear INTP0 flag

read value

0*

7.3.5.7 INTMODE — Interrupt Mode register

When interrupt(s) are enabled, bits [3:0] determine whether rising edge or falling edge of

signal at P0 to P3 causes the interrupt to be generated. Interrupts are latched and flag(s)

are set in the corresponding bits of INTSTAT register. When interrupts are masked using

MSK register, these bits have no effect.

Table 17. INTMODE - Interrupt mode register (address 0Dh) bit description

Legend: * default value.

Address

Register

Bit

7:4

3

Access

Value Description

0Dh

INTMODE

-

0*

1

reserved

R/W

interrupt occurs on falling edge for P3

interrupt occurs on rising edge for P3

interrupt occurs on falling edge for P2

interrupt occurs on rising edge for P2

interrupt occurs on falling edge for P1

interrupt occurs on rising edge for P1

interrupt occurs on falling edge for P0

interrupt occurs on rising edge for P0

0*

1

2

1

0

R/W

0*

1

0*

1

0*

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CLRINT[0]

WATCHDOG

TIMER

1

D

Q

IOC[0]

MSK[0]

MODE[5]

RISING EDGE

DETECTOR

P0

INTMODE

FALLING EDGE

DETECTOR

INT

CLRINT[3]

1

D

Q

IOC[3]

MSK[3]

RISING EDGE

DETECTOR

P3

INTMODE

FALLING EDGE

DETECTOR

002aaf870

Fig 6. PCA9629 interrupt logic

7.3.6 Interrupt based motor control

Interrupt mechanisms from GPIOs 0 and 1 (INTP0 and INTP1) can be used to control the

motor operation. Interrupts from GPIOs 2 and 3 are not used for motor control. They

behave as normal GPIO interrupts. In the following sections, the word interrupt refers only

to INTP0 and INTP1. The following actions can be performed upon the occurrence of an

interrupt:

• Stop the motor

• Reverse the direction of motion

• Move extra steps/rotations and then, stop the motor or reverse its direction.

Only interrupts that occurred after the motor was started are acted upon. When an

interrupt occurs, it is latched and the programmed action is performed. The

microcontroller has to clear the interrupt before another occurrence of the same interrupt

otherwise the second occurrence will not be acted upon. The following four registers,

INT_ACT_SETUP, INT_MTR_SETUP, INT_ES_SETUP and INT_AUTO_CLR are used to

program the various interrupt based control features of the motor. To enable the interrupt

based control of the motor, bit 0 of the INT_ACT_SETUP register must be set.

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7.3.6.1 INT_ACT_SETUP — Interrupt Action Setup control register

Table 18. INT_ACT_SETUP - Interrupt action setup control register (address 0Eh)

bit description

Legend: * default value.

Address

Register

Bit Access Value Description

0Eh

INT_ACT_SETUP 7:5

4

-

not used

R/W

1

unit for EXTRASTEPS for both P0 and

P1 counter is number of full rotations

0*

unit for EXTRASTEPS for both P0 and

P1 counter is number of steps

3:1

0

-

not used

R/W

1

0*

enable interrupt based control of motor

disable interrupt based control of motor

If the interrupt based control is disabled, then values programmed in the following three

registers (INT_MTR_SETUP, INT_ES_SETUP and INT_AUTO_CLR) have no effect on

the motor operation.

Bit 4 of this register determines whether the values programmed in EXTRASTEPS0 and

EXTRASTEPS1 registers represent the number of steps or number of rotations (see

Section 7.3.16).

7.3.6.2 INT_MTR_SETUP — Interrupt Motor Setup control register

Table 19. INT_MTR_SETUP - Interrupt motor setup control register (address 0Fh)

bit description

Legend: * default value.

Address Register

Bit Access Value Description

0Fh INT_MTR_SETUP 7:2

R

-

reserved

1:0 R/W

11

10

01

00*

Reverse motor on INT caused by P0 or P1

Stop motor on INT caused by P0 or P1

Stop motor on INT caused by P1

Stop motor on INT caused by P0

When an interrupt occurs, if the motor is programmed to stop on that interrupt, the

following sequence of events takes place in the given order:

1. If extra steps feature is enabled for that interrupt (see INT_ES_SETUP,

Section 7.3.6.3) then extra steps (/rotations) will occur.

2. If ramp down is enabled (see RMPCNTL, Section 7.3.17), the motor starts ramping

down.

3. Motor stops.

When an interrupt occurs, if the motor is programmed to reverse direction on that

interrupt, the following sequence of events takes place:

1. If extra steps feature is enabled for that interrupt (see INT_ES_SETUP,

Section 7.3.6.3) then extra steps (/rotations) occurs in the current direction of motion.

2. The motor stops for the amount of time specified in the LOOPDLY timer register.

3. Motor reverses its direction of rotation.

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7.3.6.3 INT_ES_SETUP — Interrupt Extra Steps Setup control register

Table 20. INT_ES_SETUP - Interrupt extra steps setup control register (address 10h)

bit description

Legend: * default value.

Address

Register

Bit

Access Value

Description

10h

INT_ES_SETUP 7:2

1:0

R

0000 00 reserved

R/W

11

Enable EXTRASTEPS on both

INTP0 and INTP1

10

Enable EXTRASTEPS only on INTP1

Enable EXTRASTEPS only on INTP0

01

00*

Disable EXTRASTEPS for both

INTP0 and INTP1

This register can be used to enable / disable the extra steps feature for each interrupt.

Extra steps feature is used to make the motor rotate a specified amount of steps/rotations

from the point of an interrupt occurrence.

7.3.6.4 INT_AUTO_CLR — Interrupt Auto Clear register

This register provides a mechanism to clear the two interrupts (INTP0 and INTP1)

automatically without the occurrence of one interrupt clears the other without the

microcontroller. The auto clear feature is disabled by default.

Table 21. INT_AUTO_CLR - Interrupt auto clear register (address 11h) bit description

Legend: * default value.

Address

Register

INT_AUTO_CLR 7:2

1:0 R/W

Bit Access Value Description

11h

-

0*

reserved

11

10

01

INTP0 auto clears INTP1

INTP1 auto clears INTP0

INTP0 auto clears INTP1;

INTP1 auto clears INTP0

00*

INT auto clear for INTP0, INTP1 disabled

This feature is only available for interrupts that directly affect the operation of the motor as

defined by the INT_MTR_SETUP register (see Section 7.3.6.2). For example, if INTP0 is

used to stop the motor then it can be automatically cleared by its pair INTP1. However

INTP1 should be manually cleared (through I²C-bus write to the CLRINT register). If both

the interrupts are used to control the motor operation (INT_MTR_SETUP = 10 or 11), then

all options of this register are valid. Any interrupt that is not automatically cleared by its

pair should be manually cleared through I²C-bus write.

The auto clear mechanism can be used to create various motor movement patterns

without being supervised by the microcontroller. For example, consider an application

where the direction of motor rotation must be automatically reversed based on signals

from two sensors placed apart from each other (sometimes referred to as ‘HOME’

positions) in a continuous manner without involving the microcontroller. The following

example shows how to program the device for such an operation.

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Example: This example assumes that two position sensors are located spaced apart and

a drive mechanism is needed to move an object back and forth between these two

sensors. Figure 7 shows this application use case. Driving the stepper motor causes

movement of the object toward one of the sensors. Logic level output of one sensor is

connected to input pin P0 and the other to P1. P0 and P1 are configured as inputs.

3.3 V

5 V

1.6 kΩ

1.1 kΩ

2 kΩ

V

DD

generates INTP0

sensor 0

MASTER

P0

P1

P2

P3

CONTROLLER

generates INTP1

sensor 1

SCL

SDA

INT

RST

RESET

PCA9629

position B

position A

electrical

stepper motor

OUT3

OUT2

OUT1

OUT0

12 V EXTERNAL

HIGH CURRENT

DRIVER

AD1

AD0

M

V

SS

002aae760

Fig 7. Example of controlling doll head movement between two home positions

At power-up, INTP0 to INTP3 flags INTSTAT[3:0] are clear (= 0).

Set INT_ACT_SETUP[0] = 1, enable interrupt based motor control.

Set INT_MTR_SETUP[1:0] = 11, Reverse motor on interrupt caused by P0 or P1.

Set INT_AUTO_CLR[1:0] = 01, INTP0 clears INTP1; INTP1 clears INTP0.

Start motor by writing MCNTL register and after some time, position sensor causes input

logic at P0 to toggle.

When the input logic level at P0 changes, the interrupt caused by P0 is latched; INTP0

flag in INTSTAT is set (= 1).

Since INT_ACT_SETUP[0] = 1 and INT_MTR_SETUP[1:0] = 11 (reverse motor on

interrupt caused by P0 or P1), the motor direction is reversed and the INTP1 flag is

cleared (since INTP0 clears INTP1). This allows interrupt generation at the end of reverse

movement by sensor at P1.

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7.3.7 SETMODE — output state on STOP control register

This register determines the condition of motor output pins when STOPPED, one of

logic 0 or Hold (last state).

Table 22. SETMODE - Output state on STOP control register (address 12h) bit description

Legend: * default value.

Address Register

Bit

Access Value Description

12h

SETMODE 7:2

1

R/W

-

reserved

1

outputs = HOLD after CCW STOP

outputs = logic 0 after CCW STOP

outputs = HOLD after CW STOP

outputs = logic 0 after CW STOP

0*

1

0

R/W

0*

7.3.8 PHCNTL — Phase Control register

This register is used to configure the phase of the output waveforms at the output ports

OUT0 to OUT3 to drive the motor coils (with external high current drivers). One of the

following three modes of drive method can be selected using these bits:

• One-phase drive (wave drive)

• Two-phase drive

• Half-step drive

Table 23. PHCNTL - Phase control register (address 13h) bit description

Legend: * default value.

Address Register Bit

Access Value Description

13h

PHCNTL 7:2

1:0

-

0*

reserved

R/W

11 or half-step drive outputs

10

01

two-phase drive outputs

one-phase drive outputs

00*

The phase drive can be changed at any time by writing to PHCNTL[1:0] bits.

7.3.9 SROTNL, SROTNH — Steps per rotation registers

This register determines how many steps are needed to execute one full turn of motor

shaft (360). This register should have a non-zero value if the requested operation is

rotations (see Section 7.3.19).

Remark: If the motor has built-in gear, the number of steps needed to complete one full

turn at the output shaft depends on the gear ratio used.

Table 24. SROTNL, SROTNH - Steps per rotation control registers (address 14h, 15h)

bit description

Legend: * default value.

Address

14h

Register

Bit

Access

R/W

Value Description

SROTNL

7:0

00h*

number of steps per one rotation, low byte

number of steps per one rotation, high byte

15h

SROTNH 7:0

R/W

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7.3.10 CWPWL, CWPWH — Clockwise step pulse width register

This register determines the step pulse width used for the phase sequence output

waveforms during ClockWise (CW) rotation.

Table 25. CWPWL, CWPWH - Clockwise step pulse width control register

(address 16h, 17h) bit description

Legend: * default value.

Address

16h

Register

CWPWL

CWPWH

Bit

7:0

Access

R/W

Value Description

00h*

step pulse width, low byte

step pulse width, high byte

17h

R/W

This register sets the pulse width value between 3 s and 3145 ms (5 %).

15

PRESCALER

P2 P1 P0

14

13

12

0

STEP PULSE WIDTH

13

13 bits (2 = 8192 steps)

002aae839

Fig 8. Step pulse width

The upper three bits of the register are the prescaler that determines the dynamic range

for the step pulse width. Table 26 shows the range for each setting of the prescaler.

Table 26. Prescaler range settings

Prescaler [P2:P0]

Decimal value (D)

2^D

1

Range

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

3 s to 24.576 ms

6 s to 49.152 ms

12 s to 98.304 ms

24 s to 196.608 ms

48 s to 393.216 ms

96 s to 786.432 ms

192 s to 1572.864 ms

384 s to 3145.728 ms

2

4

8

16

32

64

128

Remark: The values given in Table 26 are based on nominal 1 MHz internal clock.

This method gives the user access to the entire range with the smallest pulse width

(fastest speed) of 3 s at the lower end, and the largest pulse width (slowest speed) of

3145 ms at the higher end.

The prescaler value defines the range of the ramp control. The ramp-up starts from its

maximum pulse width and ramp-down ends at same maximum pulse width. The top

speed of the ramp control is defined by both PRESCALER and STEP_PULSE_WIDTH

values.

Final (top) speed = (minimum pulse width in the range defined by

PRESCALER[15:13])  (STEP_PULSE_WIDTH[12:0] + 1).

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7.3.11 CCWPWL, CCWPWH — Counter-clockwise step pulse width register

This register determines the step pulse width used for the phase sequence output

waveforms during Counter-ClockWise (CCW) rotation.

Table 27. CCWPWL, CCWPWH - Counter-clockwise step pulse width control register

(address 18h, 19h) bit description

Legend: * default value.

Address

18h

Register

Bit

Access

R/W

Value Description

CCWPWL 7:0

CCWPWH 7:0

00h*

step pulse width, low byte

step pulse width, high byte

19h

R/W

The 16-bit value sets the pulse width between 3 s and 3145 ms (5 %).

15

PRESCALER

P2 P1 P0

14

13

12

0

STEP PULSE WIDTH

13

13 bits (2 = 8192 steps)

002aae839

Fig 9. Step pulse width

The upper three bits of the register are the prescaler that determines the dynamic range

for the step pulse width. Table 28 shows the range for each setting of the prescaler.

Table 28. Prescaler range settings

Prescaler [P2:P0]

Decimal value (D)

2^D

1

Range

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

3 s to 24.576 ms

6 s to 49.152 ms

12 s to 98.304 ms

24 s to 196.608 ms

48 s to 393.216 ms

96 s to 786.432 ms

192 s to 1572.864 ms

384 s to 3145.728 ms

2

4

8

16

32

64

128

Remark: The values given in Table 28 are based on nominal 1 MHz internal clock.

This method gives the user access to the entire range with the smallest pulse width

(fastest speed) of 3 s at the lower end, and the largest pulse width (slowest speed) of

3145 ms at the higher end.

The prescaler value defines the range of the ramp control. The ramp-up is started from its

maximum pulse width and ramp-down ends at same maximum pulse width. The top

speed of the ramp control is defined by both PRESCALER and STEP_PULSE_WIDTH

values.

Final (top) speed = (minimum pulse width in the range defined by

PRESCALER[15:13])  (STEP_PULSE_WIDTH[12:0] + 1).

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7.3.12 CWSCOUNTL, CWSCOUNTH — Number of clockwise steps register

This register determines the number of steps the motor should turn in clockwise direction.

Table 29. CWSCOUNTL, CWSCOUNTH - Number of clockwise steps count register

(address 1Ah, 1Bh) bit description

Legend: * default value.

Address

1Ah

Register

Bit

Access

R/W

Value Description

CWSCOUNTL 7:0

CWSCOUNTH 7:0

00h*

number of clockwise steps, low byte

number of clockwise steps, high byte

1Bh

R/W

7.3.13 CCWSCOUNTL, CCWSCOUNTH — Number of counter-clockwise steps

register

This register determines the number of steps the motor should turn in counter-clockwise

direction.

Table 30. CCWSCOUNTL, CCWSCOUNTH - Number of counter-clockwise steps count

register (address 1Ch, 1Dh) bit description

Legend: * default value.

Address

Register

Bit

Access

Value Description

1Ch

CCWSCOUNTL 7:0

R/W

00h*

number of counter-clockwise steps,

low byte

1Dh

CCWSCOUNTH 7:0

R/W

00h*

number of counter-clockwise steps,

high byte

7.3.14 CWRCOUNTL, CWRCOUNTH — Number of clockwise rotations register

This register determines the number of full rotations the motor should turn in clockwise

direction.

Table 31. CWRCOUNTL, CWRCOUNTH - Number of clockwise rotations count register

(address 1Eh, 1Fh) bit description

Legend: * default value.

Address

1Eh

Register

Bit

Access Value Description

CWRCOUNTL 7:0

CWRCOUNTH 7:0

R/W

00h*

number of clockwise rotations, low byte

number of clockwise rotations, high byte

1Fh

7.3.15 CCWRCOUNTL, CCWRCOUNTH — Number of counter-clockwise rotations

register

This register determines the number of full rotations the motor should turn in

counter-clockwise direction.

Table 32. CCWRCOUNTL, CCWRCOUNTH - Number of counter-clockwise rotations count

register (address 20h, 21h) bit description

Legend: * default value.

Address

Register

Bit

Access

Value Description

20h

CCWRCOUNTL 7:0

R/W

00h*

number of counter-clockwise rotations,

low byte

21h

CCWRCOUNTH 7:0

R/W

00h*

number of counter-clockwise rotations,

high byte

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7.3.16 EXTRASTEPS0, EXTRASTEPS1 — Extra steps count for INTP0, INTP1

control register

Table 33. EXTRASTEPS0, EXTRASTEPS1 - Extra steps count for INTP0, INTP1 register

(address 22h, 23h) bit description

Legend: * default value.

Address

Register

Bit

Access

Value Description

22h

EXTRASTEPS0 7:0

R/W

00h*

count value for EXTRASTEPS (steps

or rotations) for INTP0

23h

EXTRASTEPS1 7:0

R/W

00h*

count value for EXTRASTEPS (steps

or rotations) for INTP1

This register has no effect if the interrupt based motor control is disabled or if the

EXTRASTEPS feature for that interrupt is disabled.

When EXTRASTEPS feature is selected using INT_ES_SETUP register bits [1:0], the

8-bit value in this register is used to determine the number of steps or rotations to be

overdriven. Direction of rotation of motor is maintained. If the count value in this register

= 0, no EXTRASTEPS occurs. Whether the count indicates the number of extra steps or

number of full rotations depends on the value of INT_ACT_SETUP control register bit 4.

If INT_ACT_SETUP[4] = 0 (default value), then EXTRASTEPSn value indicates number

of extra steps that will occur after the corresponding interrupt.

If INT_ACT_SETUP[4] = 1, then EXTRASTEPSn value indicates number of full rotations

that will occur after the corresponding interrupt.

7.3.17 RMPCNTL — Ramp control register

Table 34. RMPCNTL - Ramp control register (address 24h) bit description

Legend: * default value.

Address

Register

Bit

7:6

5

Access

R only

R/W

Value Description

24h

RMPCNTL

00*

1

reserved

enable ramp-up during start

disable ramp-up during start

enable ramp-down to stop

disable ramp-down to stop

0*

1

4

R/W

0*

3:0

R/W

0000* ramp step multiplication factor

The multiplication factor has a decimal range from 1 to 8192 as shown in Table 35.

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Table 35. Multiplication factor value for ramp-up, ramp-down control

Register value [3:0]

Decimal value (D)

Ramp step multiplication factor (2^D)

0000

0001

0010

0011

0100

0101

0110

0111

0

1

2

4

3

8

4

16

5

32

6

64

7

128

1000

1001

1010

1011

1100

1101

1110, 1111

8

256

9

512

10

11

12

13

14, 15

1024

2048

4096

8192

reserved and do not use

RMPCNTL[5:4] enables/disables the speed ramp-up during starting of the motor and

speed ramp-down during stopping of the motor.

The RMPCNTL[3:0] defines the acceleration/decelerating rate of the ramp control. If the

value is small, the PWM width decrement (accelerating)/increment (decelerating) is

slower.

The pulse width decrement and increment step is ‘smallest_pulse_step  RMPCNTL[3:0]’.

The smallest_pulse_step is defined by prescaler value of CWPWH and CCWPWH. Each

prescaler setting’s smallest_pulse_step is given in Table 26 and Table 28 (the minimum

value of the range).

The ramp control will start and end in speed of maximum_pulse_step, which is the

maximum value of the range given in Table 26 and Table 28.

The ramp-up is completed when the pulse width gets the width that is set by

CWPWL/CWPWH or CCWPWL/CCWPWH registers.

During ramp-up, the step pulse width is automatically decremented (from the maximum

value for step pulse width in the chosen range) until the value in CWPW or the CCWPW

register is reached, depending on the direction of rotation. See Figure 10.

During ramp-down, the step pulse width is automatically incremented from the current

value in CWPW or the CCWPW, depending on the direction of rotation, until it reaches the

maximum value for step pulse width in the chosen range. See Figure 10.

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During ramp-up and ramp-down phase of operation, the interrupt based controls do not

affect the motor run. An interrupt can happen during ramp-up or ramp-down and it gets

registered in the chip. Once the ramp-up operation is finished, then the interrupt is acted

upon. A stop request from the microcontroller (writing MCNTL[7] to ‘0’) is the only event

that affects the motor operation during ramp-up and ramp-down.

During ramp-up, the micro can issue a stop request. The following sequence of events

takes place in the given order:

1. If hard stop is enabled, the motor stops immediately (even if ramp-down is enabled) -

Priority 1.

2. If hard stop is disabled but ramp-down is enabled, then the motor starts to ramp down

to a stop - Priority 2.

3. If hard stop is disabled and ramp-down is disabled, then motor stops immediately -

Priority 3.

During ramp-down, the micro can issue a stop request. The following sequence of events

takes place in the given order:

1. If hard stop is enabled, the motor stops immediately (it does not finish ramping down)

- Priority 1.

2. If hard stop is disabled but ramp-down is enabled, then the motor continues to ramp

down to a stop - Priority 2.

In the duration between end of ramp-up and beginning of ramp-down, the interrupt based

controls (if enabled) can affect the operation of the motor. In this region, Section 7.3.6

gives the priority of events when both interrupt based control and ramp control are

enabled together.

7.3.18 LOOPDLY — Loop delay timer register

This feature is used to make the motor wait for a certain amount of time before reversing

its direction of rotation. There are two situations in which the motor must reverse its

direction of rotation:

• The user requests both clockwise and counter clockwise rotation (also known as auto

reversal mode).

• On an interrupt (also known as interrupt reversal mode). This register holds the wait

time value in seconds. 00h = 0 second wait time. FFh = 255 seconds wait time.

Remark: LOOPDLY has an accuracy of 5 %.

Table 36. LOOPDLY - Loop delay timer control register (address 25h) bit description

Legend: * default value.

Address

Register

Bit

Access

Value Description

00h* loop delay counter

25h

LOOPDLY 7:0

R/W

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7.3.19 MCNTL — Motor control register

This register acts like the master control panel for driving the motor. It determines the type

of motor operation and controls the starting/stopping of the motor. The registers from

address 0Eh (INT_ACT_SETUP) to 25h (LOOPDLY) are referred to as the motor

parameter registers. The user must first program the motor parameter registers that are

required for the current run of the motor. After that, this register should be programmed

with the type of operation required. The motor starts when bit 7 of this register is set.

Table 37. MCNTL - Motor control register (address 26h) bit description

Legend: * default value.

Address

Register Bit

Access

Value Description

26h

MCNTL

7

R/W

1

start motor

0*

1

stop motor

6

5

R only

R/W

reserved

hard stop enabled

hard stop disabled

0*

1

4

R/W

perform the actions specified in bits [3:0]

continuously

0*

perform the actions specified in bits [3:0] once

step pulses and then rotations

3:2

11 or

10

01

rotate for specified number of rotations

send specified number of step pulses

rotate counter-clockwise first, then clockwise

rotate clockwise first, then counter-clockwise

rotate counter-clockwise

00*

11

1:0

R/W

10

01

00*

rotate clockwise

7.3.19.1 MCNTL[7]: start/stop motor

This bit indicates the state of the motor. A ‘1’ indicates that the motor is running and

‘0’ indicates that the motor is in the stopped state.

To start the motor, write ‘1’ to this bit. Once the motor is started, any changes to the motor

parameter registers do not affect the current run of the motor except for phase changes.

Only phase changes (using the PHCNTL register) are allowed during motor operation.

Similarly, bits [6:0] of the MCNTL register cannot be changed during motor operation. The

only bit that can be changed in the MCNTL register while the motor is running is this

start/stop bit. Also, any restart command (writing ‘1’ to this bit when it is already set),

before the completion of the current operation are ignored.

When the current operation is completed, the motor stops and this bit is cleared. The

completion of motor operation can be checked by reading this bit. After the motor has

stopped, the motor parameter registers can be updated and the motor can be started

again.

The microcontroller can stop the motor at any time by writing ‘0’ to this bit (this is referred

to as a stop request). Once the motor stops, this bit is cleared. Stop request issued when

the motor is already in the stopped state is ignored.

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7.3.19.2 MCNTL[5]: hard stop

The ‘hard stop’ feature is only applicable for stop requests issued by the micro. It does not

affect the interrupt based stop mechanism. This feature is used to stop the motor

immediately when the micro issues a stop request. Hard stop feature has a higher priority

over ramp down. So even if ramp down is enabled, if the micro issues a stop request, the

motor stops immediately and does not ramp down to stop. The micro should decide how

the part should handle its stop request and accordingly enable/disable this feature. The

priority of events during a stop request is:

• If hard stop is enabled (MCNTL[5]), then the motor stops immediately.

• If ramp down is enabled (RMPCNTL[4]), the motor starts ramping down to a stop.

7.3.19.3 MCNTL[4]: continuous operation

This bit determines if the operation specified in bits [3:0] of this register is executed once

or continuously. If continuous operation is enabled, the motor can be stopped either by

issuing a stop request or if an interrupt happens and the motor is programmed to stop on

that interrupt. If continuous operation is not enabled then, the motor stops automatically

after finishing the current operation once.

7.3.19.4 MCNTL[3:2]: steps and/or rotations

These two bits determine how many steps and/or rotations are executed by the motor in

the current run. Based on clockwise or counter-clockwise direction (MCNTL[1:0]), the

clockwise registers (CWSCOUNT, CWRCOUNT) or counter-clockwise registers

(CCWSCOUNT, CCWRCOUNT) are used to determine the number steps/rotations. The

following rules should be observed while programming these bits:

• Requested operation is steps (MCNTL[3:2] = 00): Number of steps should be

non zero in the direction of operation (CW or CCW). In auto/interrupt based reversal

modes (CW and CCW), the number of steps in both directions should be non zero.

If this condition is not satisfied, the motor does not start.

• Requested operation is rotations (MCNTL[3:2] = 01): Number of rotations should be

non zero in the direction of operation (CW or CCW). In auto/interrupt based reversal

modes (CW and CCW), the number of rotations in both directions should be non zero.

If this condition is not satisfied, the motor does not start.

• Requested operation is steps and rotations (MCNTL[3:2] = 10 or 11): At least one of

the parameters, steps or rotations, should be a non zero value in the direction of

operation. In auto/interrupt based reversal modes (CW and CCW), the same rule

applies to both directions. If this condition is not satisfied, the motor does not start.

7.3.19.5 MCNTL[1:0]: clockwise (CW) / counter-clockwise (CCW)

These two bits are used to program the direction of the motor for current operation.

Options 10 and 11 are called auto reversal modes (to differentiate it from interrupt based

reversal). In these modes, the motor starts rotating in one direction and after completing

the required steps/rotations reverses the direction of rotation. If continuous mode of

operation is programmed with auto reversal, then the motor keeps repeating the operation

continuously.

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7.4 Motor coil excitation

Initially, after a power-up of the device, when the motor is started for the first time, the first

coil that is energized is OUT0 (if the motor is turning in the clockwise direction), or OUT3

(if the motor is turning in the counter clockwise direction). This very first step (after a

power-up) is not counted towards the number steps the motor is required to move (it is the

reference step). All subsequent steps are all counted. This applies only for the very first

time the motor is started after the device is powered up.

For all subsequent starting of the motor, the first coil that is energized is the same coil

where it had stopped. For example, consider the motor running in clockwise direction in

the one-phase drive mode. If the last coil that was energized before the motor stopped

was OUT2, then when the motor is started again OUT2 is energized first and after the

pulse width time elapses the next coil in sequence, that is, OUT3 is energized.

7.5 Power-on reset

When power is applied to V_DD, an internal Power-On Reset (POR) holds the PCA9629 in

a reset condition until V_DDhas reached V_POR. At that point, the reset condition is released

and the PCA9629 registers and state machine initialize to their default states. The

power-on reset typically completes the reset and enables the part by the time the power

supply is above V_POR. However, when it is required to reset the part by lowering the power

supply, it is necessary to lower it below 2 V typical.

Remark: The system level reset pulse should be > 4 s for the chip to guarantee reset

condition.

7.6 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of t_w(rst). The

PCA9629 registers and I²C-bus state machine are held in their default state until the

RESET input is once again HIGH. The RESET input has a 200 k internal pull-up to V_DD

pin.

The maximum wait time after RESET pin is released is 1 ms (typical).

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7.7 Software reset

The Software Reset Call allows all the devices in the I²C-bus to be reset to the power-up

state value through a specific formatted I²C-bus command. To be performed correctly, it

implies that the I²C-bus is functional and that there is no device hanging the bus.

The maximum wait time after software reset is 1 ms (typical).

The SWRST Call function is defined as the following:

1. A START command is sent by the I²C-bus master.

2. The reserved General Call I²C-bus address ‘0000 000’ with the R/W bit set to ‘0’

(write) is sent by the I²C-bus master.

3. The PCA9629 device(s) acknowledge(s) after seeing the General Call address

‘0000 0000’ (00h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned to

the I²C-bus master.

4. Once the General Call address has been sent and acknowledged, the master sends

one byte. The value of the byte must be equal to 06h. The PCA9629 acknowledges

this value only. If the byte is not equal to 06h, the PCA9629 does not acknowledge it.

If more than one byte of data is sent, the PCA9629 does not acknowledge anymore.

5. Once the right byte has been sent and correctly acknowledged, the master sends a

STOP command to end the software reset sequence: the PCA9629 then resets to the

default value (power-up value) and is ready to be addressed again within the specified

bus free time. If the master sends a Repeated START instead, no reset is performed.

The I²C-bus master must interpret a non-acknowledge from the PCA9629 (at any

time) as a ‘Software Reset Abort’. The PCA9629 does not initiate a software reset.

7.8 Interrupt output

The open-drain active LOW interrupt is activated by the following two mechanisms:

• Watchdog timer: If the watchdog timer is enabled and the timer times out, then an

interrupt is generated and the watchdog interrupt flag bit [3] is set in the watchdog

control register (WDCNTL).

• GPIOs: One or more of pins P0 to P3 can generate an interrupt if the following

conditions are met:

– The pin is configured as an input in the I/O configuration register (IOC).

– The interrupt from that pin is enabled in the mask interrupt register (MSK).

– The pin’s state change (rising edge or falling edge) is programmed to generate an

interrupt in the interrupt mode register (INTMODE).

The interrupt INT pin output can be enabled or disabled using MODE register bit [5]

(0 = enable; 1 = disable). The interrupt flag bit is set in the INTSTAT register when one of

the interrupts is generated from P0 to P3.

Remark: If the state of the pin does not match the contents of the Input port register,

changing an I/O from an output to an input may cause a false interrupt to occur.

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7.9 Phase sequence generator

The PCA9629 phase sequence generator uses the on-chip oscillator and control logic to

generate logic waveforms needed to support the following three types of stepper motor

drive formats:

• One-phase drive, also called ‘wave drive’

• Two-phase drive

• Half-step drive

These logic level outputs are used to drive high current power driver stages to provide

required drive current to the stepper motor coils.

7.9.1 One-phase drive (wave drive)

In one-phase drive method, only one winding is energized at any given time. The

advantage of wave drive mode is its simplicity. The disadvantage of wave drive mode is

that in the unipolar wound motor only 25 %, and in the bipolar motor only 50 % of the total

motor winding are used at any given time. This means that maximum torque output from

the motor is not made available. Since only one winding is energized, holding torque and

working torque are reduced by 30 %. This can, within limits, be compensated by

increasing supply voltage. The advantage of this form of drive is higher efficiency, but at

the cost of reduced step accuracy.

step pulses

output A

output B

output C

output D

A

B

C

D

output

disabled

rotor position

002aae757

Number of steps shown = 4 for simplicity.

Fig 11. Wave drive step sequence waveforms

Table 38. Logic output sequence for wave drive

Winding

Step

1

0

2

0

1

0

3

0

1

0

4

0

1

5

1

0

6

0

1

0

7

0

1

0

8

0

1

Winding D

Winding C

Winding B

Winding A

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7.9.2 Two-phase drive

In two-phase drive method, two windings are energized at any given time. In case of

two-phase drive, the torque output of the unipolar wound motor is lower than the bipolar

motor (for motors with the same winding parameters) since the unipolar motor uses only

50 % of the available winding, while the bipolar motor uses the entire winding.

step pulses

output A

output B

output C

output D

A

B

C

D

output

disabled

rotor position

002aae758

Number of steps shown = 4 for simplicity.

Fig 12. Two-phase drive step sequence waveforms

Table 39. Logic output sequence for two-phase drive

Winding

Step

1

0

2

0

1

0

3

0

1

4

1

0

1

5

1

0

6

0

1

0

7

0

1

8

1

0

1

Winding D

Winding C

Winding B

Winding A

7.9.3 Half-step drive (one-phase and two-phase on)

‘Half-step drive’ combines both wave and two-phase (one-phase and two-phase on) drive

modes. This results in angular movements that are half of those in 1- or 2-phases-on drive

modes. Half-stepping can reduce a phenomenon referred to as resonance, which can be

experienced in 1- or 2-phases-on drive modes.

As the name implies, in this mode it is possible to step a motor in a half-step sequence,

thus producing half steps, for example 3.75 steps from a 7.5 motor. A possible drawback

for some applications is that the holding torque is alternately strong and weak on

successive motor steps. This is because on full steps only one phase winding is

energized, while on the half-steps two stator windings are energized. Also, because

current and flux paths differ on alternate steps, accuracy is worse than when full stepping.

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step pulses

output D

output C

output B

output A

D

C

B

A

output

disabled

rotor position

002aae759

Four step stepper motor run with half-step waveforms increases the number of steps to eight.

Fig 13. Half-step drive sequence waveforms

Table 40. Logic output sequence for half-step drive

Winding

Step

1

0

2

1

0

3

0

1

0

4

0

1

0

5

0

1

0

6

0

1

7

0

1

8

1

0

1

Winding D

Winding C

Winding B

Winding A

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8. Characteristics of the I²C-bus

The I²C-bus is for two-way, two-line communication between different ICs or modules.

The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 14).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 14. Bit transfer

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 15).

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 15. Definition of START and STOP conditions

8.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 16).

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SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

2

TRANSMITTER/

MULTIPLEXER

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

SLAVE

002aaa966

Fig 16. System configuration

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold

time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 17. Acknowledgement on the I²C-bus

9. Bus transactions

Data is transmitted to the PCA9629 registers using ‘Write Byte’ transfers.

Data is read from the PCA9629 registers using ‘Read Byte’ transfers.

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10. Application design-in information

3.3 V

5 V

1.6 kΩ

1.1 kΩ

2 kΩ

V

DD

generates INTP0

sensor 0

MASTER

P0

P1

P2

P3

CONTROLLER

generates INTP1

sensor 1

SCL

SDA

INT

RST

RESET

PCA9629

position B

position A

electrical

stepper motor

OUT3

OUT2

OUT1

OUT0

12 V EXTERNAL

HIGH CURRENT

DRIVER

AD1

AD0

M

V

SS

002aae760

Device address configured as 0100 0000b for this example.

Fig 18. Typical application

10.1 Stepper motor coil driver considerations

When choosing a motor and coil driver circuit for an application, it is necessary to choose

the coil driver such that the minimum expected drive strength of the coil driver over the

anticipated operating conditions exceeds the minimum coil current in the application. For

the NMOS FETs, the gate voltage affects the FET drive strength, so it is necessary to

evaluate the FET with its gate at the minimum V_DDplanned for the PCA9629 application,

because the PCA9629 cannot drive the gate higher than the V_DD

.

For example, in most applications a 5 V power supply would have a specification like

5 V  10 % or 5 V  20 %, so it would be necessary to verify that the ON-resistance or

current sinking capability of the FET with a gate voltage of 4.75 V or 4.5 V, whichever

applies, is capable of sinking all of the current that the motor might require. Since FETs

present a capacitive load to the outputs of the PCA9629, the output asymptotically

approaches the V_DDof the part, so eventually the full V_DDappears at the output. However,

for Darlington bipolar coil drivers the input current represents a static current load that

reduces the V_OH. So depending upon the input current of the Darlington bipolar coil driver,

the PCA9629 output voltage will always be less than V_DD. This in turn reduces the input

current and also reduces the available drive current from the Darlington bipolar coil driver,

so the lowest gain for the driver and the input current gain product must be considered in

verifying that the maximum motor current can be sunk by the driver.

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10.2 Considerations when using GPIO pins P0 to P3 as inputs

For proper operation of GPIO pins as inputs, the signals at the inputs must be free from

any glitches or noise. The signals must be logic level inputs.

For example, outputs from sensors must provide logic level signals at the input pins of

PCA9629. This may require signal conditioning at the outputs of sensors. Another

example is when using P0 to P3 for key switch sensing. The inputs of PCA9629 do not

provide key de-bouncing. This is external to PCA9629 and is user-defined and supplied.

10.3 Priority of ramp control, interrupt-based control, loop delay and

hard stop

During ramp-up and ramp-down phases of operation, the interrupt-based controls do not

affect the motor run. Interrupts that occur during ramp-up or ramp-down are ignored. Once

the ramp-up operation is finished (when the motor is running at the final speed), then the

interrupts that occur are acted upon. A stop request from the microcontroller (writing 0 to

MCNTL[7]) is the only event that affects the motor operation during ramp-up and

ramp-down.

During ramp-up, the microcontroller can issue a stop request. The following sequence of

events takes place in the given order:

1. If hard stop is enabled, the motor stops immediately (even if ramp-down is enabled);

Priority 1.

2. If hard stop is disabled but ramp-down is enabled, then the motor starts to ramp down

to a stop; Priority 2.

3. If hard stop is disabled and ramp-down is disabled, then motor stops immediately;

Priority 3.

During ramp-down, the microcontroller can issue a stop request. The following sequence

of events takes place in the given order:

1. If hard stop is enabled, the motor stops immediately (it does not finish ramping down);

Priority 1.

2. If hard stop is disabled but ramp-down is enabled, then the motor continues to

ramp down to a stop; Priority 2.

In the duration between end of ramp-up and beginning of ramp-down, the interrupt-based

controls (if enabled) can affect the operation of the motor. In this region, Section 7.3.6.2

gives the priority of events when both interrupt-based control and ramp control are

enabled together. Consider the following example (the motor is programmed to reverse

rotation on an interrupt):

• Motor programmed for CW rotations; ramp-up and ramp-down enabled; reverse

rotation on interrupt P0/P1.

• When motor is started, it starts ramping up and when ramp-up is completed it rotates

at the final speed.

• If interrupt P0 happens, then it reverses rotation right away and start rotating in the

CCW direction for the specified number of rotations.

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• Before the specified number of rotations is completed in the CCW direction, if interrupt

P1 happens, then it again reverses its rotation right away and start rotating in the CW

direction for the specified number of rotations.

• If no other interrupt happens, the motor finishes executing the specified number of

rotations in the CW direction and then starts to ramp down.

In the above example, if extra steps are enabled for interrupts P0 and P1, then when the

interrupts happen the motor executes the extra steps in the current direction of rotation

and then reverses its direction.

11. Limiting values

Table 41. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_I/O

I_I/O

Parameter

Conditions

Min

Max

+6.0

5.5

Unit

V

supply voltage

0.5

voltage on an input/output pin

input/output current

input current

V_SS 0.5

V

Pn, OUTn, INT, SCL, SDA

-

50

20

210

400

+150

+85

mA

mW

C

I_I

-

I_SS

ground supply current

total power dissipation

storage temperature

ambient temperature

-

P_tot

-

T_stg

T_amb

65

40

C

12. Static characteristics

Table 42. Static characteristics

V_DD= 4.5 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Supply

Conditions

Min

Typ

Max

Unit

V_DD

I_DD

supply voltage

supply current

4.5

-

5.5

10

V

operating mode; no load;

f_SCL= 1 MHz; V_DD= 5.5 V

6

mA

I_stb

standby current

no load; f_SCL= 0 kHz;

-

1

2

mA

V_I= V_DDor V_SS; V_DD= 5.5 V

V_POR

V_PDR

power-on reset voltage

no load; V_I= V_DDor V_SS

-

2.3

2.0

-

V

[1]

power-down reset voltage

Input SCL; input/output SDA

V_IL

V_IH

I_OL

I_L

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

leakage current

0.5

0.7V_DD

30

-

+0.3V_DD

V

-

5.5

-

V

V_OL= 0.4 V; V_DD= 5.0 V

V_I= V_DDor V_SS

V_I= V_SS

40

-

mA

A

pF

1

+1

10

C_i

input capacitance

-

6

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Table 42. Static characteristics …continued

V_DD= 4.5 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

OUT0 to OUT3 outputs

Conditions

Min

Typ

Max

Unit

[2]

[3]

I_OL

LOW-level output current

V_OL= 0.5 V; V_DD= 4.5 V

I_OH= 10 mA; V_DD= 4.5 V

25

-

28

-

mA

V

I_OL(tot)

V_OH

P0 to P3 I/Os

total LOW-level output current

120

-

HIGH-level output voltage

4.0

-

[2]

[3]

I_OL

LOW-level output current

V_OL= 0.5 V; V_DD= 4.5 V

I_OH= 10 mA; V_DD= 4.5 V

3-state; V_OH= V_DDor V_SS

3-state pins as inputs

25

-

28

-

mA

V

I_OL(tot)

V_OH

I_OZ

total LOW-level output current

HIGH-level output voltage

OFF-state output current

input/output capacitance

120

-

4.0

10

-

+10

8

A

pF

C_io

5

Address inputs

V_IL

V_IH

I_LI

LOW-level input voltage

0.5

0.7V_DD

1

-

+0.3V_DD

V

HIGH-level input voltage

input leakage current

input capacitance

-

5.5

+1

5

V

-

A

pF

C_i

-

3

RESET input

V_IL

LOW-level input voltage

0.5

0.7V_DD

1

-

+0.3V_DD

5.5

V

V_IH

HIGH-level input voltage

input leakage current

input capacitance

-

V

I_LI

-

+1

A

pF

A

C_i

-

3

-

5

I_LIL

LOW-level input leakage current V_I= V_SS

7

45

INT output

I_OL

I_OH

C_o

LOW-level output current

HIGH-level output current

output capacitance

V_OL= 0.5 V; V_DD= 4.5 V

open-drain; V_OH= V_DD

24

10

-

28

-

mA

A

pF

+10

-

5

[1] In order to reset part, V_DDmust be lowered to 1.4 V.

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 210 mA due to internal busing limits.

[3] For I_OH= 25 mA, the minimum V_OH= V_DD 0.7 V with V_DD= 4.5 V to 5.5 V.

V

= 5.0 V

PMOS

DD

V

= 5.0 V

PMOS

DD

data[0:3]

enable

I/O

CONTROL

P[0:3]

(I/O)

OUTPUT

CONTROL

OUT[0:3]

(output)

NMOS

data[0:3]

NMOS

input data [0:3]

002aag587

002aag588

Fig 19. OUT[0:3] output equivalent circuit

Fig 20. P[0:3] input/output equivalent circuit

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13. Dynamic characteristics

Table 43. Dynamic characteristics

V_DD= 4.5 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Oscillator frequency = 1 MHz  5 % at 25 C (see Figure 23).

Symbol Parameter

Conditions

Standard-mode

I²C-bus

Fast-mode

I²C-bus

Fast-mode Plus Unit

I²C-bus

Min

0

Max

100

-

Min

0

Max

Min

0

Max

[1]

f_SCL

t_BUF

SCL clock frequency

400

-

1000 kHz

bus free time between a

STOP and START condition

4.7

1.3

0.5

-

s

ns

t_HD;STA

t_SU;STA

t_SU;STO

hold time (repeated) START

condition

4.0

4.7

4.0

-

0.6

-

0.26

set-up time for a repeated

START condition

set-up time for STOP

condition

t_HD;DAT

t_VD;ACK

t_VD;DAT

t_SU;DAT

t_LOW

data hold time

0

-

3.45

-

0

-

0.9

-

0

[2]

[3]

data valid acknowledge time

data valid time

0.3

250

4.7

4.0

-

0.1

100

1.3

0.6

20 +

0.05

50

0.45 s

data set-up time

-

ns

s

ns

LOW period of the SCL clock

HIGH period of the SCL clock

-

0.5

0.26

-

t_HIGH

-

[4][5]

t_f

fall time of both SDA and SCL

signals

300

120

[6]

0.1C_b

t_r

rise time of both SDA and

SCL signals

-

1000

50

20 +

0.1C_b

-

300

50

-

120

50

ns

[6]

[7]

[8]

t_SP

pulse width of spikes that

must be suppressed by the

input filter

t_d(o)

output delay time

interruptbased

motor control

latency

5.7

7.4

5.7

7.4

5.7

7.4

s

RESET

t_w(rst)

[9]

reset pulse width

1

-

4

1

-

4

1

-

4

1

s

t_rec(rst)

reset recovery time

ms

[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held

LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[2]

t_VD;ACK= time for acknowledgement signal from SCL LOW to SDA (out) LOW.

[3] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[4] In order to bridge the undefined region of the SCL falling edge, a master device must internally provide a hold time of at least 300 ns for

the SDA signal (refer to the V_ILof the SCL signal).

[5] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t_f) for the SDA output stage is specified at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum specified t_f.

[6] C_b= total capacitance of one bus line in pF.

[7] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

[8] The time delay from one of the P[1:0] inputs edge changes to the motor control outputs OUT[3:0] change. Typical value = 6.5 s.

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[9] The internal glitch filter rejects any LOW pulse less than 1 s. The system level reset pulse should be > 4 s for the chip to guarantee

reset condition.

0.7 × V

0.3 × V

DD

SDA

SCL

DD

t

r

t

f

t

SP

t

HD;STA

BUF

t

LOW

0.7 × V

0.3 × V

DD

t

SU;STO

HD;STA

SU;STA

t

SU;DAT

HD;DAT

HIGH

P

S

Sr

P

002aaa986

Fig 21. Definition of timing

ACK or read cycle

START

30 %

SCL

SDA

RESET

50 %

t

rec(rst)

t

w(rst)

50 %

P0 to P3

output off

002aag778

Fig 22. Reset timing

002aag081

1.050

f

osc

(MHz)

1.025

1.000

0.975

0.950

-40

-15

10

25 35

60

85

(°C)

T

amb

Fig 23. Typical oscillator frequency versus temperature

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14. Test information

2V

DD

open

V

SS

V

R

500 Ω

DD

L

V

O

I

PULSE

DUT

GENERATOR

C

50 pF

L

R

T

500 Ω

002aac019

R_L= load resistance.

C_L= load capacitance includes jig and probe capacitance.

R_T= termination resistance should be equal to the output impedance Z_oof the pulse generators.

Fig 24. Test circuitry for switching times for GPIO pins P0 to P3

V

DD

open

V

SS

V

DD

R

L

165 Ω

V

I

V

O

PULSE

GENERATOR

DUT

C

L

R

T

50 pF

002aaf593

R_Lfor SDA and SCL = 165  (30 mA or less current).

C_L= load capacitance includes jig and probe capacitance.

R_T= termination resistance should be equal to the output impedance Z_oof the pulse generators.

Fig 25. Test circuitry for switching times for SDA and SCL

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15. Package outline

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 26. Package outline SOT403-1 (TSSOP16)

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16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

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• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 27) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 44 and 45

Table 44. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 45. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 27.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 27. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

18. Abbreviations

Table 46. Abbreviations

Acronym

AI

Description

Auto-Increment

CCW

CDM

CMOS

CPU

CW

Counter-ClockWise

Charged-Device Model

Complementary Metal-Oxide Semiconductor

Central Processing Unit

ClockWise

DMOS

DUT

ESD

FET

double-Diffused Metal-Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Field-Effect Transistor

Fast-mode Plus

Fm+

GPIO

HBM

HVAC

I/O

General Purpose Input/Output

Human Body Model

Heating, Venting and Air Conditioning

Input/Output

I²C-bus

Inter-Integrated Circuit bus

Integrated Circuit

IC

LED

Light Emitting Diode

LSB

Least Significant Bit

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Table 46. Abbreviations …continued

Acronym Description

NMOS

MSB

PCB

pps

Negative-channel Metal-Oxide Semiconductor

Most Significant Bit

Printed-Circuit Board

pulses per second

PWM

POR

Pulse Width Modulator

Power-On Reset

19. Revision history

Table 47. Revision history

Document ID

Release date

20120229

Data sheet status

Change notice

Supersedes

PCA9629 v.1

Product data sheet

-

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20. Legal information

20.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

20.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

20.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

20.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCA9629

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 29 February 2012

49 of 51

PCA9629

NXP Semiconductors

Fm+ I²C-bus stepper motor controller

22. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.3.11

7.3.12

7.3.13

7.3.14

7.3.15

7.3.16

CCWPWL, CCWPWH — Counter-clockwise

step pulse width register . . . . . . . . . . . . . . . . 21

CWSCOUNTL, CWSCOUNTH — Number

of clockwise steps register. . . . . . . . . . . . . . . 22

CCWSCOUNTL, CCWSCOUNTH — Number

of counter-clockwise steps register . . . . . . . . 22

CWRCOUNTL, CWRCOUNTH — Number

of clockwise rotations register . . . . . . . . . . . . 22

CCWRCOUNTL, CCWRCOUNTH — Number

of counter-clockwise rotations register. . . . . . 22

EXTRASTEPS0, EXTRASTEPS1 — Extra

steps count for INTP0, INTP1 control register 23

RMPCNTL — Ramp control register . . . . . . . 23

LOOPDLY — Loop delay timer register . . . . . 26

MCNTL — Motor control register. . . . . . . . . . 27

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

7.2

7.3

7.3.1

7.3.1.1

7.3.1.2

7.3.2

Functional description . . . . . . . . . . . . . . . . . . . 5

Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5

Command register . . . . . . . . . . . . . . . . . . . . . . 6

Register definitions . . . . . . . . . . . . . . . . . . . . . . 6

MODE — Mode register . . . . . . . . . . . . . . . . . . 8

Disable interrupt output pin (bit 5) . . . . . . . . . . 8

Outputs change on STOP (bit 4) . . . . . . . . . . . 8

SUBADR1 to SUBADR3 — I²C-bus

subaddress 1 to 3. . . . . . . . . . . . . . . . . . . . . . . 9

ALLCALLADR — All Call I²C-bus address. . . . 9

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 10

WDTOI — WatchDog Time-Out Interval

register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WDCNTL — WatchDog Control register . . . . 11

GPIOs and interrupts . . . . . . . . . . . . . . . . . . . 12

IP — Input Port register . . . . . . . . . . . . . . . . . 12

INTSTAT — Interrupt Status register . . . . . . . 12

OP — Output Port register . . . . . . . . . . . . . . . 12

IOC — I/O Configuration register . . . . . . . . . . 13

MSK — Mask interrupt register. . . . . . . . . . . . 13

CLRINT — Clear Interrupts register . . . . . . . . 14

INTMODE — Interrupt Mode register . . . . . . . 14

Interrupt based motor control . . . . . . . . . . . . . 15

INT_ACT_SETUP — Interrupt Action

Setup control register . . . . . . . . . . . . . . . . . . . 16

INT_MTR_SETUP — Interrupt Motor

Setup control register . . . . . . . . . . . . . . . . . . . 16

INT_ES_SETUP — Interrupt Extra Steps

Setup control register . . . . . . . . . . . . . . . . . . . 17

INT_AUTO_CLR — Interrupt Auto Clear

register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SETMODE — output state on STOP

control register . . . . . . . . . . . . . . . . . . . . . . . . 19

PHCNTL — Phase Control register . . . . . . . . 19

SROTNL, SROTNH — Steps per rotation

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CWPWL, CWPWH — Clockwise step

7.3.17

7.3.18

7.3.19

7.3.19.1 MCNTL[7]: start/stop motor . . . . . . . . . . . . . . 27

7.3.19.2 MCNTL[5]: hard stop . . . . . . . . . . . . . . . . . . . 28

7.3.19.3 MCNTL[4]: continuous operation . . . . . . . . . . 28

7.3.19.4 MCNTL[3:2]: steps and/or rotations . . . . . . . . 28

7.3.19.5 MCNTL[1:0]: clockwise (CW) /

7.3.3

7.3.4

7.3.4.1

counter-clockwise (CCW) . . . . . . . . . . . . . . . 28

7.4

7.5

7.6

7.7

7.8

7.9

7.9.1

7.9.2

7.9.3

Motor coil excitation . . . . . . . . . . . . . . . . . . . . 29

Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . 29

RESET input . . . . . . . . . . . . . . . . . . . . . . . . . 29

Software reset . . . . . . . . . . . . . . . . . . . . . . . . 30

Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 30

Phase sequence generator . . . . . . . . . . . . . . 31

One-phase drive (wave drive) . . . . . . . . . . . . 31

Two-phase drive. . . . . . . . . . . . . . . . . . . . . . . 32

Half-step drive

7.3.4.2

7.3.5

7.3.5.1

7.3.5.2

7.3.5.3

7.3.5.4

7.3.5.5

7.3.5.6

7.3.5.7

7.3.6

(one-phase and two-phase on) . . . . . . . . . . . 32

8

Characteristics of the I²C-bus . . . . . . . . . . . . 34

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

START and STOP conditions. . . . . . . . . . . . . 34

System configuration . . . . . . . . . . . . . . . . . . . 34

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.1

8.1.1

8.2

8.3

7.3.6.1

7.3.6.2

7.3.6.3

7.3.6.4

7.3.7

9

Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 35

10

10.1

10.2

Application design-in information. . . . . . . . . 36

Stepper motor coil driver considerations . . . . 36

Considerations when using GPIO pins

P0 to P3 as inputs . . . . . . . . . . . . . . . . . . . . . 37

Priority of ramp control, interrupt-based

10.3

control, loop delay and hard stop. . . . . . . . . . 37

7.3.8

7.3.9

11

12

13

14

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38

Static characteristics . . . . . . . . . . . . . . . . . . . 38

Dynamic characteristics. . . . . . . . . . . . . . . . . 40

Test information . . . . . . . . . . . . . . . . . . . . . . . 42

7.3.10

pulse width register. . . . . . . . . . . . . . . . . . . . . 20

continued >>

PCA9629

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 29 February 2012

50 of 51

PCA9629

NXP Semiconductors

Fm+ I²C-bus stepper motor controller

15

16

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 43

Handling information. . . . . . . . . . . . . . . . . . . . 44

17

Soldering of SMD packages . . . . . . . . . . . . . . 44

Introduction to soldering . . . . . . . . . . . . . . . . . 44

Wave and reflow soldering . . . . . . . . . . . . . . . 44

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 44

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 45

17.1

17.2

17.3

17.4

18

19

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 46

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 47

20

Legal information. . . . . . . . . . . . . . . . . . . . . . . 48

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 48

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 49

20.1

20.2

20.3

20.4

21

22

Contact information. . . . . . . . . . . . . . . . . . . . . 49

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 February 2012

Document identifier: PCA9629


型号：	PCA9629PW,118
厂家：	NXP
描述：	PCA9629 - Fm+ I2C-bus stepper motor controller TSSOP 16-Pin PC
文件：	总51页 (文件大小：1022K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA9629PW,118 [NXP]

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