P87CL881H/000中文资料_数据手册_规格书

INTEGRATED CIRCUITS

DATA SHEET

P87CL881H

Low-voltage microcontroller with

63-kbyte OTP program memory

and 2-kbyte RAM

1999 Apr 16

Product speciﬁcation

File under Integrated Circuits, IC17

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

CONTENTS

1

2

3

4

5

FEATURES

GENERAL DESCRIPTION

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING INFORMATION

5.1

5.2

Pinning

Pin description

6

FUNCTIONAL DESCRIPTION

6.1

6.2

6.3

6.4

6.5

6.6

Special Function Registers

I/O facilities

Internal data memory

OTP programming

Oscillator circuitry

Non-conformance

7

LIMITING VALUES

DC CHARACTERISTICS

AC CHARACTERISTICS

AC testing

8

9

9.1

10

11

11.1

PACKAGE OUTLINE

SOLDERING

Introduction to soldering surface mount

packages

11.2

11.3

11.4

11.5

Reflow soldering

Wave soldering

Manual soldering

Suitability of surface mount IC packages for

wave and reflow soldering methods

12

13

14

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I²C COMPONENTS

1999 Apr 16

2

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

1

FEATURES

• Full static 80C51 CPU; enhanced 8-bit architecture with:

– Minimum 6 cycles per instruction (twice as fast as a

standard 80C51 core)

– Non-page oriented instructions

– Direct addressing

• Wake-up from Power-down mode via LVD or external

interrupts at Port 1

– Four 8-byte RAM register banks

• Two 16-bit timer/event counters

– Stack depth limited only by available internal RAM

(maximum 256 bytes)

• Additional 16-bit timer/event counters, with capture,

compare and PWM function

– Multiply, divide, subtract and compare instructions.

• Very low current consumption

• Watchdog Timer

• Full duplex enhanced UART with double buffering

• I²C-bus interface for serial transfer on two lines,

• Single supply voltage of 2.7 to 3.6 V

• Frequency: 1 to 10 MHz

maximum operating frequency 400 kHz.

• Operating temperature: −25 to +70 °C

• 44-pin LQFP package

2

GENERAL DESCRIPTION

• Four 8-bit ports (32 I/O lines)

The P87CL881 is an 8-bit microcontroller especially suited

for pager applications.

• 63-kbyte One-Time Programmable (OTP) program

memory; programmable in parallel mode or in-system

via I²C-bus interface.

The P87CL881 is manufactured in an advanced CMOS

technology and is based on single chip technology.

• 256-byte internal RAM

• 1792-byte internal AUX-RAM

The device is optimized for low power consumption and

has two software selectable features for power reduction:

Idle and Power-down modes. In addition, all derivative

blocks switch off their clock if they are inactive.

• External address range: 64 kbytes of ROM and

64 kbytes of RAM

• Amplitude Controlled Oscillator (ACO) suitable for use

with a quartz crystal or ceramic resonator

The instruction set of the P87CL881 is based on that of

the 80C51. The P87CL881 also functions as an arithmetic

processor having facilities for both binary and BCD

arithmetic plus bit-handling capabilities. The instruction set

consists of over 100 instructions: 49 one-byte,

46 two-byte, and 16 three-byte.

• Improved Power-on/Power-off reset circuitry (POR)

• Low Voltage Detection (LVD) with 11 software

programmable levels

• 8 interrupts on Port 1, edge or level sensitive triggering

selectable via software power-saving use for keyboard

control

This data sheet details the specific properties of the

P87CL881; for details of the P87CL881 core and the

derivative functions see the “TELX family” data sheet and

“8051-Based 8-bit Microcontrollers; Data Handbook IC20”.

• Twenty source, twenty vector interrupt structure with two

priority levels

3

ORDERING INFORMATION

TYPE

PACKAGE

PRODUCT TYPE

NUMBER⁽¹⁾

NAME

DESCRIPTION

VERSION

P87CL881H/000 Blank OTP

LQFP44

plastic low proﬁle quad ﬂat package; SOT389-1

44 leads; body 10 × 10 × 1.4 mm

P87CL881H/xxx

Factory-programmed OTP

Note

1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type

number will also specify the required program and options.

1999 Apr 16

3

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

5

PINNING INFORMATION

Pinning

5.1

handbook, full pagewidth

P1.5/INT7

P1.6/INT8/SCL

P1.7/INT9/SDA

RST

1

2

3

4

5

6

7

8

9

33 P0.4/AD4

32 P0.5/AD5

31 P0.6/AD6

30 P0.7/AD7

29 EA

P3.0/RXD/data

P87CL881H

PORENABLE/V

PP

28 EW

P3.1/TXD/clock

P3.2/INT0

27 ALE

26 PSEN

P3.3/INT1

25 P2.7/A15

24 P2.6/A14

23 P2.5/A13

P3.4/T0 10

P3.5/T1 11

MGL616

Fig.2 Pin configuration.

5

1999 Apr 16

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

5.2

Table 1 LQFP package

SYMBOL PIN

Pin description

DESCRIPTION

V_DD

39

38

17

16

4

Power supply for core.

Power supply for I/O ring.

Ground for core.

V_DDP

V_SS

V_SSP

RST

Ground for I/O ring.

RESET. A LOW level on this pin for two machine cycles while the oscillator is running,

resets the device. The RST pin is also an output which can be used to reset other ICs.

PORENABLE/V_PP

6

PORENABLE. If set to a logic 1, the internal Power-on reset circuit is enabled. If external

reset circuitry is used, it is recommended to keep PORENABLE LOW in order to achieve

the lowest power consumption. This pin is also used for the OTP programming voltage

V_PP

.

EW

28

14

Enable Watchdog Timer.

XTAL2

Crystal output. Output of the amplitude controlled oscillator. If an external oscillator

clock is used this pin not used.

XTAL1

PSEN

15

26

Crystal input. Input to the amplitude controlled oscillator. Also the input for an externally

generated clock source.

Program Store Enable. Read strobe to external program memory. When executing

code out of external program memory, PSEN is activated twice each machine cycle.

However, during each access to external data memory two PSEN activations are

skipped. During Power-down mode the PSEN pin stays HIGH.

ALE

27

Address Latch Enable. Latches the low byte of the address during accesses to external

memory. It is activated every six oscillator periods and may be used for external timing or

clocking purposes. For improved EMC behaviour, the toggle of the ALE pin can be

disabled by setting the RFI bit in the PCON register by software. This bit is cleared on

reset and can be set and cleared by software. When set, the ALE pin will be pulled-down

internally, switching an external address latch to a quiet state. The MOVX instruction will

still toggle ALE if external memory is accessed. ALE will retain its normal HIGH state

during Idle mode and a LOW state during the Power-down mode while in the EMC mode.

Additionally, during internal access (EA = 1) ALE will toggle normally when the address

exceeds the internal program memory size. During external access (EA = 0) ALE will

always toggle normally, whether the RFI bit is set or not.

EA

29

External Access. When EA is held HIGH, the CPU executes out of the internal program

memory (unless the program counter exceeds the highest address for internal program

memory). When EA is held LOW, the CPU executes out of external program memory

regardless of the value of the program counter. The state of the EA pin is internally

latched at reset.

1999 Apr 16

6

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

SYMBOL

P0.0/AD0

DESCRIPTION

37

36

35

34

33

32

31

30

40

41

42

Port 0. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used

as open-drain, standard port, high-impedance input or push-pull output, according to

Section 6.2. AD7 to AD0 provide the multiplexed low-order address and data bus during

accesses to external memory.

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

P1.0/INT2/T2

P1.1/INT3/T2EX

Port 1. 8-bit bidirectional I/O port with alternative functions. Every port pin except P1.6

and P1.7 (I²C-bus pins) can be used as open-drain, standard port, high-impedance input

or push-pull output, according to Section 6.2. Port 1 also serves the alternative functions

INT2 to INT9 interrupts, Timer 2 external input and Timer 2 compare output, external

clock output CLK and I²C-bus clock and I²C-bus data in/outputs.

P1.2/INT4/

T2COMP

P1.3/INT5

P1.4/INT6/CLK

P1.5/INT7

P1.6/INT8/SCL

P1.7/INT9/SDA

P2.0/A8

43

44

1

2

3

18

19

20

21

22

23

24

25

5

Port 2. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used

as open-drain, standard port, high-impedance input or push-pull output, according to

Section 6.2. Port 2 emits the high order address byte during accesses to external

memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses the

strong internal pull-ups when emitting logic 1's. During accesses to external memory that

use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function

Register.

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

P3.0/RXD/data

P3.1/TXD/clock

P3.2/INT0

P3.3/INT1

P3.4/T0

Port 3. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used

as open-drain, standard port, high-impedance input or push-pull output, according to

Section 6.2. RXD/data is the serial port receiver data input (asynchronous) or data I/O

(synchronous). TXD/clock is the serial port transmitter data output (asynchronous) or

clock output (synchronous). INT0 and INT1 are external interrupt lines. T0 and T1 are

external inputs for Timers 0 and 1 respectively. WR is the external memory write strobe

and RD is the external memory read strobe.

7

8

9

10

11

12

13

P3.5/T1

P3.6/WR

P3.7/RD

1999 Apr 16

7

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

6

FUNCTIONAL DESCRIPTION

For the functional and block descriptions of the P87CL881, refer to the “TELX family” data sheet.

6.1

Special Function Registers

Table 2 Special Function Registers memory map and reset values; note 1

REGISTER NAME

REGISTER MNEMONIC

SFR ADDRESS

RESET VALUE⁽²⁾

80C51 core

Accumulator

B Register

ACC

B

E0H

F0H

0000 0000

0000 0111

XXXX X000

Data Pointer Low byte

Data Pointer High byte

Program Counter High byte

Program Counter Low byte

Power Control Register

Prescaler Register

DPL

82H

DPH

PCH

PCL

83H

no SFR

87H

PCON

PRESC

PSW

SP

F3H

Program Status Word

Stack Pointer

D0H

81H

XRAM Page Register

XRAMP

FAH

Timers 0 and 1

Timer/Counter Control Register

Timer/Counter 0 High byte

Timer/Counter 1 High byte

Timer/Counter 0 Low byte

TCON

TH0

88H

8CH

8DH

8AH

8BH

89H

0000 0000

TH1

TL0

Timer/Counter 1 Low byte

TL1

Timer/Counter Mode Control Register

TMOD

Ports

Alternative Port Function Control Register

Port P0 output data Register

ALTP

A3H

80H

8EH

8FH

90H

9EH

9FH

A0H

AEH

AFH

B0H

BEH

BFH

0000 0000

1111 1111

0000 0000

0111 1111

0000 1000

0111 1111

1111 1111

0000 0000

1111 1111

1111 1110

1111 1111

P0

Port P0 Conﬁguration A Register

Port P0 Conﬁguration B Register

Port P1 output data Register

P0CFGA

P0CFGB

P1

Port P1 Conﬁguration A Register

Port P1 Conﬁguration B Register

Port P2 output data Register

P1CFGA

P1CFGB

P2

Port P2 Conﬁguration A Register

Port P2 Conﬁguration B Register

Port P3 output data Register

P2CFGA

P2CFGB

P3

Port P3 Conﬁguration A Register

Port P3 Conﬁguration B Register

P3CFGA

P3CFGB

1999 Apr 16

8

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

REGISTER NAME

REGISTER MNEMONIC

SFR ADDRESS

RESET VALUE⁽²⁾

Timer 2

Timer 2 Compare High byte

Timer 2 Compare Low byte

Timer 2 Reload/Capture High byte

Timer 2 Reload/Capture Low byte

Timer/Counter 2 Control Register

Timer/Counter 2 High byte

COMP2H

COMP2L

RCAP2H

RCAP2L

T2CON

TH2

ABH

AAH

CBH

CAH

C8H

CDH

CCH

0000 0000

Timer/Counter 2 Low byte

TL2

Interrupt logic

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Enable Register 2

Interrupt Priority Register 0

Interrupt Priority Register 1

Interrupt Priority Register 2

Interrupt Sensitivity Register 1

Interrupt Polarity Register

Interrupt Request Flag Register 1

IEN0

IEN1

IEN2

IP0

A8H

E8H

F1H

B8H

F8H

F9H

E1H

E9H

C0H

0000 0000

IP1

IP2

ISE1

IX1

IRQ1

Low Voltage Detection

LVD Control Register

PORACO

LVDCON

RSTAT

F2H

E6H

0000 0000

Reset Status Register

UART

XXX1 1000

Serial Port Buffer

S0BUF

S0CON

99H

98H

0000 0000

Serial Port Control Register

I²C-bus interface

Address Register

S1ADR

S1CON

S1DAT

S1STA

DBH

D8H

DAH

D9H

0000 0000

1111 1000

Serial Control Register

Data Shift Register

Serial Status Register

Watchdog timer

Watchdog Timer Control Register

Watchdog Timer Interval Register

WDCON

WDTIM

A5H

FFH

1010 0101

0000 0000

1999 Apr 16

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Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

REGISTER NAME

OTP interface

REGISTER MNEMONIC

SFR ADDRESS

RESET VALUE⁽²⁾

OTP Address High Register

OTP Address Low Register

OTP Data Register

OAH

D5

D4

D6

DC

D7

X00X XXXX

XXXX XXXX

000X 0000

0000 0000

OAL

ODATA

OISYS

OTEST

OTP In-System Programming Register

OTP Test Register

Notes

1. E7H and FDH are reserved locations and must not be written to.

2. Where: X = undefined state.

To enable a port pin alternative function, the port bit latch

in its SFR must contain a logic 1.

6.2

I/O facilities

6.2.1

PORTS

Each port consists of a latch (Special Function Registers

P0 to P3), an output driver and input buffer. All ports have

internal pull-ups. Figure 3(a) shows that the strong

transistor P1 is turned on for only 1 oscillator period after a

LOW-to-HIGH transition in the port latch. When on, it turns

on P3 (a weak pull-up) through the inverter IN1. This

inverter and transistor P3 form a latch which holds the

logic 1.

The P87CL881 has 32 I/O lines treated as 32 individually

addressable bits or as four parallel 8-bit addressable ports.

Ports 0, 1, 2 and 3 perform the following alternative

functions:

Port 0 Provides the multiplexed low-order address and

data bus for expanding the device with standard

memories and peripherals.

Port 1 Used for a number of special functions:

6.2.2

PORT I/O CONFIGURATION

• P1.0 to P1.7 provides the inputs for the external

interrupts INT2 to INT9

I/O port output configurations are determined by the

settings in the port configuration SFRs. Each port has two

associated SFRs: PnCFGA and PnCFGB, where ‘n’

indicates the specific port number (0 to 3). One bit in each

of the 2 SFRs relates to the output setting for the

corresponding port pin, allowing any combination of the

2 output types to be mixed on those port pins.

• P1.0/T2 and P1.1/T2EX for external inputs of Timer 2

• P1.2/T2COMP for external activation and compare

output of Timer 2

• P1.4/CLK for the clock output

• P1.6/SCL and P1.7/SDA for the I²C-bus interface are

real open-drain outputs or high-impedance; no other

port configurations are available.

For example, the output type of P1.3 is controlled by

setting bit 3 in the SFRs P1CFGA and P1CFGB.

The port pins may be individually configured via the SFRs

with one of the following modes (P1.6 and P1.7 can be

open-drain or high-impedance but never have any diodes

against V_DD).

Port 2 Provides the high-order address bus when

expanding the device with external program

memory and/or external data memory.

Port 3 Pins can be configured individually to provide:

Mode 0 Open-drain; quasi-bidirectional I/O with

n-channel open-drain output. Use as an output

(e.g. Port 0 for external memory accesses

(EA = 0) or access above the built-in memory

boundary) requires the connection of an external

pull-up resistor. The ESD protection diodes

against V_DDand V_SSare still present. Except for

the I²C-bus pins P1.6 and P1.7, ports which are

configured as open-drain still have a protection

diode to V_DD. See Fig.3a.

• P3.0/RXD/data and P3.1/TXD/clock which are serial

port receiver input and transmitter output (UART)

• P3.2/INT0 and P3.3/INT1 are external interrupt request

inputs

• P3.4/T0 and P3.5/T1 as counter inputs

• P3.6/WR and P3.7/RD are control signals to write and

read to external memories.

1999 Apr 16

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Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

Mode 1 Standard port; quasi-bidirectional I/O with

pull-up. The strong pull-up p1 is turned on for

only one oscillator periods after a LOW-to-HIGH

transition in the port latch. After these two

oscillator periods the port is only weakly driven

through p2 and ‘very weakly’ driven through p3.

See Fig.3b.

Tables 2 and 3 show the configuration register settings for

the four output configurations. The electrical

characteristics of each output configuration are specified

in Chapter 8. The default port configuration after reset is

given in Table 2.

In case of external memory access, the appropriate

options for ports P0, P2 and P3.6/P3.7 (WR/RD, only in

case of external data memory access) must be set by

software.

Mode 2 High-impedance; this mode turns all port output

drivers off. Thus, the pin will not source or sink

current and may be used as an input-only pin with

no internal drivers for an external device to

overcome. See Fig.3c.

For Special Function Registers for port configurations/data

please refer to Table 2, note 1.

Mode 3 Push-pull; output with drive capability in both

polarities. In this mode, pins can only be used as

outputs. See Fig.3d.

Table 3 Port conﬁguration register settings

PORT OUTPUT CONFIGURATION

MODE⁽¹⁾

PnCFGA

PnCFGB

NORMAL PORTS

I²C-BUS PORTS (P1.6 AND P1.7)

0

1

2

3

0

1

0

1

0

1

open-drain

quasi-bidirectional

high-impedance

push-pull

open-drain

high-impedance

open-drain

Note

1. Mode changes may cause glitches to occur during transitions. When modifying both registers, write instructions

should be carried out consecutively.

1999 Apr 16

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Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

handbook, full pagewidth

V

external

V

DD

this diode is not

implemented

on the I C-bus pins

external

pull-up

2

I/O pin

Q

from port latch

n

V

SS

MBK004

input data

a. Open-drain.

handbook, full pagewidth

V

strong pull-up

DD

1 oscillator

period

p2

p3

p1

n

I/O pin

Q

from port latch

IN1

V

SS

MBK001

input data

b. Standard/quasi-bidirectional.

V

handbook, full pagewidth

DD

this diode is not

implemented

2

on the I C-bus pins

input data

I/O pin

MBK002

V

SS

c. High-impedance.

strong pull-up

handbook, full pagewidth

V

DD

V

DD

p

I/O pin

Q

from port latch

n

V

SS

MBK003

input data

d. Push-pull.

Fig.3 Port configuration options.

1999 Apr 16

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Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

instructions in the same way as in the 80C51 structure, so

with P0 and P2 as data/address bus and P3.6 and P3.7 as

write and read timing signals. Note that the external data

memory cannot be accessed with R0 and R1 as address

pointer if the AUX-RAM is enabled (ARD = 0, default after

reset).

6.3

Internal data memory

The internal data memory is divided into three physically

separated parts:

256 bytes of RAM, 128 bytes of Special Function

Registers and 1792 bytes of AUX-RAM. These can be

addressed each in a different way (see also Table 4).

The Special Function Registers (SFR) can only be

1. RAM 0 to 127 can be addressed directly and indirectly

as in the 80C51; address pointers are R0 and R1 of

the selected register-bank

addressed directly in the address range from 128 to 255.

Four register banks, each 8 registers wide, occupy

locations 0 through 31 in the lower RAM area. Only one of

these banks may be enabled at a time. The next 16 bytes,

locations 32 through 47, contain 128 directly addressable

bit locations. The stack can be located anywhere in the

internal 256 bytes RAM. The stack depth is only limited by

the available internal RAM space of 256 bytes (see Fig.4).

2. RAM 128 to 255 can only be addressed indirectly;

address pointers are R0 and R1 of the selected

register bank

3. AUX-RAM 0 to 1791 is indirectly addressable via the

AUX-RAM Page Register (XRAMP) and MOVX-Ri

instructions, unless it is disabled by setting ARD = 1.

AUX-RAM 0 to 1791 is also indirectly addressable as

external data memory via MOVX-datapointer

Table 4 Internal data memory map

LOCATION ADDRESS

ADDRESSING

instruction, unless it is disable by setting ARD = 1.

When executing from internal program memory, an

access to AUX-RAM 0 to 1791 when ARD = 0 will not

affect the ports P0, P2, P3.6 and P3.7.

RAM

0 to 127

direct and indirect

indirect only with MOVX

indirect only

AUX-RAM

RAM

0 to 1791

128 to 255

An access to external data memory locations higher

than 1791 will be performed with the MOVX @ DPTR

SFR

direct only

FFFFH

handbook, full pagewidth

FFFFH

FBFFH

(ARD = 0/1)

0700H

06FFH

PAGE 6

PAGE 5

PAGE 4

PAGE 3

PAGE 2

PAGE 1

PAGE 0

FFH

INDIRECT

ADDRESSING

(ARD = 1)

DIRECT

7FH

INDIRECT AND

DIRECT

ADDRESSING

INTERNAL

(EA = 1)

EXTERNAL

(EA = 0)

00H

0000H

INTERNAL RAM

INTERNAL

AUX-RAM

(ARD = 0)

EXTERNAL DATA

MEMORY

0

MGL618

PROGRAM MEMORY

DATA MEMORY

Fig.4 Memory map.

13

1999 Apr 16

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

6.3.1

AUX-RAM PAGE REGISTER (XRAMP)

The AUX-RAM Page Register is used to select one of the seven 256 bytes pages of the internal 1792-byte AUX-RAM

for MOVX-accesses via R0 or R1. Its reset value is ‘XXXX X000’ (AUX-RAM page 0).

Table 5 AUX-RAM Page Register (SFR address FAH)

7

6

5

4

3

2

1

0

−

XRAMP2

XRAMP1

XRAMP0

Table 6 Description of XRAMP bits

BIT

SYMBOL

−

FUNCTION

7 to 3

reserved, undeﬁned during read, a write operation must write logic 0 to these locations

AUX-RAM page select bit 2

2

1

0

XRAMP2

XRAMP1

XRAMP0

AUX-RAM page select bit 1

AUX-RAM page select bit 0

Table 7 Memory locations for all possible MOVX accesses

ARD⁽¹⁾XRAMP2 XRAMP1 XRAMP0

ACCESS

INSTRUCTION TYPE

0

1

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

AUX-RAM page 0 (address 0 to 255)

AUX-RAM page 1 (address 256 to 511)

AUX-RAM page 2 (address 512 to 767)

AUX-RAM page 3 (address 768 to 1023)

AUX-RAM page 4 (address 1024 to 1279)

AUX-RAM page 5 (address 1280 to 1535)

AUX-RAM page 6 (address 1536 to 1791)

no valid memory access

MOVX @ Ri, A and

MOVX @ A, Ri

external RAM locations 0 to 255

AUX-RAM locations 0 to 1791 external

RAM locations 1792 to 65535

MOVX @ DPTR, A and

MOVX A, DPTR

1

X

external RAM locations 0 to 65535

Note

1. ARD (AUX-RAM Disable) corresponds to bit 6 in the Special Function Register PCON (address 87H).

1999 Apr 16

14

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

6.4

OTP programming

6.4.2

IN-SYSTEM PROGRAMMING MODE

In the In-System Programming mode the OTP can be

programmed under control of the CPU. A program to

control programming has to be available in the OTP. This

mode can be used to program several bytes in the OTP if

the chip is already in a system e.g. to store tuning

parameters.

6.4.1

OTP PROGRAMMING

The 63-kbyte One-Time Programmable (OTP) memory

can be programmed by using an OM4260 programmer

together with a programmer adapter OM5510. Since the

memory is programmable only once, programming an

already programmed address results in a logical AND of

the old and new code. The OTP code can be read out by

the programmer for verification.

In the In-System Programming mode the complete

address space OTP can be programmed.

The user should take care not to overwrite the existing

code.

6.4.1.1

Signature bytes

For In-System Programming four SFRs are used to control

the OTP.

The OTP memory contains three signature bytes which

can be read by the programmer to identify the device.

A special address space has been used for these bytes

which does not influence the user address space.

The values of the signature bytes are:

Table 8 SFRs for In-System Programming

SFR NAME

DESCRIPTION

(030H) = 15H, indicates manufactured by Philips

Semiconductors

OAH

OTP Address High Register

OTP Address Low Register

OTP Data Register

OAL

(031H) = D6H, indicates P87CL881H

(060H) = 00H, currently not used.

ODATA

OISYS

OTP In-System Register

6.4.2.1

OTP In-System Programming Register (OISYS)

The OISYS SFR controls the In-System Programming mode. The data that has to be programmed is stored in the SFR

ODATA and the address for this data in the SFRs OAH and OAL.

Table 9 OTP In-System Programming Register (SFR address DCH)

7

6

5

4

3

2

1

0

−

VPon

0

SIG

WE

InSysMode

Table 10 Description of OISYS bits

BIT

SYMBOL

DESCRIPTION

7 to 5

−

VPon

0

These bits are reserved.

V_PPstatus (read only).

4

3

2

1

0

This bit is reserved and must be kept to logic 0.

Signature bytes enable.

SIG

WE

Write Enable, enables programming.

InSysMode In-System Programming status bit.

1999 Apr 16

15

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

The signature bytes (and other test addresses) are always

readable independent of the security.

6.4.2.2

Mode entry

The In-System Programming mode is entered by setting

the InSysMode bit of the OISYS SFR. The I²C-bus is used

for data transfer in this mode. If the I²C-bus interface is

addressed by an external master, the interface generates

an interrupt request. The interrupt handler can now read

the OISYS SFR and determine the status of the external

high voltage (VPon). If high voltage is not present the

interrupt is a standard I²C-bus interrupt.

6.4.2.6

How to connect the PORENABLE/V_PPpin in

the In-System Programming mode

If the V_PPpin is dual-mode (e.g. PORENABLE/V_PP), ICs

connected to the signal PORENABLE must be able to

withstand up to 13 V, i.e. cannot have clamping diodes or

low break-down voltages. If the pin is connected to a fixed

voltage (V_DDor V_SS) there must be a way of switching-off

this connection on the PCB. A possible implementation is

presented in Fig.5.

If high voltage is present the In-System program interrupt

routine has to start that writes the InSysMode bit

(OISYS.0) and controls the address and data transfer.

In the example (see Fig.5) the POR is enabled in normal

mode of operation (pin PORENABLE/V_PP= 1 by the

pull-up), but the V_PPsource must supply enough current

in R_pin order to guarantee a minimum 12.5 V on the

PORENABLE/V_PPpin.

The program voltage has to be available and stable for at

least 10 µs before the mode is entered and has to be

stable until the circuit has left the In-System Programming

mode. The high voltage can be applied for maximum

60 seconds during the complete lifetime of the circuit.

Note that if in the application the Power-on reset is

disabled (pin PORENABLE/V_PP= 0), applying a high

voltage to the PORENABLE/V_PPpin will also enable the

POR circuit. This will cause a reset independent of the

actual V_DDvalue.

6.4.2.3

Program cycle

The data and address must be supplied to the

microcontroller and the control program has to write the

SFRs: ODATA, OAH and OAL. A timer has to be initialized

for a 100 µs cycle and the WE bit of the OISYS SFR must

be set. Now the core has to be set into Idle mode. As long

as the circuit is in Idle mode a programming pulse is

applied. After the interrupt request of the timer the OTP is

available for normal code fetching.

V

handbook, halfpage

DD

R

p

The address applied to the OAH and OAL SFRs must be

in the 63 kbytes address space.

V

pad on PCB

PP

6.4.2.4

Verify for In-System Programming

44

34

Verify is done in similar way as programming. The circuit

is put into Idle mode and at the start of this mode the sense

amplifiers are switched to verify mode and a read cycle is

started. The timer has to be initialized for a cycle of at least

1 µs. The address is supplied by the SFRs OAH and OAL.

The WE bit of the OISYS SFR has to be reset. The OTP

output data is latched in the ODATA SFR. After Idle mode

is finished this SFR can be read in a normal way. To be

sure that the verified data is written into the SFR it is

advised to write FFH into the ODATA SFR before a verify

is started.

1

6

33

P87CL881H

11

23

12

22

6.4.2.5

Signature bytes

MBL001

The signature bytes can be read by setting the SIG bit of

the OISYS SFR and applying the address of the signature

byte. Applying a write pulse while the SIG bit of the OISYS

SFR is HIGH is forbidden although the contents of the

signature bytes will never be destroyed.

Fig.5 Example of PORENABLE/V_PPconnection

on a PCB.

1999 Apr 16

16

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

6.5

Oscillator circuitry

6.6

Non-conformance

General information on the oscillator circuitry can be found

in the “TELX family” data sheet.

6.6.1

PROGRAMMING INTERFACE/TRANSPARENT MODE

The transparent mode is a special operating mode of the

microcontroller used for parallel and In-System OTP

programming.

6.5.1

RESONATOR REQUIREMENTS

For correct function of the oscillator, the values

For certain combinations of data written to Port 2 (used for

control signal during parallel programming mode) the

Transparent mode may be incorrectly active during normal

operation of the microcontroller. In this case, a transition

on any of the Port 0 pins can influence the read out of the

on-chip program memory resulting in incorrect code

execution.

of R₁and C₀of the chosen resonator (quartz or PXE) must

be below the line shown in Fig.6a. The value of the parallel

resistor R₀must be less than 47 kΩ. The wiring between

chip and resonator should be kept as short as possible.

To avoid this problem, the InSysMode bit in the OTP

In-System Programming Register (SFR address DCH)

must be set in the start-up sequence of the program code.

MDA088

500

handbook, halfpage

R1

(Ω)

400

300

Apart from preventing incorrect operation as described

above, the setting of this bit does not affect the normal

operation.

(1)

(2) (3)

6.6.2

MOVC INSTRUCTION LIMITATION

200

The ‘MOVC’ access to a data or program byte stored in

internal ROM/OTP-memory is inhibited while fetching

code from external program memory in roll-over mode.

100

0

Roll-over mode means that the CPU executes code out of

the external program memory because the program

counter exceeds the highest address for internal program

memory. The affected address range is FC00H to FFFFH.

0

20

40

60

80

C

(pF)

o

6.6.3

LOW VOLTAGE DETECTION

C_1eand C_2eare the external load capacitances; normally not needed

due to integrated load capacitances of typically 10 pF.

The LVDI bit (LVDCON.6) may be incorrectly set due to a

glitch on the LVD output when the LVD is enabled by

changing the bits LVDCON<3:0> from ‘0000’ to any value

within the range ‘0001’ to ‘0101’. If bit EA in register IEN0

is enabled, an unwanted interrupt may occur.

(1) C_1e= C_2e= 22 pF.

(2)

C_1e= C_2e= 0 pF.

(3) C_1e= C_2e= 12 pF.

a. Resonator curves for 3.58 MHz.

A software workaround for this problem exist. During the

initialisation sequence:

C

• Enable LVD by writing to register LVDCON

L

R

1

handbook, halfpage

1

• Enable LVD interrupt by writing to register IEN2

• Clear the LVDI bit by writing to LVDCON a second time

R

0

MGL137

• Set bit EA in register IEN0 (ensures LVDI to be cleared

C

0

after initialisation).

b. Resonator equivalent circuit.

Fig.6 Resonator requirements for the ACO.

1999 Apr 16

17

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

7

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

PARAMETER

MIN.

−0.5

MAX.

+4.0

UNIT

V_DD

V_I

supply voltage

V

input voltage on any pin with respect to ground (V_SS

total power dissipation

)

−0.5

−

V_DD+ 0.5

800

P_tot

T_stg

mW

storage temperature

−65

+150

°C

8

DC CHARACTERISTICS

V_DD= 2.7 to 3.6 V; V_SS= 0 V; f_xtal= 1 to 10 MHz; T_amb= −25 to +70 °C; all voltages with respect to V_SS; unless

otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

V_DD

supply voltage

operating

2.7

−

3.6

V

RAM data retention in

Power-down mode

1.0

3.6

V

V_PP

I_DD

OTP programming voltage

supply current operating

12.5

−

13.0

4.8

−

V

V_DD= 3 V; f_xtal= 7 MHz; note 1

−

mA

T

_amb= 25 °C

V_DD= 3 V; f_xtal= 7 MHz; note 2

_amb= 25 °C

3.7

−

I_DD(id)

supply current Idle mode

0.7

−

T

0.58

I_DD(pd)

supply current Power-down V_DD= 3 V; T_amb= 25 °C; note 3

mode

POR and LVD enabled

−

2

5

µA

POR and LVD disabled

50

−

nA

I_DD(block)

supply current per block:

Watchdog

V_DD= 3 V; f_xtal= 7 MHz; T_amb= 25 °C;

notes 4 and 5

−

220

180

10

−

µA

I²C-bus

UART

Timer T2

Timer T0 or T1

1999 Apr 16

18

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Inputs (ports, RST and PORENABLE)

V_IL

V_IH

I_IL

LOW-level input voltage

HIGH-level input voltage

notes 6 and 7

0

−

0.2V_DD

V_DD

V

note 6

0.8V_DD

V

LOW-level input current

(ports in Mode 1)

V_IN= 0.4 V; note 8 and Fig.8

−

10

50

µA

I_IL(T)

LOW-level input current;

HIGH-to-LOW transition

(ports in Mode 1)

V_IN= 0.2V_DD; note 8 and Fig.8

−

200

1000

1

µA

I_ILEAK

input leakage current (ports

in Mode 0 or 2)

V_SS≤ V_I≤ V_DD

−

Outputs (ports and RST)

I_OL

LOW-level output current;

except SDA and SCL

V_OL= 0.4 V

2

3

2

−

mA

I_OL2

I_OH

LOW-level output current;

SDA and SCL

V_OL= 0.4 V; note 9

HIGH-level output current

except (push-pull options

only)

V_OH= V_DD− 0.4 V

I_RST

RST pull-up current source V_DD= 3 V; V_OH= V_DD− 0.4 V

_DD= 3 V; V_OH= V_SS

POR (Power-on reset) for the LVD (Low Voltage Detection), see note 10

0.05

0.2

0.6

−

µA

V

−

2.5

V_PORH

trip level HIGH

(option 5 in “TELX family

speciﬁcation”)

2.13

2.37

1.30

2.61

V

V_PORL

trip level LOW

(option B in “TELX family

speciﬁcation”)

−

ACO (Amplitude Controlled Oscillator)

V_XTAL1

external clock signal

500

−

V_DD

mV

amplitude peak-to-peak

z_i(XTAL1)

C_1i; C_2i

input impedance on XTAL1

300

1000

10

−

kΩ

input capacitance on

XTAL1 and XTAL2

notes 5 and 11

−

pF

In-System Programming for the OTP

t_progprogram cycle time

t_{prog(security)}program cycle time security note 12

90

180

1

100

200

−

110

220

−

µs

s

t_ver

verify cycle time

t_VPP(setup)

t_VPP(max)

program voltage setup time

10

−

maximum program voltage cumulative for the product lifetime

time

−

60

I_VPP

program voltage current

In-System Programming

−

40

mA

1999 Apr 16

19

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

Notes

1. The operating supply current is measured with all output pins disconnected; V_IL= V_SS; V_IH= V_DD; RST = V_DD; XTAL1

driven with square wave; XTAL2 not connected; fetch of NOP instructions; all derivative blocks disabled.

2. The Idle mode supply current is measured with all output pins and RST disconnected; V_IL= V_SS; V_IH= V_DD; XTAL1

driven with square wave; XTAL2 not connected; all derivative blocks disabled.

3. The power-down current is measured with all output pins and RST disconnected; V_IL= V_SS; V_IH= V_DD; XTAL1 and

XTAL2 not connected.

4. The typical currents are only for the specific block. To calculate the typical power consumption of the microcontroller,

the current consumption of the CPU must be added. Example: the typical current consumption of the microcontroller

in operating mode with CPU, Watchdog and UART active can be calculated as (3.7 + 0.220 + 0.18) mA = 4.1 mA at

V_DD= 3 V and f_XTAL= 7 MHz.

5. Verified on sampling basis.

6. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I²C-bus specification. Therefore, an input voltage

below 0.3V_DDwill be recognized as a logic 0 and an input voltage above 0.7V_DDwill be recognized as a logic 1.

7. For pin PORENABLE the V_ILmax is 0.1V_DD

.

8. Not valid for pins SDA, SCL, RST and PORENABLE.

9. The maximum allowed load capacitance C_Lis in this case limited to around 200 pF.

10. The LVD is tested according to the “TELX family specification, Chapter - Low voltage detection”.

11. C_1i/C_2iare the total internal capacitances (including gate capacitance and leadframe capacitance).

12. Can also be done by two 100 µs pulses.

handbook, full pagewidth

MGL506

500 µA

I

IL(T)

I

IL

10 µA

0

0.3V

0.5V

V

DD

Fig.7 Input current.

1999 Apr 16

20

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

MGL625

MGL626

5.3

1.0

handbook, halfpage

I

DD

DD(id)

(mA)

4.7

0.8

4.1

3.5

0.6

0.4

2.9

2.2

0.2

2.2

2.6

3

3.4

3.8

V

4.2

(V)

2.6

3

3.4

3.8

V

DD

4.2

(V)

DD

Fig.8 Typical operating current as a function of

Fig.9 Typical Idle current as a function of V_DD;

V_DD; T_amb= 25 °C; f_xtal= 7 MHz.

T_amb= 25 °C; f_xtal= 7 MHz.

MDA085

4

handbook, halfpage

I

DD(pd)

(µA)

(1)

3

(2)

2

1

(3)

(4)

0

1

2

3

4

V

(V)

DD

(1) POR and LVD enabled (T_amb= 70 °C).

(2) POR and LVD enabled (T_amb= 25 °C).

(3) POR and LVD disabled (T_amb= 70 °C).

(4) POR and LVD disabled (T_amb= 25 °C).

Fig.10 Typical power-down current as a function of

V_DD

.

1999 Apr 16

21

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

9

AC CHARACTERISTICS

_DD= 3 V; V_SS= 0 V; T_amb= −25 to +70 °C; C_L= 50 pF for Port 0, ALE and PSEN; C_L= 80 pF for all other outputs

V

unless otherwise speciﬁed. All values veriﬁed on sampling basis.

VARIABLE CLOCK

MIN. MAX.

SYMBOL

PARAMETER

UNIT

External program memory

t_LHLL

t_AVLL

t_LLAX

t_LLIV

ALE pulse width

address valid to ALE LOW

t_CLK

−

ns

0.5t_CLK− 10

ns

address hold after ALE LOW

ALE LOW to valid instruction in

ALE LOW to PSEN LOW

0.5t_CLK

−

2t_CLK− 25

t_LLPL

t_PLPH

t_PLIV

t_PXIX

t_PXIZ

t_AVIV

t_PLAZ

0.5t_CLK

−

PSEN pulse width

1.5t_CLK

−

PSEN LOW to valid instruction in

input instruction hold after PSEN

input instruction ﬂoat after PSEN

address to valid instruction in

PSEN LOW to address ﬂoat

−

0

−

1.5t_CLK− 35

−

0.5t_CLK

2.5t_CLK− 35

5

External data memory

t_RLRH

t_WLWH

t_AVLL

RD pulse width

3t_CLK

−

ns

WR pulse width

3t_CLK

−

address valid to ALE LOW

address hold after ALE LOW

RD LOW to valid data in

data hold after RD

0.5t_CLK

−

t_LLAX

0.5t_CLK

−

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

t_AVDV

t_LLWL

t_AVWL

t_WHLH

t_QVWX

t_QVWH

t_WHQX

t_RLAZ

−

2.5t_CLK

0

−

data ﬂoat after RD

−

t_CLK

ALE LOW to valid data in

address to valid data in

ALE LOW to RD or WR LOW

address valid to RD or WR LOW

RD or WR HIGH to ALE HIGH

data valid to WR transition

data valid time WR HIGH

data hold after WR

−

4t_CLK

−

4.5t_CLK− 30

1.5t_CLK− 15

2t_CLK

1.5t_CLK+ 15

−

0.5t_CLK− 5

0.5t_CLK

3.5t_CLK

0.5t_CLK

−

0.5t_CLK+ 5

−

0

RD LOW to address ﬂoat

1999 Apr 16

22

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

one machine cycle

handbook, full pagewidth

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

P1 P2

P1 P2 P1 P2 P1 P2

P1 P2

XTAL1

INPUT

ALE

PSEN

RD

dotted lines

are valid when

RD or WR are

active

only active

during a read

from external

data memory

only active

during a write

to external

WR

data memory

BUS

(PORT 0)

inst.

in

address

A0 - A7

inst.

in

address

A0 - A7

inst.

in

address

A0 - A7

inst.

in

address

A0 - A7

external

program

memory

fetch

PORT 2

address A8 - A15

BUS

(PORT 0)

inst.

in

address

A0 - A7

inst.

in

address

A0 - A7

address

A0 - A7

data output or data input

read or

write of

external data

memory

address A8 - A15

address A8 - A15 or Port 2 out

address A8 - A15

PORT 2

PORT

OUTPUT

old data

new data

PORT

INPUT

sampling time of I/O port pins during input (including INT0 and INT1)

SERIAL

PORT

CLOCK

MGA180

Fig.11 Instruction cycle timing.

23

1999 Apr 16

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

t

CY

handbook, full pagewidth

t

LLIV

LHLL

ALE

PSEN

t

LLPL

t

PLPH

t

LLAX

t

PXIZ

AVLL

PLIV

PORT 0

PORT 2

A0 to A7

inst. input

A0 to A7

inst. input

t

PXIX

PLAZ

t

AVIV

address A8 to A15

MGA176

Fig.12 Read from external program memory.

t

CY

handbook, full pagewidth

ALE

t

LHLL

LLDV

WHLH

PSEN

RD

t

RLRH

LLWL

t

RHDZ

AVLL

LLAX

t

RHDX

AVWL

RLDV

PORT 0

PORT 2

A0 to A7

data input

t

RLAZ

t

AVDV

address A8 to A15 (DPH) or Port 2

MGA177

Fig.13 Read from external data memory.

24

1999 Apr 16

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

t

CY

handbook, full pagewidth

t

WHLH

LHLL

ALE

PSEN

t

WLWH

LLWL

WR

t

AVWL

t

AVLL

LLAX

QVWH

WHQX

t

QVWX

PORT 0

PORT 2

A0 to A7

data output

address A8 to A15 (DPH) or Port 2

MGA178

Fig.14 Write to external data memory.

9.1

AC testing

AC testing inputs are driven at 2.4 V for a HIGH level and 0.45 V for a LOW level. Timing measurements are taken at

2.0 V for a HIGH level and 0.8 V for a LOW level, see Fig.15a. The float state is defined as the point at which a Port 0

pin sinks 3.2 mA or sources 400 µA at the voltage test levels, see Fig.15b.

V

OH(min)

handbook, full pagewidth

V

IH(min)

V

IL(max)

V

OL(max)

MGL620

a. AC inputs during testing are driven at V_OH(min)for a logic 1 and V_OL(max)for a logic 0. Timing measurements

are made at V_IH(min)for a logic 1 and V_IL(max)for a logic 0.

V

− 0.1 V

handbook, full pagewidth

OH

OL

V

− 0.1 V

LOAD

V

= 0.5 V

DD

LOAD

MGL619

b. For timing purposes, a port is no longer floating when a 100 mV change from load voltage occurs and begins

to float when a 100 mV change from the loaded V_OH/V_OLlevel occurs. I_OH/I_OL> 1.6 mA.

Fig.15 AC testing input, output waveform (a) and float waveform (b).

1999 Apr 16

25

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

10 PACKAGE OUTLINE

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm

SOT389-1

c

y

X

33

23

A

E

34

22

Z

E

e

Q

H

E

A

2

A

(A )

3

A

1

w M

p

pin 1 index

θ

b

L

p

L

44

12

detail X

11

1

Z

v M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

Q

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.45 0.20 10.10 10.10

0.30 0.12 9.90 9.90

12.15 12.15

11.85 11.85

0.75 0.70

0.45 0.57

1.14 1.14

0.85 0.85

mm

1.60

0.25

0.80

1.0

0.20 0.20 0.10

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-12-19

SOT389-1

1999 Apr 16

26

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

11 SOLDERING

11.1 Introduction to soldering surface mount

packages

• For packages with leads on two sides and a pitch (e):

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population densities. In these situations reflow

soldering is often used.

The footprint must incorporate solder thieves at the

downstream end.

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

11.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating

method.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 230 °C.

11.4 Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

11.3 Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

1999 Apr 16

27

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

11.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE

WAVE

REFLOW⁽¹⁾

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable⁽²⁾

PLCC⁽³⁾, SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended⁽³⁾⁽⁴⁾

not recommended⁽⁵⁾

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

1999 Apr 16

28

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

12 DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

13 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

14 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1999 Apr 16

29

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

NOTES

1999 Apr 16

30

Philips Semiconductors

Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

NOTES

1999 Apr 16

31

Philips Semiconductors – a worldwide company

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Philippines: Philips Semiconductors Philippines Inc.,

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Slovakia: see Austria

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Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

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MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

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Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA63

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

465008/00/01/pp32

Date of release: 1999 Apr 16

Document order number: 9397 750 05026

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP, QFP44,.47SQ,32	针数：	44
Reach Compliance Code：	compliant	HTS代码：	8542.31.00.01
风险等级：	5.77	具有ADC：	NO
地址总线宽度：	16	位大小：	8
CPU系列：	8051	最大时钟频率：	10 MHz
DAC 通道：	NO	DMA 通道：	NO
外部数据总线宽度：	8	JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e3	长度：	10 mm
I/O 线路数量：	32	端子数量：	44
最高工作温度：	70 °C	最低工作温度：	-25 °C
PWM 通道：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP44,.47SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
电源：	3/3.3 V	认证状态：	Not Qualified
RAM（字节）：	2048	ROM（单词）：	64512
ROM可编程性：	OTPROM	座面最大高度：	1.6 mm
速度：	10 MHz	子类别：	Microcontrollers
最大压摆率：	4.8 mA	最大供电电压：	3.6 V
最小供电电压：	2.7 V	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	TIN
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	10 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER	Base Number Matches：	1

型号	制造商	描述	价格	文档
P87CL881H/XXX	ETC	8-Bit Microcontroller	获取价格
P87CL881HDH/000	NXP	IC 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP44, Microcontroller	获取价格
P87CL881HDH/XXX	NXP	IC 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP44, Microcontroller	获取价格
P87CL881HDH/XXX-T	NXP	IC 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP44, Microcontroller	获取价格
P87CL883DDT	NXP	8-BIT, OTPROM, 3.58MHz, MICROCONTROLLER, PDSO28	获取价格
P87CL883DDT	PHILIPS	Microcontroller, 8-Bit, UVPROM, 8051 CPU, 3.58MHz, CMOS, PDSO28,	获取价格
P87CL883DDT-T	NXP	暂无描述	获取价格
P87CL883T	NXP	TELX microcontrollers for CT0 handset/basestation applications	获取价格
P87CL883T/000	NXP	TELX microcontrollers for CT0 handset/basestation applications	获取价格
P87CL883T/XXX	NXP	MICROCONTROLLER\|8-BIT\|8051 CPU\|CMOS\|SOP\|28PIN\|PLASTIC	获取价格

P87CL881H/000

P87CL881H/000 概述

P87CL881H/000 规格参数

P87CL881H/000 数据手册

P87CL881H/000 相关器件

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