P87C750EBAA_技术文档

INTEGRATED CIRCUITS

83C750/87C750

80C51 8-bit microcontroller family

1K/64 OTP ROM, low pin count

Product specification

1998 May 01

Supersedes data of 1998 Jan 19

IC20 Data Handbook

Philips

Semiconductors

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

83C750/87C750

DESCRIPTION

PIN CONFIGURATIONS

The Philips 8XC750 offers the advantages of the 80C51 architecture

in a small package and at low cost.

24

23

22

V

CC

P3.4/A4

P3.3/A3

1

2

3

The 8XC750 Microcontroller is fabricated with Philips high-density

CMOS technology. Philips epitaxial substrate minimizes CMOS

latch-up sensitivity.

P3.5/A5

P3.6/A6

P3.2/A2/A10

21 P3.7/A7

4

5

P3.1/A1/A9

P3.0/A0/A8

PLASTIC

DUAL

IN-LINE

AND

SHRINK

SMALL

The 87C750 contains a 1k × 8 EPROM, a 64 × 8 RAM, 19 I/O lines,

a 16-bit auto-reload counter/timer, a five-source, fixed-priority level

interrupt structure and an on-chip oscillator.

20 P1.7/T0/D7

19 P1.6/INT1/D6

6

7

P0.2/V

PP

18

17

16

15

P0.1/OE–PGM

P1.5/INT0/D5

P1.4/D4

OUTLINE

PACKAGE

FEATURES

• 80C51 based architecture

8

P0.0/ASEL

RST

9

P1.3/D3

• Oscillator frequency range—up to 16MHz

P1.2/D2

10

11

12

X2

• Small package sizes

– 24-pin DIP (300 mil “skinny DIP”)

– 24-pin Shrink Small Outline Package

– 28-pin PLCC

14 P1.1/D1

13

X1

V

P1.0/D0

SS

4

1

26

• 87C750 available in one-time programmable plastic packages

5

25

PLASTIC

LEADED

CHIP

• Low power consumption:

– Normal operation: less than 11mA @ 5V, 12MHz

– Idle mode

CARRIER

11

19

– Power-down mode

12

18

• 1k × 8 EPROM (87C750)

• 64 × 8 RAM

1

2

3

4

5

6

7

8

Function

P3.4/A4

P3.3/A3

P3.2/A2/A10

P3.1/A1/A9

NC*

P3.0/A0/A8

P0.2/V

PP

P0.1/OE-PGM

P0.0/ASEL

NC*

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Function

P1.0/D0

P1.1/D1

P1.2/D2

P1.3/D3

P1.4/D4

P1.5/INT0/D5

NC*

• 16-bit auto reloadable counter/timer

• Boolean processor

• CMOS and TTL compatible

NC*

9

P1.6/INT1/D6

P1.7/T0/D7

P3.7/A7

P3.6/A6

P3.5/A5

• Well suited for logic replacement, consumer and industrial

10

11

12

13

14

RST

X2

X1

applications

• LED drive outputs

V

CC

SS

SU00295A

* NO INTERNAL CONNECTION

ORDERING INFORMATION

DRAWING

1

ROM

EPROM

TEMPERATURE RANGE °C AND PACKAGE

FREQUENCY

NUMBER

SOT222-1

SOT261-3

SOT340-1

P83C750EBP N

P83C750EFP N

P83C750EBA A

P83C750EFA A

P83C750EBD DB

P87C750EBP N

P87C750EFP N

P87C750EBA A

P87C750EFA A

P87C750EBD DB

OTP

0 to +70, Plastic Dual In-line Package

–40 to +85, Plastic Dual In-line Package

0 to +70, Plastic Lead Chip Carrier

–40 to +85, Plastic Lead Chip Carrier

0 to +70, Shrink Small Outline Package

3.5 to 16MHz

NOTE:

1. OTP = One Time Programmable EPROM.

2

1998 May 01

853–1683 19331

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

83C750/87C750

BLOCK DIAGRAM

P0.0–P0.2

PORT 0

DRIVERS

V

CC

V

SS

RAM ADDR

REGISTER

PORT 0

LATCH

RAM

EPROM

STACK

POINTER

B

ACC

REGISTER

PROGRAM

ADDRESS

REGISTER

TMP1

TMP2

BUFFER

PCON

TCON

ALU

IE

TH0

RTH

TL0

RTL

PC

INCRE-

MENTER

PSW

INTERRUPT AND

TIMER BLOCKS

PROGRAM

COUNTER

TIMING

RST

AND

DPTR

CONTROL

PORT 1

LATCH

PORT 3

LATCH

PD

OSCILLATOR

PORT 1

DRIVERS

PORT 3

DRIVERS

X1

X2

P1.0–P1.7

P3.0–P3.7

SU00312

3

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

83C750/87C750

PIN DESCRIPTIONS

PIN NO.

MNEMONIC

DIP/

SSOP

LCC

TYPE

NAME AND FUNCTION

V

12

24

14

28

I

Circuit Ground Potential

Supply voltage during normal, idle, and power-down operation.

SS

CC

P0.0-P0.2

8-6

9-7

I/O

Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,

and in that state can be used as high-impedance inputs. These pins are driven low if the port register

bit is written with a 0. The state of the pin can always be read from the port register by the program.

P0.0, P0.1, and P0.2 are open drain bidirectional I/O pins with the electrical characteristics listed in

the tables that follow. While these differ from “standard TTL” characteristics, they are close enough

for the pins to still be used as general-purpose I/O. Port 0 also provides alternate functions for

programming the EPROM memory as follows:

6

7

8

N/A

I

V

(P0.2) – Programming voltage input. (See Note 1.)

PP

OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.

OE/PGM = 1 output enabled (verify mode).

OE/PGM = 0 program mode.

8

9

I

ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.

ASEL = 0 low address byte available on port 3.

ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).

P1.0-P1.7

13-20 15-20,

23, 24

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written

to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins

that are externally pulled low will source current because of the internal pull-ups. (See DC

Electrical Characteristics: I ). Port 1 serves to output the addressed EPROM contents in the verify

IL

mode and accepts as inputs the value to program into the selected address during the program

mode. Port 1 also serves the special function features of the 80C51 family as listed below:

18

19

20

23

24

I

INT0 (P1.5): External interrupt.

INT1 (P1.6): External interrupt.

T0 (P1.7): Timer 0 external input.

P3.0-P3.7

5-1,

23-21

6, 4-1,

27-25

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written

to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins

that are externally being pulled low will source current because of the pull-ups. (See DC Electrical

Characteristics: I ). Port 3 also functions as the address input for the EPROM memory location to

IL

be programmed (or verified). The 10-bit address is multiplexed into this port as specified by

P0.0/ASEL.

RST

9

11

I

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.

An internal diffused resistor to V permits a power-on RESET using only an external capacitor to

SS

V

CC

. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places

the device in the programming state allowing programming address, data and V to be applied for

PP

programming or verification purposes. The RESET serial sequence must be synchronized with the

X1 input.

X1

11

10

13

12

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the

programming state.

X2

O

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

1. When P0.2 is at or close to 0 Volt, it may affect the internal ROM operation. We recommend that P0.2 be tied to V via a small pull-up (e.g.,

CC

2kΩ).

enough to allow the oscillator time to start up (normally a few

OSCILLATOR CHARACTERISTICS

X1 and X2 are the input and output, respectively, of an inverting

amplifier which can be configured for use as an on-chip oscillator.

milliseconds) plus two machine cycles. At power-up, the voltage on

and RST must come up at the same time for a proper start-up.

V

CC

To drive the device from an external clock source, X1 should be

driven while X2 is left unconnected. There are no requirements on

the duty cycle of the external clock signal, because the input to the

internal clock circuitry is through a divide-by-two flip-flop. However,

minimum and maximum high and low times specified in the data

sheet must be observed.

IDLE MODE

In idle mode, the CPU puts itself to sleep while all of the on-chip

peripherals stay active. The instruction to invoke the idle mode is the

last instruction executed in the normal operating mode before the

idle mode is activated. The CPU contents, the on-chip RAM, and all

of the special function registers remain intact during this mode. The

idle mode can be terminated either by any enabled interrupt (at

which time the process is picked up at the interrupt service routine

and continued), or by a hardware reset which starts the processor in

the same manner as a power-on reset.

RESET

A reset is accomplished by holding the RST pin high for at least two

machine cycles (24 oscillator periods), while the oscillator is running.

To insure a good power-up reset, the RST pin must be high long

4

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

83C750/87C750

TCON is set on counter overflow and, if the interrupt is enabled, will

generate an interrupt.

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the

instruction to invoke power-down is the last instruction executed.

Only the contents of the on-chip RAM are preserved. A hardware

reset is the only way to terminate the power-down mode. the control

bits for the reduced power modes are in the special function register

PCON.

TCON Register

MSB

LSB

IT1

GATE

C/T

TF

TR

IE0

IT0

IE1

GATE

1

– Timer/counter is enabled only when INT0 pin is high,

and TR is 1.

Table 1.

External Pin Status During Idle and

Power-Down Modes

0

1

0

1

0

– Timer/counter is enabled when TR is 1.

– Counter/timer operation from T0 pin.

– Timer operation from internal clock.

– Set on overflow of TH.

– Cleared when processor vectors to interrupt routine

and by reset.

C/T

TF

MODE

Port 0

Port 1

Port 2

Idle

Power-down

Data

TR

1

0

1

0

1

0

– Timer/counter enabled.

– Timer/counter disabled.

– Edge detected in INT0.

– INT0 is edge triggered.

– INT0 is level sensitive.

– Edge detected on INT1.

– INT1 is edge triggered.

– INT1 is level sensitive.

DIFFERENCES BETWEEN THE 8XC750 AND THE

80C51

IE0

IT0

Program Memory

IE1

IT1

On the 8XC750, program memory is 1024 bytes long and is not

externally expandable, so the 80C51 instructions MOVX, LJMP, and

LCALL are not implemented. The only fixed locations in program

memory are the addresses at which execution is taken up in

response to reset and interrupts, which are as follows:

Program Memory

These flags are functionally identical to the corresponding 80C51

flags, except that there is only one timer on the 83C750 and the

flags are therefore combined into one register.

Event

Reset

External INT0

Counter/timer 0

External INT1

Address

000

003

00B

013

Note that the positions of the IE0/IT0 and IE1/IT1 bits are

transposed from the positions used in the standard 80C51 TCON

register.

Interrupt Subsystem – Fixed Priority

The IP register and the 2-level interrupt system of the 80C51 are

eliminated. Simultaneous interrupt conditions are resolved by a

single-level, fixed priority as follows:

Counter/Timer Subsystem

Timer/Counter

Highest priority:

Pin INT0

The 8XC750 has one timers: a 16-bit timer/counter. The 16-bit

timer/counter’s operation is similar to mode 2 operation on the

80C51, but is extended to 16 bits. The timer/counter is clocked by

either 1/12 the oscillator frequency or by transitions on the T0 pin.

The C/T pin in special function register TCON selects between

these two modes. When the TCON TR bit is set, the timer/counter is

enabled. Register pair TH and TL are incremented by the clock

source. When the register pair overflows, the register pair is

reloaded with the values in registers RTH and RTL. The value in the

reload registers is left unchanged. See the 83C750 counter/timer

block diagram in Figure 1. The TF bit in special function register

Counter/timer flag 0

Pin INT1

Special Function Register Addresses

Special function registers for the 8XC750 are identical to those of

the 80C51, except for the changes listed below:

80C51 special function registers not present in the 8XC750 are

TMOD (89), P2 (A0) and IP (B8). The 80C51 registers TH1 and TL1

are replaced with the 87C750 registers RTH and RTL respectively

(refer to Table 2).

OSC

÷ 12

C/T = 0

C/T = 1

TL

TH

TF

Int.

T0 Pin

TR

Reload

Gate

RTL

RTH

INT0 Pin

SU00300

Figure 1. 83C751 Counter/Timer Block Diagram

5

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

83C750/87C750

Table 2.

87C750 Special Function Registers

DIRECT

DESCRIPTION

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

ADDRESS MSB

RESET

VALUE

SYMBOL

LSB

E0

ACC*

B*

Accumulator

B register

E0H

F0H

E7

F7

E6

F6

E5

F5

E4

F4

E3

F3

E2

F2

E1

F1

00H

F0

00H

DPTR:

Data pointer

(2 bytes)

DPH

DPL

High byte

Low byte

83H

82H

00H

AF

EA

AE

–

AD

–

AC

–

AB

–

AA

A9

A8

IE*#

Interrupt enable

Port 0

A8H

80H

EX1

ET0

EX0

00H

82

–

81

–

80

–

P0*#

–

xxxxx111B

97

T0

B7

96

INT1

B6

95

INT0

B5

94

–

93

–

92

–

91

–

90

–

P1*

P3*

Port 1

Port 3

90H

B0H

FFH

B4

B3

B2

B1

B0

PCON#

Power control

87H

–

PD

IDL

xxxxxx00B

D7

CY

D6

AC

D5

F0

D4

D3

D2

D1

–

D0

P

PSW*

SP

Program status word

Stack pointer

D0H

81H

88H

RS1

RS0

OV

00H

07H

00H

8F

8E

8D

TF

8C

TR

8B

8A

89

88

TCON*#

Timer/counter control

GATE

C/T

IE0

IT0

IE1

IT1

TL#

Timer low byte

Timer high byte

Timer low reload

Timer high reload

8AH

8CH

8BH

8DH

00H

TH#

RTL#

RTH#

*

SFRs are bit addressable.

#

SFRs are modified from or added to the 80C51 SFRs.

1, 2

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

UNIT

°C

V

Storage temperature range

–65 to +150

–0.5 to +6.5

Voltage from V to V

CC

SS

Voltage from any pin to V (except V

)

–0.5 to V + 0.5

V

SS

PP

CC

Power dissipation

1.0

0 to +13.0

10

W

Voltage on V pin to V

V

PP

SS

Maximum I per I/O pin

mA

OL

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

6

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

83C750/87C750

DC ELECTRICAL CHARACTERISTICS

1

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V

CC SS

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

0.2V –0.1

UNIT

V

Input low voltage

–0.5

V

IL

DD

Input high voltage, except X1, RST

Input high voltage, X1, RST

0.2V +0.9

V

+0.5

IH

CC

0.7V

IH1

CC

2

V

Output low voltage, ports 1 and 3

Output low voltage, port 0

I

= 1.6mA

= 3.2mA

0.45

V

OL

2

OL1

OL

V

OH

Output high voltage, ports 1 and 3

I

= –60µA

= –25µA

= –10µA

2.4

V

OH

I

0.75V

CC

0.9V

CC

C

Capacitance

10

pF

I

Logical 0 input current, ports 1 and 3

V

= 0.45V

–50

µA

IL

IN

3

Logical 1 to 0 transition current, ports 1 and 3

V

= 2V (0 to +70°C)

= 2V (–40 to +85°C)

–650

–750

µA

TL

IN

V

IN

I

Input leakage current, port 0

Internal pull-down resistor

0.45 < V < V

CC

±10

µA

LI

IN

R

C

25

175

kΩ

RST

IO

Test freq = 1MHz,

= 25°C

Pin capacitance

10

50

pF

T

amb

4

I

Power-down current

V

= 2 to V max

µA

PD

CC

V

CC

= 0V

= 5V±10%

SS

V

program voltage

V

amb

12.5

13.0

50

V

PP

T

= 21°C to 27°C

I

Program current

V

= 13.0V

mA

PP

5, 6

Supply current (see Figure 3)

CC

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise

SS

noted.

2. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

10mA

26mA

67mA

(NOTE: This is 85°C spec.)

OL

Maximum I per 8-bit port:

OL

Maximum total I for all outputs:

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

OL

test conditions.

3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V is approximately 2V.

IN

4. Power-down I is measured with all output pins disconnected; port 0 = V ; X2, X1 n.c.; RST = V .

CC

SS

5. Active I is measured with all output pins disconnected; X1 driven with t

, t

= 5ns, V = V + 0.5V, V = V – 0.5V; X2 n.c.;

CC

CLCH CHCL IL SS IH CC

RST = port 0 = V . I will be slightly higher if a crystal oscillator is used.

CC CC

6. Idle I is measured with all output pins disconnected; X1 driven with t

, t

= 5ns, V = V + 0.5V, V = V – 0.5V; X2 n.c.;

CC

CLCH CHCL

IL

SS

IH

CC

port 0 = V ; RST = V

.

SS

CC

AC ELECTRICAL CHARACTERISTICS

1, 2

T

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V

amb

CC SS

VARIABLE CLOCK

SYMBOL

1/t

PARAMETER

MIN

MAX

MIN

MAX

UNIT

Oscillator frequency:

External Clock (Figure 2)

3.5

16

3.5

40

MHz

CLCL

t

High time

Low time

Rise time

Fall time

20

10

ns

CHCX

CLCX

CLCH

CHCL

20

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise

SS

noted.

2. Load capacitance for ports = 80pF.

7

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

83C750/87C750

EXPLANATION OF THE AC SYMBOLS

In defining the clock waveform, care must be taken not to exceed

the MIN or MAX limits of the AC electrical characteristics table.

Each timing symbol has five characters. The first character is always

‘t’ (= time). The other characters, depending on their positions,

indicate the name of a signal or the logical status of that signal. The

designations are:

H – Logic level high

L – Logic level low

Q – Output data

T – Time

V – Valid

X – No longer a valid logic level

Z – Float

C – Clock

D – Input data

t

V

–0.5

CLCX

CC

0.2 V + 0.9

CC

0.2 V – 0.1

CC

t

0.45V

CHCX

t

CLCH

CHCL

t

CLCL

SU00297

Figure 2. External Clock Drive

60

5

22

20

18

16

14

12

10

8

MAX ACTIVE I

CC

50

40

30

5

TYP ACTIVE I

CC

5

TYP ACTIVE I

CC

6

20

10

0

6

MAX IDLE I

TYP IDLE I

CC

MAX IDLE I

TYP IDLE I

CC

4

2

6

CC

4

8

12

16

20

24

28

32

36

40

Frequency (MHz)

SU00313

Figure 3.

I

vs. Frequency

CC

Maximum I values taken at V max and worst case temperature.

CC

Typical I values taken at V = 5.0V and 25°C.

CC

Notes 5 and 6 refer to DC Electrical Characteristics.

ROM CODE SUBMISSION

When submitting ROM code for the 80C750, the following must be specified:

1. 1k byte user ROM data

ADDRESS

CONTENT

BIT(S)

COMMENT

User ROM Data

0000H to 03FFH

DATA

7:0

8

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

83C750/87C750

repeated until a total of 25 programming pulses have occurred. At

the conclusion of the last pulse, the PGM/ signal should remain high.

87C750 PROGRAMMING CONSIDERATIONS

EPROM Characteristics

The V signal may now be driven to the V level, placing the

PP

OH

The 87C750 is programmed by using a modified Quick-Pulse

Programming algorithm similar to that used for devices such as the

87C451 and 87C51. It differs from these devices in that a serial data

stream is used to place the 87C750 in the programming mode.

87C750 in the verify mode. (Port 1 is now used as an output port).

After four machine cycles (48 clock periods), the contents of the

addressed location in the EPROM array will appear on Port 1.

The next programming cycle may now be initiated by placing the

address information at the inputs of the multiplexed buffers, driving

Figure 4 shows a block diagram of the programming configuration

for the 87C750. Port pin P0.2 is used as the programming voltage

the V pin to the V voltage level, providing the byte to be

PP

supply input (V signal). Port pin P0.1 is used as the program

PP

programmed to Port1 and issuing the 26 programming pulses on the

PGM/ pin, bringing V back down to the V level and verifying the

(PGM/) signal. This pin is used for the 25 programming pulses.

PP

C

byte.

Port 3 is used as the address input for the byte to be programmed

and accepts both the high and low components of the eleven bit

address. Multiplexing of these address components is performed

using the ASEL input. The user should drive the ASEL input high

and then drive port 3 with the high order bits of the address. ASEL

should remain high for at least 13 clock cycles. ASEL may then be

driven low which latches the high order bits of the address internally.

the high address should remain on port 3 for at least two clock

cycles after ASEL is driven low. Port 3 may then be driven with the

low byte of the address. The low address will be internally stable 13

clock cycles later. The address will remain stable provided that the

low byte placed on port 3 is held stable and ASEL is kept low. Note:

ASEL needs to be pulsed high only to change the high byte of the

address.

Programming Modes

The 87C750 has four programming features incorporated within its

EPROM array. These include the USER EPROM for storage of the

application’s code, a 16-byte encryption key array and two security

bits. Programming and verification of these four elements are

selected by a combination of the serial data stream applied to the

RESET pin and the voltage levels applied to port pins P0.1 and

P0.2. The various combinations are shown in Table 3.

Encryption Key Table

The 87C750 includes a 16-byte EPROM array that is programmable

by the end user. The contents of this array can then be used to

encrypt the program memory contents during a program memory

verify operation. When a program memory verify operation is

performed, the contents of the program memory location is

XNOR’ed with one of the bytes in the 16-byte encryption table. The

resulting data pattern is then provided to port 1 as the verify data.

The encryption mechanism can be disable, in essence, by leaving

the bytes in the encryption table in their erased state (FFH) since

the XNOR product of a bit with a logical one will result in the original

bit. The encryption bytes are mapped with the code memory in

16-byte groups. the first byte in code memory will be encrypted with

the first byte in the encryption table; the second byte in code

memory will be encrypted with the second byte in the encryption

table and so forth up to and including the 16the byte. The encryption

repeats in 16-byte groups; the 17th byte in the code memory will be

encrypted with the first byte in the encryption table, and so forth.

Port 1 is used as a bidirectional data bus during programming and

verify operations. During programming mode, it accepts the byte to

be programmed. During verify mode, it provides the contents of the

EPROM location specified by the address which has been supplied

to Port 3.

The XTAL1 pin is the oscillator input and receives the master system

clock. This clock should be between 1.2 and 6MHz.

The RESET pin is used to accept the serial data stream that places

the 87C750 into various programming modes. This pattern consists

of a 10-bit code with the LSB sent first. Each bit is synchronized to

the clock input, X1.

Programming Operation

Figures 5 and 6 show the timing diagrams for the program/verify

cycle. RESET should initially be held high for at least two machine

Security Bits

cycles. P0.1 (PGM/) and P0.2 (V ) will be at V as a result of the

PP

OH

Two security bits, security bit 1 and security bit 2, are provided to

limit access to the USER EPROM and encryption key arrays.

Security bit 1 is the program inhibit bit, and once programmed

performs the following functions:

RESET operation. At this point, these pins function as normal

quasi-bidirectional I/O ports and the programming equipment may

pull these lines low. However, prior to sending the 10-bit code on the

RESET pin, the programming equipment should drive these pins

1. Additional programming of the USER EPROM is inhibited.

high (V ). The RESET pin may now be used as the serial data input

IH

2. Additional programming of the encryption key is inhibited.

3. Verification of the encryption key is inhibited.

for the data stream which places the 87C750 in the programming

mode. Data bits are sampled during the clock high time and thus

should only change during the time that the clock is low. Following

transmission of the last data bit, the RESET pin should be held low.

4. Verification of the USER EPROM and the security bit levels may

still be performed.

Next the address information for the location to be programmed is

placed on port 3 and ASEL is used to perform the address

multiplexing, as previously described. At this time, port 1 functions

as an output.

(If the encryption key array is being used, this security bit should be

programmed by the user to prevent unauthorized parties from

reprogramming the encryption key to all logical zero bits. Such

programming would provide data during a verify cycle that is the

logical complement of the USER EPROM contents).

A high voltage V level is then applied to the V input (P0.2).

PP

(This sets Port 1 as an input port). The data to be programmed into

the EPROM array is then placed on Port 1. This is followed by a

series of programming pulses applied to the PGM/ pin (P0.1). These

pulses are created by driving P0.1 low and then high. This pulse is

Security bit 2, the verify inhibit bit, prevents verification of both the

USER EPROM array and the encryption key arrays. The security bit

levels may still be verified.

9

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

83C750/87C750

Verification occurs in a similar manner using the RESET serial

stream shown in Table 3. Port 3 is not required to be driven and the

results of the verify operation will appear on ports 1.6 and 1.7.

Programming and Verifying Security Bits

Security bits are programmed employing the same techniques used

to program the USER EPROM and KEY arrays using serial data

streams and logic levels on port pins indicated in Table 3. When

programming either security bit, it is not necessary to provide

address or data information to the 87C750 on ports 1 and 3.

Ports 1.7 contains the security bit 1 data and is a logical one if

programmed and a logical zero if not programmed. Likewise, P1.6

contains the security bit 2 data and is a logical one if programmed

and a logical zero if not programmed.

Table 3. Implementing Program/Verify Modes

OPERATION

SERIAL CODE

P0.1 (PGM/)

P0.2 (V

)

PP

1

Program user EPROM

296H

292H

29AH

298H

29AH

–

V

PP

Verify user EPROM

Program key EPROM

Verify key EPROM

Program security bit 1

Program security bit 2

Verify security bits

V

IH

1

–

V

PP

V

IH

1

IH

PP

–

V

1

V

IH

NOTE:

1. Pulsed from V to V and returned to V .

IH

IL

EPROM PROGRAMMING AND VERIFICATION

T

amb

= 21°C to +27°C, V = 5V ±10%, V = 0V

CC SS

SYMBOL

PARAMETER

MIN

1.2

MAX

UNIT

1/t

Oscillator/clock frequency

6

MHz

CLCL

1

t

Address setup to P0.1 (PROG–) low

Address hold after P0.1 (PROG–) high

Data setup to P0.1 (PROG–) low

Data hold after P0.1 (PROG–) high

10µs + 24t

AVGL

CLCL

48t

38t

36t

GHAX

DVGL

GHDX

SHGL

GHSL

GLGH

CLCL

V

setup to P0.1 (PROG–) low

hold after P0.1 (PROG–)

10

90

µs

PP

P0.1 (PROG–) width

low (V ) to data valid

110

2

V

PP

48t

CLCL

AVQV

CC

P0.1 (PROG–) high to P0.1 (PROG–) low

P0.0 (sync pulse) low

10

µs

GHGL

SYNL

4t

CLCL

8t

CLCL

P0.0 (sync pulse) high

ASEL high time

SYNH

MASEL

MAHLD

HASET

ADSTA

13t

CLCL

Address hold time

2t

Address setup to ASEL

Low address to valid data

13t

CLCL

48t

CLCL

NOTES:

1. Address should be valid at least 24t

before the rising edge of P0.2 (V ).

PP

CLCL

2. For a pure verify mode, i.e., no program mode in between, t

is 14t

maximum.

AVQV

CLCL

10

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

83C750/87C750

87C750

V

A0–A9

P3.0–P3.7

P0.0/ASEL

+5V

CC

ADDRESS STROBE

SS

PROGRAMMING

PULSES

P0.1

V

/V VOLTAGE

P0.2

PP IH

P1.0–P1.7

DATA BUS

SOURCE

CLK SOURCE

XTAL1

RESET

CONTROL

LOGIC

RESET

SU00314

Figure 4. Programming Configuration

XTAL1

MIN 2 MACHINE

CYCLES

TEN BIT SERIAL CODE

RESET

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

UNDEFINED

P0.2

P0.1

UNDEFINED

SU00302

Figure 5. Entry into Program/Verify Modes

12.75V

P0.2 (V

)

5V

t

PP

t

SHGL

GHSL

25 PULSES

P0.1 (PGM)

P0.0 (ASEL)

t

GLGH

MASEL

t

GHGL

98µs MIN

10µs MIN

t

HASET

t

HAHLD

HIGH ADDRESS

LOW ADDRESS

PORT 3

PORT 1

t

ADSTA

DVGL

GHDX

AVQV

INVALID DATA

VERIFY MODE

INVALID DATA

VERIFY MODE

VALID DATA

DATA TO BE PROGRAMMED

PROGRAM MODE

VALID DATA

SU00310

Figure 6. Program/Verify Cycle

11

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM low pin count

83C750/87C750

DIP24: plastic dual in-line package; 24 leads (300 mil)

SOT222-1

12

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM low pin count

83C750/87C750

PLCC28: plastic leaded chip carrer; 28 leads; pedestal

SOT261-3

13

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM low pin count

83C750/87C750

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm

SOT340-1

14

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM low pin count

83C750/87C750

NOTES

15

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

1K/64 OTP/ROM low pin count

83C750/87C750

Data sheet status

[1]

Data sheet

status

Product

status

Definition

Objective

specification

Development

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

Preliminary

specification

Qualification

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make chages at any time without notice in order to

improve design and supply the best possible product.

Product

specification

Production

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 1998

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Date of release: 05-98

Document order number:

9397 750 03844

Philips

Semiconductors

16

1998 May 01


型号：	P87C750EBAA
厂家：	NXP
描述：	80C51 8-bit microcontroller family 1K/64 OTP ROM, low pin count 80C51的8位单片机系列1K / 64 OTP ROM ，低引脚数 OTP只读存储器
文件：	总16页 (文件大小：162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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