MC34931SEKR2_技术文档

Document Number: MC34931

Rev. 4.0, 8/2016

NXP Semiconductors

Technical Data

5.0 A H-Bridge

34931

The 34931 is a monolithic H-Bridge Power IC in a robust thermally enhanced

package. It is designed for any low voltage DC servo motor control application

within the current and voltage limits stated in this specification. This device is

powered by SMARTMOS technology.

Industrial

H-BRIDGE

The 34931 H-Bridge is able to control inductive loads with currents up to 5.0 A

peak. RMS current capability is subject to the degree of heatsinking provided to

the device package. Internal peak current limiting (regulation) is activated at load

currents above 6.5 A ±1.5 A. Output loads can be pulse-width modulated

(PWMed at frequencies up to 20 kHz. A load current feedback feature provides

a proportional (0.24% of the load current) current output suitable for monitoring

by a microcontroller’s A/D input. A status flag output reports undervoltage,

overcurrent, and overtemperature fault conditions.

EK SUFFIX (PB-FREE)

98ARL10543D

32-PIN SOICW-EP

Two independent inputs provide polarity control of two half-bridge totem-pole

outputs. The disable inputs are provided to force the H-Bridge outputs to tri-state

(high-impedance off-state).

Features

Applications

• DC motor control

• 5.0 V to 36 V continuous operation with 24 V nominal operating voltage

(transient operation from 5.0 V to 40 V)

• DC brushed and servo motor driver

• Copiers, printers

• Factory automation

• POS, ATM, vending kiosks

• Robotics

• 235 mΩ maximum R_DS(on)at T_J= 150 °C (each H-Bridge MOSFET)

• 3.0 V and 5.0 V TTL/CMOS logic compatible inputs

• Overcurrent limiting (regulation) via internal constant-off-time PWM

• Output short-circuit protection (short to VPWR or GND)

• Temperature-dependant current-limit threshold reduction

• All inputs have an internal source/sink to define the default (floating input)

states

• Security camera control

• Ticketing, toll systems

• Sleep mode with current draw < 20 µA

V

PWR

DD

34931

SF

FB

VPWR

CCP

OUT1

IN1

IN2

MOTOR

MCU

OUT2

D1

EN/D2

PGND

AGND

Figure 1. MC34931 simplified application diagram

1

Orderable parts

Table 1. Orderable part variations

Temperature (T )

Part number

MC34931EK

MC34931SEK

PWM frequency

Package

Notes

A

11 kHz

20 kHz

(1)

-40 °C to 85 °C

32 SOICW-EP

Notes

1. To order parts in Tape & Reel, add the R2 suffix to the part number.

34931

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NXP Semiconductors

2

Internal block diagram

VPWR

VDD

LOGIC SUPPLY

VCP

CHARGE

PUMP

HS1

LS1

HS2

LS2

CCP

OUT1

OUT2

TO GATES

HS1

LS1

IN1

IN2

HS2

LS2

PGND

EN/D2

D1

GATE DRIVE

AND

PROTECTION

LOGIC

VSENSE

CURRENT MIRROR

AND

CONSTANT OFF-TIME

SF

FB

ILIM PWM

PWM CURRENT REGULATOR

AGND

PGND

Figure 2. 34931 Simplified internal block diagram

34931

NXP Semiconductors

3

Pin connections

3.1

Pinout diagram

AGND

D1

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

SF

2

IN1

3

FB

N/C

4

N/C

IN2

EN/D2

N/C

5

CCP

N/C

6

7

VPWR

N/C

VPWR

N/C

8

EP

9

10

11

12

13

14

15

16

OUT1

N/C

OUT2

N/C

PGND

32 SOICW-EP

Transparent Top View

Figure 3. 34931 pin connections

A functional description of each pin can be found in the Functional Description section beginning on page 12.

Table 2. 34931 pin definitions

Pin function

Pin number

Pin name

Formal name

Definition

Disable Input 1

(Active High)

When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger input

with ~ 80 μA source so default condition = disabled.

2

D1

Logic Input

Analog

Output

The load current feedback output provides ground referenced 0.24% of the high-side

output current. (Tie to GND through a resistor if not used.)

3

5

FB

Feedback

When EN/D2 is logic HIGH the H-Bridge is operational. When EN/D2 is logic LOW,

the H-Bridge outputs are tri-stated and placed in Sleep mode. (logic input with

~80 μA sink so default condition = Sleep mode.)

EN/D2

Logic Input

Power Input

Enable Input

Positive Power

Supply

These pins must be connected together physically as close as possible and directly

soldered down to a wide, thick, low resistance supply plane on the PCB.

7, 8, 25, 26

10, 11

VPWR

OUT1

Power

Output

H-Bridge Output 1

Power Ground

Source of HS1 and drain of LS1

High-current power ground pins must be connected together physically as close as

possible and directly soldered down to a wide, thick, low resistance ground plane on

the PCB.

Power

Ground

15-18

22, 23

28

PGND

OUT2

CCP

Power

Output

H-Bridge Output 2

Source of HS2 and drain of LS2

External reservoir capacitor connection for the internal charge pump; connected to

VPWR. Allowable values are 30 nF to 100 nF. Note: This capacitor is required for

the proper performance of the device.

Analog

Output

Charge Pump

Capacitor

Logic input control of OUT2;e.g., when IN2 is logic HIGH, OUT2 is set to VPWR, and

when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger Input with ~80 μA

source so default condition = OUT2 HIGH.)

29

IN2

Logic Input

Input 2

34931

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NXP Semiconductors

Table 2. 34931 pin definitions (continued)

Pin function

Pin number

Pin name

Formal name

Definition

Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to VPWR,

and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger Input with ~80 μA

source so default condition = OUT1 HIGH.)

31

IN1

Logic Input

Input 1

Logic Output

-

Open Drain

Open drain active LOW Status Flag output (requires an external pull-up resistor

Status Flag

(Active Low)

32

1

SF

AGND

N/C

to V . Maximum permissible load current < 0.5 mA. Maximum V

0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)

< 0.4 V at

DD

SFLOW

Analog

Ground

The low-current analog signal ground must be connected to PGND via low-

impedance path (<10 mΩ, 0 Hz to 20 kHz).

Analog Signal Ground

No Connect

4, 6, 9, 12-14,

19-21, 24, 27,

30

None

Pin is not used

Exposed TAB is also the main heatsinking path for the device and must be

connected to GND.

EP

Thermal Pad

Exposed Pad

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5

4

Electrical characteristics

4.1

Maximum ratings

Table 3. Maximum ratings

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage

to the device. These parameters are not production tested.

Ratings

Symbol

Value

Unit

Electrical ratings

Power Supply Voltage

•

Normal Operation (Steady-state)

Transient Overvoltage⁽¹⁾

V_PWR(SS)

V_PWR(T)

-0.3 to 36

-0.3 to 40

V

Logic Input Voltage⁽²⁾

SF Output⁽³⁾

V_IN

V _SF

-0.3 to 7.0

5.0

V

A

Continuous Output Current⁽⁴⁾

I_OUT(CONT)

ESD Voltage⁽⁵⁾

•

Human Body Model

Machine Model

Charge Device Model

Corner Pins

±2000

±200

V_ESD1

V_ESD2

V

±750

±500

All Other Pins

Thermal ratings

Storage Temperature

Operating Temperature⁽⁶⁾

T_STG

- 65 to 150

°C

•

Ambient

Junction

T_A

T_J

-40 to 85

-40 to 150

Peak Package Reflow Temperature During Reflow^(7),(8)

Approximate Junction-to-Case Thermal Resistance⁽⁹⁾

Notes

T_PPRT

R_θJC

Note 8

<1.0

°C

°C/W

1. Device survives repetitive transient overvoltage conditions for durations not to exceed 500 ms at duty cycle not to exceed 5.0%. External protection

is required to prevent device damage in case of a reverse power condition.

2. Exceeding the maximum input voltage on IN1, IN2, EN/D2 or D1 may cause a malfunction or permanent damage to the device.

3. Exceeding the pull-up resistor voltage on the open drain SF pin may cause permanent damage to the device.

4. Continuous output current capability is dependent on sufficient package heatsinking to keep junction temperature ≤150°C.

5. ESD testing is performed in accordance with the Human Body Model (C

= 100 pF, R

= 1500 Ω), Machine Model (C

= 200 pF, R

=

ZAP

0 Ω), and the Charge Device Model (CDM), Robotic (C_ZAP= 4.0 pF).

6. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief non-

repetitive excursions of junction temperature above 150°C can be tolerated, provided the duration does not exceed 30 seconds maximum. (Non-

repetitive events are defined as not occurring more than once in 24 hours.)

7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause

malfunction or permanent damage to the device.

8. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and

Moisture Sensitivity Levels (MSL), Go to www.NXP.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all

orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

9. Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual R_θJB(junction-to-PC board) values

varies depending on solder thickness and composition and copper trace thickness and area. Maximum current at maximum die temperature

represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the R_θJAmust be

<5.0 °C/W for maximum current at 70 °C ambient. Module thermal design must be planned accordingly.

34931

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NXP Semiconductors

4.2

Static electrical characteristics

Table 4. Static electrical characteristics

Characteristics noted under conditions 5.0 V ≤ V_PWR≤ 36 V, -40 °C ≤ T_A≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values

noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min.

Typ.

Max.

Unit

Power inputs (VPWR)

Operating Voltage Range⁽¹⁰⁾

•

Steady-state

Transient (t < 500 ms)⁽¹¹⁾

V_PWR(SS)

V_PWR(t)

5.0

–

36

40

V

Sleep State Supply Current⁽¹²⁾

EN/D2 = Logic [0], IN1, IN2, D1 = Logic [1], and I

I_PWR(SLEEP)

μA

•

= 0A

–

15

–

20

18

OUT

Standby Supply Current (Part Enabled)

= 0 A, V = 5.0 V

I_PWR(STANDBY)

mA

•

I

OUT

EN

Undervoltage Lockout Thresholds

•

V

V_UVLO(ACTIVE)

V_{UVLO(INACTIVE)}

V_UVLO(HYS)

4.15

–

150

–

200

–

5.0

350

V

mV

PWR(FALLING)

PWR(RISING)

Hysteresis

Charge pump

Charge Pump Voltage (CP Capacitor = 33 nF), No PWM

•

V

= 5.0 V

= 36 V

V_CP- V_PWR

3.5

–

12

V

PWR

Charge Pump Voltage (CP Capacitor = 33 nF), PWM = 11 kHz for

MC34931EK and 20 kHz for MC34931SEK

V_CP- V_PWR

3.5

–

12

•

V

= 5.0 V

= 36 V

PWR

Control inputs

Operating Input Voltage (IN1, IN2, D1, EN/D2)

V_I

–

5.5

V

Input Voltage (IN1, IN2, D1, EN/D2)

•

Logic Threshold HIGH

Logic Threshold LOW

Hysteresis

V_IH

V_IL

V_HYS

2.0

–

250

–

400

–

1.0

–

V

mV

Logic Input Currents, VPWR = 5.0 V

•

Input EN/D2 (internal pull-downs), V_IH= 5.0 V

Inputs IN1, IN2, D1 (internal pull-ups), VIL = 0 V

I_IN

20

-200

80

-80

200

-20

μA

Notes

10. Device specifications are characterized over the range of 8.0 V ≤ V

≤ 36 V. Continuous operation above 36 V may degrade device reliability.

PWR

Device is operational down to 5.0 V, but below 8.0 V the output resistance may increase by 50 percent.

11. Device survives the transient overvoltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once every 10

seconds.

12.

I

is with Sleep Mode activated and EN/ D2, = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating. Typical value

PWR(SLEEP)

characterized under the following conditions: T_A= 85 °C and V

= 36 V.

PWR

34931

NXP Semiconductors

7

Table 4. Static electrical characteristics (continued)

Characteristics noted under conditions 5.0 V ≤ V_PWR≤ 36 V, -40 °C ≤ T_A≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values

noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min.

Typ.

Max.

Unit

Power outputs OUT1, OUT2

Output-ON Resistance⁽¹⁴⁾, I_LOAD= 3.0 A

•

V_PWR= 8.0 V, T = 25 °C

–

120

–

235

325

J

R_DS(ON)

mΩ

V_PWR= 8.0 V, T = 150 °C

J

V_PWR= 5.0 V, T = 150 °C

J

Output Current Regulation Threshold

•

T_J< T_FB

I_LIM

5.2

–

6.5

4.2

8.0

–

A

T_J≥ T_FB(Foldback Region - see Figure 9 and Figure 11)⁽¹³⁾

High-side Short-circuit Detection Threshold (Short Circuit to Ground)⁽¹³⁾

I_SCH

I_SCL

11

13

11

16

14

A

(13)

Low-side Short-circuit Detection Threshold (Short Circuit to V_PWR

)

9.0

Output Leakage Current⁽¹⁵⁾, Outputs off, V_PWR= 36 V

MC34931EK and MC34931SEK

I_OUTLEAK

–

-140

–

100

–

μA

•

V

= V_PWR

= Ground

OUT

Output MOSFET Body Diode Forward Voltage Drop, I

Overtemperature Shutdown⁽¹³⁾

= 3.0 A

V_F

–

2.0

V

OUT

•

Thermal Limit at T

T_LIM

T_HYS

175

–

12

200

–

°C

J

Hysteresis at T

J

(13)

Current Foldback at T

T_FB

165

10

–

185

15

°C

J

Current Foldback to Thermal Shutdown Separation⁽¹³⁾

T_SEP

High-side current sense feedback

Feedback Current (pin FB sourcing current)⁽¹⁶⁾

•

I

= 0 mA

0.0

0.35

2.86

5.71

11.43

–

270

0.775

3.57

7.14

14.29

50

750

1.56

4.28

8.57

17.15

μA

mA

OUT

= 300 mA

= 500 mA

= 1.5 A

= 3.0 A

= 6.0 A

I_FB

STATUS FLAG⁽¹⁷⁾

Status Flag Leakage Current⁽¹⁸⁾

I_SFLEAK

μA

•

V

= 5.0 V

–

5.0

0.4

SF

Status Flag SET Voltage⁽¹⁹⁾

V_SFLOW

V

•

I

= 300 µA

SF

Notes

13. This parameter is Guaranteed By Design.

14. Output-ON resistance as measured from output to VPWR and from output to GND.

15. Outputs switched OFF via D1.

16. Accuracy is better than 20% from 0.5 A to 6.0 A. Recommended terminating resistor value: R_FB= 270 Ω.

17. Status Flag output is an open drain output requiring a pull-up resistor to logic V

.

DD

18. Status Flag Leakage Current is measured with Status Flag HIGH and not SET.

19. Status Flag Set Voltage measured with Status Flag LOW and SET with I = 300 μA. Maximum allowable sink current from this pin is <500 μA.

SF

Maximum allowable pull-up voltage < 7.0 V.

34931

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NXP Semiconductors

4.3

Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics

Characteristics noted under conditions 5.0 V ≤ V_PWR≤ 36 V, -40 °C ≤ T_A≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values

noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min.

Typ.

Max.

Unit

Timing characteristics

PWM Frequency⁽²⁰⁾

•

MC34931EK

MC34931SEK

f_PWM

–

11

20

kHz

Maximum Switching Frequency During Current Limit Regulation⁽²¹⁾

f_MAX

t_DON

–

20

kHz

Output ON Delay⁽²²⁾

μs

•

V

= 24 V

PWR

–

18

Output OFF Delay⁽²²⁾

= 24 V

t_DOFF

μs

•

V

–

15

12

–

12

32

27

8.0

PWR

I_LIMOutput Constant-OFF Time^(23),(25)

I_LIMBlanking Time^(24),(25)

t_A

t_B

20.5

16.5

–

μs

Disable Delay Time⁽²⁶⁾

t_DDISABLE

Output Rise and Fall Time⁽²⁷⁾

•

MC34931EK

MC34931SEK

t_F, t_R

1.9

0.2

3.9

1.1

8.0

1.5

μs

Short-circuit/Overtemperature Turn-OFF (Latch-OFF) Time^(28),(29)

Power-ON Delay Time⁽²⁹⁾

t_FAULT

t_POD

t_RR

–

8.0

5.0

150

–

μs

ms

1.0

100

7.0

Output MOSFET Body Diode Reverse Recovery Time⁽²⁹⁾

Charge Pump Operating Frequency⁽²⁹⁾

Notes

75

–

ns

f_CP

MHz

20. The maximum PWM frequency should be limited to frequencies < 11 kHz for MC34931EK and < 20 kHz for MC34931SEK in order to allow the

internal high-side driver circuitry time to fully enhance the high-side MOSFETs at a duty cycle range of 15 to 85%.

21. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s inductance,

capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM frequency during current

limit.

22. * Output Delay is the time duration from 1.5 V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction) of the

OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5 V on the input signal to the 80% point of the output response

signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5 V on the input signal to the 20% point of the output response signal. See

Figure 4, page 10.

23. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.

24. The time during which the current regulation threshold is ignored so the short-circuit detection threshold comparators may have time to act.

25. Parameter is Guaranteed By Characterization.

26. * Disable Delay Time measurement is defined in Figure 5, page 10.

27. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with V

= 24 V,

PWR

R

= 3.0 ohm. See Figure 6, page 10.

LOAD

28. Load currents ramping up to the current regulation threshold become limited at the I_LIMvalue (see Figure 7). The short-circuit currents possess a

di/dt which ramps up to the I or I threshold during the I_LIMblanking time, registering as a short-circuit event detection and causing the

SCH

SCL

shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode may cause junction

temperatures to rise. Junction temperatures above ~160 °C causes the output current limit threshold to “fold back”, or decrease, until ~175 °C is

reached, after which the T_LIMthermal latch-OFF occurs. Permissible operation within this fold back region is limited to non-repetitive transient

events of duration not to exceed 30 seconds (see Figure 9).

29. Parameter is Guaranteed By Design.

34931

NXP Semiconductors

9

4.4

Timing diagrams

5.0

1.5 V

t

0

DON

80%

t

DOFF

V_PWR

20%

0

TIME

Figure 4. Output delay time

5.0 V

0 V

1.5 V

t_DDISABLE

90%

0 ς

TIME

Figure 5. Disable delay time

.

t

R

F

V_PWR

90%

10%

0

TIME

Figure 6. Output switching time

Overload Condition

I_SCShort-circuit Detection Threshold

9.0

6.5

t

= I

Blanking Time

LIM

B

t

= Constant-OFF Time (OUT1 and OUT2 Tri-Stated)

A

t

A

B

I

LIM

0.0

5.0

t

ON

TIME

Figure 7. Current limit blanking time and constant-off time

34931

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NXP Semiconductors

Short-circuit Condition

t

FAULT

I_SCShort-circuit Detection Threshold

9.0

6.5

Hard Short Occurs

OUT1, OUT2 Tri-stated,

SF set Low

t

B

I

LIM

0.0

5.0

(~16 μs)

t

TIME

B

Figure 8. Short-circuit detection turn-off time t_FAULT

.

Current Limit Threshold Foldback.

Operation within this region must be

limited to non-repetitive events not to

exceed 30 s per 24 hr.

6.5

4.2

t

SEP

LIM

Thermal Shutdown

t

HYS

t

LIM

FB

Figure 9. Output current limiting foldback region

34931

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11

5

Functional description

5.1

Introduction

Numerous protection and operational features (speed, torque, direction, dynamic breaking, PWM control, and closed-loop control) make

the 34931 a very attractive, cost-effective solution for controlling a broad range of small DC motors. The 34931 outputs are capable of

supporting peak DC load currents of up to 5.0 A from a 36 V V_PWRsource. An internal charge pump and gate drive circuitry which can

support external PWM frequencies up to 11 kHz in MC34931EK and 20 kHz in MC34931SEK.

The 34931 has an analog feedback (current mirror) output pin (the FB pin) which provides a constant-current source ratioed to the active

high-side MOSFETs’ current. This can be used to provide monitoring of output current to facilitate closed-loop operation for motor speed/

torque control, or for the detection of open load conditions.

Two independent inputs, IN1 and IN2, provide control of the two totem-pole half-bridge outputs. Two independent disable inputs, D1 and

EN/D2, provide the means to force the H-Bridge outputs to a high-impedance state (all H-Bridge switches OFF). The EN/D2 pin also

controls an enable function allowing the IC to be placed in a power-conserving Sleep mode.

The 34931 has output current limiting (via constant OFF-time PWM current regulation), output short-circuit detection with latch-OFF, and

overtemperature detection with latch-OFF. Once the device is latched-OFF due to a fault condition, either of the Disable inputs (D1 or EN/

D2), or V_PWRmust be toggled to clear the status flag.

Current limiting (Load Current Regulation) is accomplished by a constant-OFF time PWM method using current limit threshold triggering.

The current limiting scheme is unique in that it incorporates a junction temperature-dependent current limit threshold. This means the

current limit threshold is reduced to around 4.2 A as the junction temperature increases above 160 °C. When the temperature is above

175 °C, overtemperature shutdown (latch-OFF) occurs. This combination of features allows the device to continue operating for short

periods of time (<30 seconds) with unexpected loads, while still retaining adequate protection for both the device and the load.

5.2

Functional pin description

5.2.1 Power ground and analog ground (PGND and AGND)

The power and analog ground pins should be connected together with a very low-impedance connection.

5.2.2 Positive power supply (VPWR)

VPWR pins are the power supply inputs to the device. All VPWR pins must be connected together on the printed circuit board with as

short as possible traces, offering as low an impedance as possible between pins.

5.2.3 Status flag (SF)

This pin is the device fault status output. This output is an active LOW open drain structure requiring a pull-up resistor to V_DD. The

maximum V_DDis <7.0 V. Refer to Table 6 for the SF Output status definition.

5.2.4 Input 1,2 and disable input 1 (IN1, IN2, and D1)

These pins are input control pins used to control the outputs. These pins are 3.0 V/5.0 V CMOS-compatible inputs with hysteresis. IN1

and IN2 independently control OUT1 and OUT2, respectively. D1 input is used to tri-state disable the H-Bridge outputs.

When D1 is SET (D1 = logic HIGH) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the device

circuitry is fully operational and the supply I_PWR(STANDBY)current is reduced to a few mA. Refer to Table 4, page 7.

5.2.5 H-Bridge output (OUT1, OUT2)

These pins are the outputs of the H-Bridge with integrated free-wheeling diodes. The bridge output is controlled using the IN1, IN2, D1,

and EN/D2 inputs. The outputs have PWM current limiting above the I_LIMthreshold. The outputs also have thermal shutdown (tri-state

latch-OFF) with hysteresis as well as short-circuit latch-OFF protection.

A disable timer (time t_B) is incorporated to distinguish between load currents which are higher than the I_LIMthreshold and short-circuit

currents. This timer is activated at each output transition.

34931

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NXP Semiconductors

5.2.6 Charge pump capacitor (CCP)

This pin is the charge pump output pin and connection for the external charge pump reservoir capacitor. The allowable value is from 30 nF

to 100 nF. This capacitor must be connected from the CCP pin to the VPWR pin. The device cannot operate properly without the external

reservoir capacitor.

5.2.7 Enable input/disable input 2 (EN/D2)

The EN/D2 pin performs the same function as D1 pin, when it goes to a logic LOW the outputs are immediately tri-stated. It is also used

to place the device in a Sleep mode so as to consume very low currents. When the EN/D2 pin voltage is a logic LOW state, the device is

in the Sleep mode. The device is enabled and fully operational when the EN pin voltage is logic HIGH. An internal pull-down resistor

maintains the device in Sleep mode in the event EN is driven through a high-impedance I/O or an unpowered microcontroller, or the EN/

D2 input becomes disconnected.

5.2.8 Feedback (FB)

The 34931 has a feedback output (FB) for monitoring of H-Bridge high-side output currents to facilitate closed-loop operation for motor

speed and torque control.

The FB pin provides current sensing feedback of the H-Bridge high-side drivers. When running in the forward or reverse direction, a

ground-referenced 0.24% of load current is output to this pin. Through the use of an external resistor to ground, the proportional feedback

current can be converted to a proportional voltage equivalent and the controlling microcontroller can measure the current proportional

voltage with its analog-to-digital converter (ADC). This is intended to provide the user with only first-order motor current feedback for motor

torque control. The resistance range for the linear operation of the FB pin is 100 Ω < R_FB<300 Ω.

If PWM-ing is implemented using the disable pin input (only D1), a small filter capacitor (~1.0 µF) may be required in parallel with the R_FB

resistor to ground for spike suppression.

5.3

Functional internal block description

VOLTAGE

CURRENT SENSE

34931

REGULATION

CHARGE

PUMP

TEMPERATURE

SENSE

H-BRIDGE

ANALOG CONTROL AND PROTECTION

OUTPUT DRIVERS

OUT1 - OUT2

INPUT LOGIC CONTROL

MCU

INTERFACE

FAULT LOGIC

PROTECTION LOGIC CONTROL

GATE CONTROL LOGIC

Figure 10. Functional internal block diagram

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13

5.3.1 Analog control and protection circuitry

An on-chip voltage regulator supplies the internal logic. The charge pump provides gate drive for the H-Bridge MOSFETs. The current

and temperature sense circuitry provides detection and protection for the output drivers. Output undervoltage protection shuts down the

MOSFETS.

5.3.2 Gate control logic

The 34931 is a monolithic H-Bridge Power IC designed primarily for any low-voltage DC servo motor control application within the current

and voltage limits stated for the device. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. Two

independent disable inputs are provided to force the H-Bridge outputs to tri-state (high-impedance off-state).

5.3.3 H-Bridge output drivers: OUT1 and OUT2

The H-Bridge is the power output stage. The current flow from OUT1 to OUT2 is reversible and under full control of the user by way of the

Input Control Logic. The output stage is designed to produce full load control under all system conditions. All protective and control

features are integrated into the control and protection blocks. The sensors for current and temperature are integrated directly into the

output MOSFET for maximum accuracy and dependability.

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6

Functional device operation

6.1

Operational modes

9.0

6.5

Typical Short-circuit Detection Threshold

Typical Current Limit Threshold

High Current Load Being Regulated via Constant-OFF-Time PWM

Moderate Current Load

PWM

Current

Limiting

Hard Short Detection and Latch-OFF

0

IN1 or IN2

IN2 or IN1

IN1 or IN2

IN2 or IN1

[1]

IN1 IN2

[0]

[1]

[0]

[1]

[0]

[1]

[0]

Outputs

Tri-stated

Outputs

Tri-stated

Outputs Operation

(per Input Control Condition)

Time

Figure 11. Operating states

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6.2

Logic commands

Table 6. Truth table

The tri-state conditions and the status flag are reset using D1 or EN/D2. The truth table uses the following notations: L = LOW, H = HIGH,

X = HIGH or LOW, and Z = High-impedance. All output power transistors are switched off.

Input conditions

D1 IN1

Status

Outputs

Device state

EN/D2

IN2

SF

OUT1

OUT2

Forward

Reverse

H

L

H

L

H

L

H

L

H

L

H

L

Freewheeling Low

Freewheeling High

Disable 1 (D1)

L

H

X

Z

X

H

X

Z

X

H

Z

H

X

Z

H

Z

X

H

Z

H

L

IN1 Disconnected

IN2 Disconnected

D1 Disconnected

Undervoltage Lockout⁽³⁰⁾

Overtemperature⁽³¹⁾

Short-circuit⁽³¹⁾

H

L

Z

X

L

Sleep Mode EN/D2

EN/D2 Disconnected

Notes

H

Z

30. In the event of an undervoltage condition, the outputs tri-state and status flag is SET logic LOW. Upon undervoltage recovery, status flag is reset

automatically or automatically cleared and the outputs are restored to their original operating condition.

31. When a short-circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input signals and

the status flag is latched to logic LOW. To reset from this condition requires the toggling of either D1, EN/D2, or V

.

PWR

Reverse

Forward

Low-Side Recirculation

High-Side Recirculation

(Forward)

V

(Forward)

V

PWR

V

PWR

V

PWR

V

PWR

Load

Current

Load

Current

Load

Current

ON

OUT1

OFF

OUT2

OFF

OUT1

ON

OUT2

OFF

OUT1

OFF

OUT2

ON

OUT1

ON

OUT2

LOAD

OFF

ON

OFF

Load

Current

ON

OFF

PGND

Figure 12. 34931 power stage operation

6.3

Protection and diagnostic features

6.3.1 Short-circuit protection

If an output short-circuit condition is detected, the power outputs tri-state (latch-OFF) independent of the input (IN1 and IN2) states, and

the fault status output flag (SF) is SET to logic LOW. If the D1 input changes from logic HIGH to logic LOW, or if the EN/D2 input changes

from logic LOW to logic HIGH, the output bridge becomes operational again and the fault status flag resets (cleared) to a logic HIGH state.

The output stage always switches into the mode defined by the input pins (IN1, IN2, D1, and EN/D2), provided the device junction

temperature is within the specified operating temperature range.

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6.3.2 Internal PWM current limiting

The maximum current flow under normal operating conditions should be less than 5.0 A. The instantaneous load currents is limited to I_LIM

via the internal PWM current limiting circuitry. When the I_LIMthreshold current value is reached, the output stages are tri-stated for a fixed

time (T_A) of 20 µs typical. Depending on the time constant associated with the load characteristics, the output current decreases during

the tri-state duration until the next output ON cycle occurs.

The PWM current limit threshold value is dependent on the device junction temperature. When -40 °C <T_J<160 °C, I_LIMis between the

specified minimum/maximum values. When T_Jexceeds 160 °C, the I_LIMthreshold decreases to 4.2 A. Shortly above 175 °C the device

overtemperature circuit detects t_LIMand an overtemperature shutdown occurs. This feature implements a graceful degradation of

operation before thermal shutdown occurs, thus allowing for intermittent unexpected mechanical loads on the motor’s gear-reduction train

to be handled.

Important:

Die temperature excursions above 150 °C are permitted only for non-repetitive durations <30 seconds. Provision must be made at the

system level to prevent prolonged operation in the current-foldback region.

6.3.3 Overtemperature shutdown and hysteresis

If an overtemperature condition occurs, the power outputs are tri-stated (latched-OFF) and the fault status flag (SF) is SET to logic LOW.

To reset from this condition, D1 must change from logic HIGH to logic LOW, or EN/D2 must change from logic LOW to logic HIGH. When

reset, the output stage switches ON again, provided the junction temperature is now below the overtemperature threshold limit minus the

hysteresis fault has cleared. When the junction temperature is below the overtemperature threshold limit, EN/D2 clears the fault. When

the junction temperature is below the overtemperature threshold limit minus the hysteresis, D1 clears the fault.

Important:

Resetting from the fault condition clears the fault status flag. Powering down and powering up the device resets the 34931 from the fault

condition.

6.3.4 Output avalanche protection

If VPWR were to become an open circuit, the outputs would likely tri-state simultaneously due to the disable logic. This could result in an

unclamped inductive discharge. The VPWR input to the 34931 should not exceed 40 V during this transient condition, to prevent electrical

overstress of the output drivers.This can be accomplished with a zener clamp or MOV, and/or an appropriately valued input capacitor with

sufficiently low ESR (see Figure 13).

V

PWR

VPWR

Bulk

Low ESR

Cap.

100nF

OUT1

OUT2

M

9

I/Os

AGND PGND

Figure 13. Avalanche protection

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NXP Semiconductors

17

7

Typical applications

7.1

Introduction

A typical application schematic is shown in Figure 14. For precision high-current applications in harsh, noisy environments, the V_PWRby-

pass capacitor may need to be substantially larger.

V

PWR

100 μF

100 nF

VPWR

33nF

VDD

LOGIC SUPPLY

VCP

CHARGE

PUMP

HS1

LS1

HS2

CCP

IN1

OUT1

OUT2

M

TO GATES

HS1

LS2

LS1

IN2

EN/D2

D1

HS2

LS2

PGND

GATE DRIVE

AND

PROTECTION

LOGIC

+5.0 V

VSENSE

CURRENT MIRRORS

AND

CONSTANT OFF-TIME

STATUS

FLAG

ILIM PWM

SF

FB

PWM CURRENT REGULATOR

TO

ADC

R

FB

270 Ω

1.0 μF

AGND

PGND

Figure 14. 34931 Typical application schematic

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NXP Semiconductors

8

Packaging

8.1

Package dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.NXP.com and

perform a keyword search for the drawing’s document number.

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19

34931

20

NXP Semiconductors

34931

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21

9

Thermal addendum

9.1

Introduction

This thermal addendum is provided as a supplement to the MC34931 technical datasheet. The addendum provides thermal performance

information which may be critical in the design and development of system applications. All electrical, application, and packaging

information is provided in the datasheet.

9.2

Package and thermal considerations

The MC34931 is offered in a 32-pin SOICW-EP single die package. There is a single heat source (P), a single junction temperature (T_J),

and thermal resistance (R_θJA).

T_J

.

=

R_θJA

P

The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This

methodology is not meant to, and does not predict the performance of a package in an application-specific environment. Stated values

were obtained by measurement and simulation according to the standards listed below.

Table 7. Table of thermal resistance data

Rating

Value

Unit

Notes

Junction to Ambient

Natural Convection

(32),(33)

Single Layer board (1s)

Four layer board (2s2p)

R_θJA

92.0

°C/W

Junction to Ambient

Natural Convection

(32),(34)

R_θJA

26.6

°C/W

(35)

(38)

(36)

(37)

Junction to Board

Junction to Case (bottom / flag)

Junction to Case (top)

R_θJB

7.0

0.62

23.3

2.7

°C/W

R_θJC

(bottom)

R_θJC(top)

Junction to Package Top

Natural Convection

Ψ_JT

Notes

32. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,

ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

33. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

34. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

35. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top

surface of the board near the package.

36. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

37. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per

JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

38. Thermal resistance between the die and the case bottom / flag surface (simulated) (flag bottom side fixed to ambient temperature).

34931

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NXP Semiconductors

100

10

1

]

W

/

C

°

[

e

c

n

a

t

s

i

s

e

R

l

a

m

r

e

h

T

0.1

0.001

0.01

0.1

1

10

100

1000

10000

Time [s]

Figure 15. Transient thermal resistance R_θJAMC34931EK on 2s2p test board

34931

NXP Semiconductors

23

Figure 16. Typical duty cycle linearity over frequency at 36 V for MC34932SEK

Operating the part continuously at more than 24 V and up to 36 V while switching the outputs at high frequencies causes additional power

dissipation on the die due to high switching losses. This could result in junction temperature (T_J) exceeding the thermal foldback

temperature (T_FB) and even thermal shutdown (T_LIM) threshold. Hence, while operating the part at such conditions, it is important to

consider methods to keep the junction temperature (T_J) below 165 °C to prevent the part exceeding the thermal foldback temperature

threshold (T_FB) and limit the current internally.

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24

NXP Semiconductors

10 References

Table 8. Thermal analysis reference documents

Reference

Description

AN4146

Thermal Modeling and Simulation of 12 V Gen3 eXtreme Switch Devices with SPICE

Basic Principles of Thermal Analysis for Semiconductor Systems

BASICTHERMALWP

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NXP Semiconductors

25

11 Revision history

Revision

1.0

Date

Description

Initial Release based on the MC33931 Data sheet

7/2013

10/2013

•

2.0

Reduced the sleep mode current specifications

•

Updated as per PCN # 16555

Added new part number MC34931SEK with higher slew rate to support PWM frequency up to 20 kHz

Updated the operating voltage up to 36 V (max.) after characterization and testing

Changed the rise/fall time, sleep current, output leakage current, sleep and stand-by current based on test and

characterization data

2/2015

3.0

4.0

•

Added performance curves of key parameters to show operation up to 36 V

•

Changed the document classification from Advance Information to Technical Data

Corrected typo in Table 1

7/2015

9/2015

8/2016

•

Added a column for PWM frequency to Table 1

Updated to NXP document form and style

34931

26

NXP Semiconductors

Information in this document is provided solely to enable system and software implementers to use NXP products.

There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits

based on the information in this document. NXP reserves the right to make changes without further notice to any

products herein.

How to Reach Us:

Home Page:

NXP.com

Web Support:

http://www.nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular

purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"

parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,

and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each

customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor

the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the

following address:

http://www.nxp.com/terms-of-use.html.

NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or

Document Number: MC34931

Rev. 4.0

8/2016


型号：	MC34931SEKR2
厂家：	NXP
描述：	H-Bridge, Brushed DC Motor Driver, High Slew Rate, 5-28V, 5A, Cur FB, Sleep, SOICW-EP 32, Reel
文件：	总27页 (文件大小：450K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC34931SEKR2 [NXP]

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