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AC16835DGG-T [NXP]

IC ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP2-56, Bus Driver/Transceiver;
AC16835DGG-T
型号： AC16835DGG-T
厂家： NXP    NXP
描述：

IC ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP2-56, Bus Driver/Transceiver

驱动 光电二极管 输出元件 逻辑集成电路
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INTEGRATED CIRCUITS  
74ALVC16835  
18-bit universal bus driver with  
5V tolerant inputs (3-State)  
Product specification  
IC24 Data Handbook  
1999 Mar 18  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
18-bit universal bus driver with 5V tolerant inputs  
(3-State)  
74ALVC16835  
FEATURES  
PIN CONFIGURATION  
• Wide supply voltage range of 1.2V to 3.6V  
NC  
NC  
1
2
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
NC  
• Complies with JEDEC standard no. 8-1A.  
• CMOS low power consumption  
• Direct interface with TTL levels  
• Current drive ± 24 mA at 3.0 V  
Y
3
A
0
0
GND  
4
GND  
Y
1
5
A
1
Y
6
A
V
A
A
A
2
2
TM  
• MULTIBYTE flow-through standard pin-out architecture  
V
7
CC  
CC  
3
• Low inductance multiple V and GND pins for minimum noise  
CC  
Y
Y
Y
8
3
4
5
and ground bounce  
9
4
• Output drive capability 50Ω transmission lines @ 85°C  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
5
GND  
GND  
Y
Y
Y
Y
A
A
A
A
A
A
6
7
8
9
6
DESCRIPTION  
7
The 74ALVC16835 is a 18–bit universal bus driver. Data flow is  
controlled by output enable (OE), latch enable (LE) and clock inputs  
(CP).  
8
9
Y
10  
10  
11  
When LE is HIGH, the A to Y data flow is transparent. When LE is  
LOW and CP is held at LOW or HIGH, the data is latched; on the  
LOW to HIGH transient of CP the A–data is stored in the  
latch/flip-flop.  
Y
11  
GND  
GND  
Y
Y
Y
A
A
A
V
A
A
12  
13  
14  
12  
13  
14  
CC  
15  
16  
When OE is LOW the outputs are active. When OE is HIGH, the  
outputs go to the high impedance OFF–state. Operation of the OE  
input does not affect the state of the latch/flip-flop.  
V
CC  
To ensure the high-impedance state during power up or power  
Y
15  
16  
down, OE should be tied to V through a pullup resistor; the  
CC  
Y
minimum value of the resistor is determined by the current-sinking  
capability of the driver.  
GND  
GND  
Y
A
17  
17  
OE  
LE  
CP  
GND  
SH00130  
QUICK REFERENCE DATA  
GND = 0V; T  
= 25°C; t = t ≤ 2.5ns  
amb  
r f  
SYMBOL  
PARAMETER  
CONDITIONS  
TYPICAL  
UNIT  
Propagation delay  
An to Yn;  
LE to Yn;  
2.3  
2.6  
2.5  
t
/t  
V
V
= 3.3V, C = 50pF  
ns  
PHL PLH  
CC  
L
CP to Yn  
F
Maximum clock frequency  
Input capacitance  
= 3.3V, C = 50pF  
350  
4.0  
8.0  
MHz  
pF  
max  
CC  
L
C
C
I
Input/Output capacitance  
pF  
I/O  
transparent mode  
Output enabled  
Output disabled  
13  
3
1
C
Power dissipation capacitance per buffer  
V = GND to V  
I CC  
pF  
PD  
Clocked mode  
Output enabled  
Output disabled  
22  
15  
NOTES:  
1. C is used to determine the dynamic power dissipation (P in µW):  
PD  
D
2
2
P
= C × V  
× f + S (C × V  
× f ) where: f = input frequency in MHz; C = output load capacitance in pF;  
CC o i L  
D
PD  
CC  
i
L
2
f = output frequency in MHz; V = supply voltage in V; S (C × V  
o
× f ) = sum of outputs.  
o
CC  
L
CC  
2
1999 Mar 18  
853-2095 21052  
Philips Semiconductors  
Product specification  
18-bit universal bus driver with 5V tolerant inputs  
(3-State)  
74ALVC16835  
ORDERING INFORMATION  
TEMPERATURE  
RANGE  
OUTSIDE NORTH  
DRAWING  
NUMBER  
PACKAGES  
NORTH AMERICA  
AC16835 DGG  
AMERICA  
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II  
–40°C to +85°C  
74ALVC16835 DGG  
SOT364-1  
PIN DESCRIPTION  
LOGIC SYMBOL (IEEE/IEC)  
PIN NUMBER  
SYMBOL NAME AND FUNCTION  
27  
OE  
CP  
LE  
EN1  
2C3  
1, 2, 55  
NC  
No connection  
30  
28  
3, 5, 6, 8, 9, 10, 12, 13,  
14, 15, 16, 17, 19, 20,  
21, 23, 24, 26  
C3  
G2  
Y to Y  
Data outputs  
0
17  
4, 11, 18, 25, 32, 39, 46,  
53, 56  
3
5
54  
52  
51  
49  
48  
47  
45  
44  
43  
42  
Y
0
A
0
GND  
Ground (0V)  
Y
Y
Y
Y
Y
Y
Y
Y
Y
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
6
7, 22, 35, 50  
27  
V
CC  
Positive supply voltage  
8
1
1
3D  
Output enable input  
(active LOW)  
OE  
9
10  
12  
13  
14  
Latch enable input  
(active HIGH)  
28  
30  
LE  
CP  
Clock input  
54, 52, 51, 49, 48, 47,  
45, 44, 43, 42, 41, 40,  
38, 37, 36, 34, 33, 31  
15  
16  
17  
19  
20  
21  
23  
24  
26  
A
A
A
A
A
A
A
A
A
A to A  
0
Data inputs  
9
17  
41  
40  
38  
37  
36  
34  
33  
31  
Y
10  
10  
11  
12  
13  
14  
15  
16  
17  
Y
11  
12  
13  
14  
15  
16  
17  
LOGIC SYMBOL  
Y
Y
Y
Y
Y
Y
OE  
CP  
SH00154  
LE  
FUNCTION TABLE  
A
0
D
INPUTS  
Y
0
OUTPUTS  
LE  
OE  
H
L
LE  
X
H
H
L
CP  
X
X
X
↑
A
X
L
CP  
Z
L
L
H
L
H
L
L
TO THE 17 OTHER CHANNELS  
L
L
↑
H
X
X
H
1
L
L
H
L
Y
0
0
SH00138  
2
L
L
Y
H
L
X
Z
↑
=
=
=
=
=
HIGH voltage level  
LOW voltage level  
Don’t care  
High impedance “off” state  
LOW-to-HIGH level transition  
NOTES:  
1. Output level before the indicated steady-state input conditions  
were established, provided that CP is high before LE goes low.  
2. Output level before the indicated steady-state input conditions  
were established.  
3
1999 Mar 18  
Philips Semiconductors  
Product specification  
18-bit universal bus driver with 5V tolerant inputs  
(3-State)  
74ALVC16835  
RECOMMENDED OPERATING CONDITIONS  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
MAX  
UNIT  
DC supply voltage 2.5V range (for max. speed  
performance @ 30 pF output load)  
2.3  
2.7  
DC supply voltage 3.3V range (for max. speed  
performance @ 50 pF output load)  
V
V
CC  
3.0  
3.6  
3.6  
DC supply voltage (for low-voltage applications)  
DC Input voltage range  
1.2  
0
V
V
CC  
V
CC  
V
V
I
V
DC output voltage range  
0
O
T
amb  
Operating free-air temperature range  
–40  
+85  
°C  
V
CC  
V
CC  
= 2.3 to 3.0V  
= 3.0 to 3.6V  
0
0
20  
10  
t , t  
r
Input rise and fall times  
ns/V  
f
ABSOLUTE MAXIMUM RATINGS  
In accordance with the Absolute Maximum Rating System (IEC 134)  
Voltages are referenced to GND (ground = 0V)  
SYMBOL  
PARAMETER  
DC supply voltage  
CONDITIONS  
RATING  
–0.5 to +4.6  
–50  
UNIT  
V
V
CC  
I
IK  
DC input diode current  
V t0  
I
mA  
1
For control pins  
–0.5 to +4.6  
V
DC input voltage  
V
I
1
For data inputs  
uV or V t 0  
–0.5 to V +0.5  
CC  
I
DC output diode current  
DC output voltage  
V
O
mA  
V
"50  
OK  
CC  
O
V
O
Note 1  
= 0 to V  
CC  
–0.5 to V +0.5  
CC  
I
O
DC output source or sink current  
V
O
mA  
mA  
°C  
"50  
"100  
I
, I  
DC V or GND current  
GND CC  
CC  
T
stg  
Storage temperature range  
–65 to +150  
Power dissipation per package  
–plastic medium-shrink (SSOP)  
–plastic thin-medium-shrink (TSSOP) above +55°C derate linearly with 8 mW/K  
For temperature range: –40 to +125 °C  
above +55°C derate linearly with 11.3 mW/K  
850  
600  
P
TOT  
mW  
NOTE:  
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
4
1999 Mar 18  
Philips Semiconductors  
Product specification  
18-bit universal bus driver with 5V tolerant inputs  
(3-State)  
74ALVC16835  
DC ELECTRICAL CHARACTERISTICS  
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).  
LIMITS  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
Temp = -40°C to +85°C  
UNIT  
1
MIN  
1.7  
TYP  
1.2  
1.5  
1.2  
1.5  
MAX  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 2.3 to 2.7V  
V
HIGH level Input voltage  
LOW level Input voltage  
V
V
IH  
= 2.7 to 3.6V  
= 2.3 to 2.7V  
= 2.7 to 3.6V  
2.0  
0.7  
0.8  
V
IL  
= 2.3 to 3.6V; V = V or V ; I = –100µA  
V
*0.2  
V
CC  
I
IH  
IL  
O
CC  
= 2.3V; V = V or V ; I = –6mA  
V
V
V
V
V
0.3  
0.6  
0.5  
0.6  
V
V
V
V
V
0.08  
0.26  
0.14  
0.09  
0.28  
*
*
*
*
*
I
IH  
IL  
O
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
= 2.3V; V = V or V ; I = –12mA  
*
*
*
*
I
IH  
IL  
O
V
OH  
HIGH level output voltage  
V
= 2.7V; V = V or V ; I = –12mA  
I
IH  
IL  
O
= 3.0V; V = V or V ; I = –12mA  
I
IH  
IL  
O
= 3.0V; V = V or V  
I
= –24mA  
*1.0  
CC  
I
IH  
IL; O  
= 2.3 to 3.6V; V = V or V ; I = 100µA  
GND  
0.07  
0.15  
0.14  
0.27  
0.20  
0.40  
0.70  
0.40  
0.55  
V
V
I
IH  
IL  
O
= 2.3V; V = V or V ; I = 6mA  
I
IH  
IL  
O
= 2.3V; V = V or V ; I = 12mA  
V
OL  
LOW level output voltage  
I
IH  
IL  
O
= 2.7V; V = V or V ; I = 12mA  
V
I
IH  
IL  
O
= 3.0V; V = V or V  
I = 24mA  
IL; O  
I
IH  
V
= 2.3 to 3.6V;  
CC  
CC  
I
Input leakage current  
0.1  
0.1  
5
µA  
µA  
I
V = V or GND  
I
V
V
= 2.3 to 3.6V; V = V or V ;  
I IH IL  
CC  
O
I
3-State output OFF-state current  
10  
OZ  
= V or GND  
CC  
I
Quiescent supply current  
V
= 2.3 to 3.6V; V = V or GND; I = 0  
0.2  
40  
µA  
µA  
CC  
CC  
CC  
I
CC  
O
∆I  
Additional quiescent supply current  
V
= 2.3V to 3.6V; V = V – 0.6V; I = 0  
150  
750  
CC  
I
CC  
O
NOTES:  
1. All typical values are at T  
= 25°C.  
amb  
5
1999 Mar 18  
Philips Semiconductors  
Product specification  
18-bit universal bus driver with 5V tolerant inputs  
(3-State)  
74ALVC16835  
AC CHARACTERISTICS FOR V = 2.3V TO 2.7V RANGE  
CC  
GND = 0V; t = t ≤ 2.0ns; C = 30pF  
r
f
L
LIMITS  
SYMBOL  
PARAMETER  
WAVEFORM  
V
CC  
= 2.3 to 2.7V  
UNIT  
1
MIN  
TYP  
MAX  
Propagation delay  
An to Yn  
1, 8  
2, 8  
4, 8  
7, 8  
7,8  
1.0  
2.4  
2.8  
2.8  
2.2  
2.0  
4.2  
Propagation delay  
LE to Yn  
t
/t  
ns  
1.0  
1.0  
1.0  
1.0  
5.0  
5.0  
4.0  
–
PHL PLH  
Propagation delay  
CP to Yn  
3-State output enable time  
OE to Yn  
t
t
/t  
ns  
ns  
PZH PZL  
3-State output disable time  
OE to Yn  
/t  
PHZ PLZ  
CP pulse width HIGH or LOW  
LE pulse width HIGH  
4, 8  
2, 8  
6, 8  
6, 8  
3, 8  
3, 8  
4, 8  
2.0  
2.0  
1.0  
1.5  
0.6  
1.4  
150  
–
–
–
–
–
–
–
–
–
t
ns  
ns  
W
Set-up time An to CP  
Set-up time An to LE  
–
t
SU  
–
Hold time An to CP  
0.2  
0.4  
300  
t
ns  
h
Hold time An to LE  
F
max  
Maximum clock pulse frequency  
MHz  
NOTE:  
1. All typical values are at V = 3.3V and T  
= 25°C.  
amb  
CC  
AC CHARACTERISTICS FOR V = 3.0V TO 3.6V RANGE AND V = 2.7V  
CC  
CC  
GND = 0V; t = t ≤ 2.5ns; C = 50pF  
r
f
L
LIMITS  
LIMITS  
SYMBOL  
PARAMETER  
WAVEFORM  
V
CC  
= 3.3 ± 0.3V  
V
CC  
= 2.7V  
UNIT  
1, 2  
1
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
Propagation delay  
An to Yn  
1, 8  
2, 8  
4, 8  
7, 8  
7, 8  
1.0  
2.3  
3.6  
4.5  
4.2  
4.4  
4.1  
1.0  
2.7  
2.8  
2.7  
3.0  
3.1  
4.0  
Propagation delay  
LE to Yn  
t
/t  
ns  
1.0  
1.0  
1.0  
1.0  
2.6  
2.5  
2.3  
2.8  
1.0  
1.0  
1.0  
1.0  
5.2  
4.9  
5.4  
4.6  
PHL PLH  
Propagation delay  
CP to Yn  
3-State output enable time  
OE to Yn  
t
t
/t  
ns  
ns  
PZH PZL  
3-State output disable time  
OE to Yn  
/t  
PHZ PLZ  
CP pulse width HIGH or LOW  
LE pulse width HIGH  
4, 8  
2, 8  
6, 8  
6, 8  
3, 8  
3, 8  
4, 8  
2.0  
2.0  
1.0  
1.5  
0.7  
1.4  
150  
–
–
–
–
–
–
–
–
–
2.0  
2.0  
1.0  
1.5  
0.6  
1.7  
200  
–
–
–
–
–
–
–
–
–
t
ns  
ns  
W
Set-up time An to CP  
Set-up time An to LE  
–
–
t
SU  
–
–
Hold time An to CP  
0.3  
0.3  
300  
0.3  
0.4  
t
ns  
h
Hold time An to LE  
F
max  
Maximum clock pulse frequency  
350  
MHz  
NOTES:  
1. All typical values are measured T  
= 25°C.  
amb  
2. Typical value is measured at V = 3.3V  
CC  
6
1999 Mar 18  
Philips Semiconductors  
Product specification  
18-bit universal bus driver with 5V tolerant inputs  
(3-State)  
74ALVC16835  
AC WAVEFORMS FOR V = 3.0V TO 3.6V AND  
CC  
1/f  
MAX  
V
= 2.7V RANGE  
CC  
V
I
V
V
V
V
= 1.5 V  
M
X
Y
OL  
CC  
V
V
M
= V + 0.3V  
M
CP INPUT  
GND  
OL  
= V – 0.3V  
OH  
t
W
and V are the typical output voltage drop that occur with the  
OH  
t
t
PLH  
PHL  
output load.  
V = 2.7V  
I
V
OH  
V
Yn OUTPUT  
M
AC WAVEFORMS FOR V = 2.3V TO 2.7V AND  
CC  
V
OL  
V
< 2.3V RANGE  
CC  
NOTE: V = 0.5V at V = 2.3 to 2.7V  
M
CC  
CC  
SH00135  
V
M
V
X
V
V
= 0.5 V  
Waveform 4. The clock (CP) to Yn propagation delays, the  
clock pulse width and the maximum clock frequency.  
= V + 0.15V  
OL  
= V – 0.15V  
Y
OH  
and V are the typical output voltage drop that occur with the  
OL  
OH  
output load.  
V = V  
I
CC  
V
I
V
CP INPUT  
M
V
I
GND  
A
n
V
M
t
su  
t
su  
INPUT  
t
h
t
h
GND  
V
I
t
t
PLH  
PHL  
An INPUT  
V
Y
OH  
n
GND  
V
M
OUTPUT  
V
OH  
V
OL  
V
M
Yn OUTPUT  
NOTE: V = 0.5V at V = 2.3 to 2.7V  
M
CC  
CC  
SH00132  
V
OL  
Waveform 1. Input (Dn) to output (Yn) propagation delay  
NOTE: The shaded areas indicate when the input is permitted to change  
for predictable output performance.  
V
= 0.5V at V = 2.3 to 2.7V  
M
CC CC  
SH00136  
V
I
Waveform 5. Data set-up and hold times for the An input to the  
clock CP input  
V
V
M
M
LE INPUT  
GND  
t
W
t
t
PLH  
PHL  
V
I
V
OH  
V
nOE INPUT  
GND  
V
M
M
Yn OUTPUT  
V
OL  
NOTE: V = 0.5V at V = 2.3 to 2.7V  
M
CC  
CC  
SH00134  
t
t
PZL  
PLZ  
Waveform 2. Latch enable input (LE) pulse width, the latch  
enable input to output (Yn) propagation delays.  
V
CC  
OUTPUT  
LOW-to-OFF  
OFF-to-LOW  
V
M
V
X
V
V
I
OL  
An  
INPUT  
V
M
t
t
PZH  
PHZ  
GND  
V
OH  
th  
th  
OUTPUT  
HIGH-to-OFF  
OFF-to-HIGH  
V
Y
t
t
SU  
SU  
V
M
V
I
LE  
INPUT  
V
M
GND  
outputs  
enabled  
outputs  
disabled  
outputs  
enabled  
GND  
NOTE: The shaded areas indicate when the input is permitted to change  
NOTE: V = 0.5V at V = 2.3 to 2.7V  
M
CC  
CC  
SH00137  
for predictable output performance.  
V
= 0.5V at V = 2.3 to 2.7V  
CC CC  
M
Waveform 6. 3-State enable and disable times  
SH00133  
Waveform 3. Data set-up and hold times for the An input to the  
LE input  
7
1999 Mar 18  
Philips Semiconductors  
Product specification  
18-bit universal bus driver with 5V tolerant inputs  
(3-State)  
74ALVC16835  
TEST CIRCUIT  
S
1
2 * V  
V
CC  
CC  
Open  
GND  
R
R
= 500 Ω  
= 500 Ω  
L
L
V
V
O
I
PULSE  
GENERATOR  
D.U.T.  
R
T
C
L
Test Circuit for switching times  
DEFINITIONS  
R
L
C
L
R
T
= Load resistor  
= Load capacitance includes jig and probe capacitance  
= Termination resistance should be equal to Z of pulse generators.  
OUT  
SWITCH POSITION  
TEST  
S
V
V
I
1
CC  
t
t
Open  
< 2.7V  
V
CC  
PLH/ PHL  
t
t
t
2.7–3.6V  
2.7V  
PLZ/ PZL  
2 < V  
CC  
t
GND  
PHZ/ PZH  
SV00906  
Waveform 7. Load circuitry for switching times  
8
1999 Mar 18  
Philips Semiconductors  
Product specification  
18-bit universal bus driver with 5V tolerant inputs  
(3-State)  
74ALVC16835  
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm  
SOT364-1  
9
1999 Mar 18  
Philips Semiconductors  
Product specification  
18-bit universal bus driver with 5V tolerant inputs  
(3-State)  
74ALVC16835  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make chages at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1998  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
print code  
Date of release: 07-98  
9397-750-05462  
Document order number:  
Philips  
Semiconductors  

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