935268596118 [NXP]
LVC/LCX/Z SERIES, 1-INPUT INVERT GATE, PDSO5, PLASTIC, SOT-353, SC-88A, 5 PIN;
| 型号： | 935268596118 |
| 厂家： | 
NXP |
| 描述： | LVC/LCX/Z SERIES, 1-INPUT INVERT GATE, PDSO5, PLASTIC, SOT-353, SC-88A, 5 PIN 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总19页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC1GU04
Inverter
Product specification
2003 Feb 12
Supersedes data of 2001 Apr 06
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.65 to 5.5 V
• High noise immunity
The 74LVC1GU04 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
• Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
The input can be driven from either 3.3 or 5 V devices.
This feature allows the use of this device in a mixed
3.3 and 5 V environment.
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Input accepts voltages up to 5 V
• Multiple package options
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall time.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1GU04 provides the inverting single state
unbuffered function.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +125 °C.
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay A to Y
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
1.7
ns
ns
ns
ns
ns
V
CC = 2.5 V; CL = 30 pF; RL = 500 Ω 1.3
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 1.7
CC = 3.3 V; CL = 50 pF; RL = 500 Ω 1.6
V
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω 1.3
CI
input capacitance
6
pF
pF
CPD
power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2
14.9
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2003 Feb 12
2
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
FUNCTION TABLE
See note 1.
INPUT
A
OUTPUT
Y
L
H
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
PACKAGE MATERIAL
TEMPERATURE
PINS
CODE
MARKING
RANGE
74LVC1GU04GW
74LVC1GU04GV
−40 to +125 °C
−40 to +125 °C
5
5
SC-88A
SC-74A
plastic
plastic
SOT353
SOT753
VD
VU4
PINNING
PIN
SYMBOL
DESCRIPTION
1
2
3
4
5
n.c.
not connected
data input A
A
GND
Y
ground (0 V)
data output Y
supply voltage
VCC
handbook, halfpage
n.c.
1
2
3
5
4
V
Y
CC
handbook, halfpage
2
A
Y
4
A
U04
GND
MNA108
MNA042
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2003 Feb 12
3
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
V
V
handbook, halfpage
CC
CC
handbook, halfpage
2
1
4
100 Ω
Y
A
MNA109
MNA636
Fig.3 IEE/IEC logic symbol.
Fig.4 Logic diagram.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
CONDITIONS
MIN.
MAX.
5.5
UNIT
supply voltage
input voltage
output voltage
1.65
0
V
VI
5.5
VCC
+125
20
V
VO
0
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.65 to 2.7 V
CC = 2.7 to 5.5 V
ns/V
ns/V
V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN.
−0.5
−
MAX.
+6.5
UNIT
VCC
IIK
supply voltage
V
input diode current
VI < 0
note 1
−50
mA
V
VI
input voltage
−0.5
−
+6.5
IOK
VO
IO
output diode current
output voltage
VO > VCC or VO < 0
active mode; notes 1 and 2
VO = 0 to VCC
±50
mA
V
−0.5
−
VCC + 0.5
±50
output source or sink current
VCC or GND current
storage temperature
power dissipation per package
mA
mA
°C
I
CC, IGND
−
±100
+150
200
Tstg
PD
−65
−
for temperature range from
mW
−40 to +125 °C
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage van be 5.5 V in normal operation.
2003 Feb 12
4
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
DC CHARACTERISTICS
At recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA
IO = 4 mA
IO = 8 mA
IO = 12 mA
IO = 24 mA
IO = 32 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
0.1
V
V
V
V
V
V
−
−
−
−
−
0.45
0.3
2.7
0.4
3.0
0.55
0.55
4.5
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
1.65 to 5.5
V
CC − 0.1
−
−
V
V
V
V
V
V
1.65
2.3
2.7
3.0
4.5
3.6
0
1.2
1.9
2.2
2.3
3.8
−
−
−
IO = −8 mA
−
−
IO = −12 mA
IO = −24 mA
IO = −32 mA
VI = 5.5 V or GND
VI or VO = 5.5 V
−
−
−
−
−
−
ILI
input leakage current
±0.1
±0.1
±5
±10
µA
µA
Ioff
power OFF leakage
current
−
ICC
quiescent supply current VI = VCC or GND;
IO = 0
5.5
−
−
0.1
5
10
µA
µA
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0
2.3 to 5.5
500
Tamb = −40 to +125 °C
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
V
V
V
V
V
0.70
0.45
0.60
0.80
0.80
IO = 8 mA
IO = 12 mA
IO = 24 mA
IO = 32 mA
2.7
3.0
4.5
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
1.65 to 5.5
1.65
2.3
V
CC − 0.1
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
0.95
1.7
1.9
2.0
3.4
IO = −8 mA
IO = −12 mA
IO = −24 mA
IO = −32 mA
2.7
3.0
4.5
2003 Feb 12
5
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
±5
UNIT
µA
OTHER
VCC (V)
ILI
input leakage current
VI = 5.5 V or GND
VI or VO = 5.5 V
3.6
0
−
−
±0.1
Ioff
power OFF leakage
current
−
±200
µA
µA
µA
ICC
quiescent supply current VI = VCC or GND;
IO = 0
5.5
−
−
−
−
200
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
2.3 to 5.5
5000
IO = 0
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.0 ns.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C
tPHL/tPLH propagation delay A to Y see Figs 5 and 8
1.65 to 1.95 0.3
1.7
1.3
1.7
1.6
1.3
5.0
4.0
5.0
3.7
3.0
ns
ns
ns
ns
ns
2.3 to 2.7
2.7
0.3
0.5
0.5
0.5
3.0 to 3.6
4.5 to 5.5
Tamb = −40 to +125 °C
tPHL/tPLH
propagation delay A to Y see Figs 5 and 8
1.65 to 1.95 0.3
−
−
−
−
−
6.5
5.5
6.5
5.0
4.0
ns
ns
ns
ns
ns
2.3 to 2.7
2.7
0.3
0.5
0.5
0.5
3.0 to 3.6
4.5 to 5.5
2003 Feb 12
6
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
AC WAVEFORMS
V
handbook, halfpage
A input
I
V
M
GND
t
t
PHL
PLH
V
OH
V
Y output
M
V
MNA637
OL
INPUT
tr = tf
VCC
VM
VI
VCC
1.65 to 1.95 V 0.5 × VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
2.3 to 2.7 V
2.7 V
0.5 × VCC
1.5 V
VCC
2.7 V
2.7 V
VCC
3.0 to 3.6 V
4.5 to 5.5 V
1.5 V
0.5 × VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 Input A to output Y propagation delay times.
MNA639
120
fs
handbook, halfpage
G
(mA/V)
100
R
= 560 kΩ
handbook, halfpage
bias
80
60
V
CC
0.47 µF
100 µF
input
output
V
i
40
20
0
A
I
o
MNA638
∆Io
Gfs
=
--------
0
2
4
6
V
(V)
∆Vi
CC
fi = 1 kHz.
Tamb = 25 °C.
VO is constant.
Fig.6 Test set-up for measuring forward
transconductance.
Fig.7 Typical forward transconductance as a
function of supply voltage.
2003 Feb 12
7
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
VCC
VI
CL
RL
tPLH/tPHL
tPZH/tPHZ
tPZL/tPLZ
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
VCC
VCC
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
open
open
open
open
open
GND
GND
GND
GND
GND
2 × VCC
2 × VCC
6 V
500 Ω
500 Ω
500 Ω
500 Ω
2.7 V
2.7 V
VCC
3.0 to 3.6 V
4.5 to 5.5 V
6 V
2 × VCC
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance (see Chapter “AC characteristics”).
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
2003 Feb 12
8
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
APPLICATION INFORMATION
Remark to the application information
Some applications for the 74LVC1GU04 are:
• Linear amplifier (see Fig.9)
All values given are typical values unless otherwise
specified.
• Crystal oscillator (see Fig.10).
R2
handbook, halfpage
handbook, halfpage
R1
V
CC
U04
1 µF
R2
R1
U04
Z
C1
C2
L
out
MNA052
MNA053
ZL > 10 kΩ, R1 ≥ 3 kΩ and R2 ≤ 1 MΩ.
Open loop amplification: AOL = 20 (typical value).
AOL
C1 = 47 pF (typical).
C2 = 22 pF (typical).
R1 = 1 to 10 MΩ (typical).
Voltage amplification: Au = –
-------------------------------------------
R1
1 +
(1 + A
)
OL
-------
R2
R2 optimum value depends on the frequency and required stability
against changes in VCC or average minimum ICC [ICC = 2 mA (typical)
at VCC = 3.3 V and f = 10 MHz].
Maximum output voltage:V o(p-p) ≈ VCC – 1.5 V centered at 0.5VCC
Unity gain bandwidth product: B = 5 MHz (typical value).
Fig.9 Used as a linear amplifier.
Fig.10 Crystal oscillator configuration.
2003 Feb 12
9
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
PACKAGE OUTLINES
Plastic surface mounted package; 5 leads
SOT353
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
(2)
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-88A
97-02-28
SOT353
2003 Feb 12
10
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
Plastic surface mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
1
2
3
p
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
SOT753
SC-74A
02-04-16
2003 Feb 12
11
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferably be kept:
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 220 °C for all the BGA packages and packages
with a thickness ≥ 2.5mm and packages with a
thickness <2.5 mm and a volume ≥350 mm3 so called
thick/large packages
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
• below 235 °C for packages with a thickness <2.5 mm
and a volume <350 mm3 so called small/thin packages.
Wave soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
2003 Feb 12
12
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(3)
PLCC(4), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(4)(5) suitable
not recommended(6)
suitable
SSOP, TSSOP, VSO, VSSOP
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Feb 12
13
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
DATA SHEET STATUS
DATA SHEET
LEVEL
PRODUCT
STATUS(2)(3)
DEFINITION
STATUS(1)
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Feb 12
14
Philips Semiconductors
Product specification
Inverter
74LVC1GU04
NOTES
2003 Feb 12
15
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
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All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
613508/03/pp16
Date of release: 2003 Feb 12
Document order number: 9397 750 10078
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74LVC1GU04;
Inverter
download datasheet
Download datasheet
General description
Features
Applications
Datasheet
Products
Buy online
Parametrics
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Block diagram
Products & packages
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General description
The 74LVC1GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families.
Catalog by
System
•
The input can be driven from either 3.3 or 5 V devices. This feature allows the use of this device in a mixed 3.3 and 5 V
environment.
Cross-reference
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•
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Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.
This device is fully specified for partial power-down applications using Ioff . The Ioff circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
Models
•
•
SoC solutions
The 74LVC1GU04 provides the inverting single state unbuffered function.
Features
●
●
●
Wide supply voltage range from 1.65 to 5.5 V
High noise immunity
Complies with JEDEC standard:
❍
❍
❍
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
●
+-24 mA output drive (VCC = 3.0 V)
●
●
●
●
●
●
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Input accepts voltages up to 5 V
Multiple package options
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from -40 to +125 Cel.
●
Applications
AN10161_2: PicoGate Logic footprints (date 30-Oct-02)
Datasheet
Type number Title
Publication release date Datasheet status
Page count File size (kB) Datasheet
74LVC1GU04 Inverter 2/12/2003
Product specification 16 85 Download
Parametrics
Type number
Package Description Propagation Voltage No. Power
Logic
Output
Delay(ns)
of
Dissipation
Switching Drive
Pins Considerations Levels
Capability
3.3V
PicoGate
Inverter
Low Power or
Battery
Applications
SOT353
(UMT5)
74LVC1GU04GW
2~4
Low
5
TTL
Medium
(Unbuffered)
Products, packages, availability and ordering
Type number
North American Ordering code Marking/Packing Package Device
Buy online
IC packing info
type number
(12NC)
status
Standard Marking
9352 720 22125 * Reel Pack,
Reverse
SOT753
Full production
Full production
Full production
Full production
74LVC1GU04GV
74LVC1GU04GW
-
Standard Marking
9352 685 96115 * Reel Pack,
SMD, 7"
SOT353
(UMT5)
74LVC1GU04GW-
G
-
Standard Marking
9352 685 96118 * Reel Pack,
SMD, 13"
SOT353
(UMT5)
Standard Marking
9352 685 96125 * Reel Pack,
Reverse
SOT353
(UMT5)
-
-
Standard Marking
SOT353
(UMT5)
* Reel Pack,
SMD, Large,
Reverse
Full production
9352 685 96165
Similar products
74LVC1GU04 links to the similar products page containing an overview of products that are similar in function or
related to the type number(s) as listed on this page. The similar products page includes products from the same catalog
tree(s), relevant selection guides and products from the same functional category.
Support & tools
I²C Bus Solutions, Typical I²C Bus Arrangement
Philips PicoGate Logic The logical alternative for miniaturization(date 01-Nov-02)
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