935263704518 [NXP]

IC AM/FM, AUDIO DEMODULATOR, PQFP44, PLASTIC, QFP-44, Receiver IC;


型号：	935263704518
厂家：	NXP
描述：	IC AM/FM, AUDIO DEMODULATOR, PQFP44, PLASTIC, QFP-44, Receiver IC 商用集成电路
文件：	总71页 (文件大小：304K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

TDA9874A

Digital TV sound

demodulator/decoder

Product speciﬁcation

2000 Aug 04

Supersedes data of 1999 Dec 03

File under Integrated Circuits, IC02

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

CONTENTS

FEATURES

GENERAL DESCRIPTION

Supported standards

ORDERING INFORMATION

BLOCK DIAGRAM

2.1

PINNING

FUNCTIONAL DESCRIPTION

6.1

Description of the demodulator and decoder

section

6.2

6.3

Description of the DSP

Description of the analog audio section

I²C-BUS CONTROL

7.1

7.2

7.3

7.4

Introduction

Power-up state

Slave receiver mode

Slave transmitter mode

I²S-BUS DESCRIPTION

LIMITING VALUES

THERMAL CHARACTERISTICS

CHARACTERISTICS

APPLICATION DIAGRAMS

PACKAGE OUTLINES

SOLDERING

14.1

14.2

14.3

14.4

Introduction

Through-hole mount packages

Surface mount packages

Suitability of IC packages for wave, reflow and

dipping soldering methods

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

PURCHASE OF PHILIPS I²C COMPONENTS

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

FEATURES

• Sound IF (SIF) input switch

• SIF Automatic Gain Control (AGC) with 24 dB control

range

• Switchable 10 dB SIF input attenuator

• SIF 8-bit Analog-to-Digital Converter (ADC)

• Easy TV standard programming option

GENERAL DESCRIPTION

The TDA9874A is a single-chip Digital TV Sound

Demodulator/Decoder (DTVSD) for analog and digital

multi-channel sound systems in TV/VCR sets and satellite

receivers.

• Differential Quadrature Phase Shift Keying (DQPSK)

demodulation for different standards, simultaneously

with 1-channel FM demodulation

• Near Instantaneous Companded Audio Multiplex

(NICAM) decoding (B/G, D/K, I and L standard)

2.1

Supported standards

• 2-carrier multi-standard FM demodulation (B/G, D/K,

The multi-standard/multi-stereo capability of the

TDA9874A is of interest in Europe, Hong Kong/PR China

and South East Asia. This includes B/G, D/K, I, M and

L standards. In other application areas there exist subsets

of the standard combinations or only single standards are

transmitted.

I and M standard)

• Single carrier high deviation FM mono demodulation

mode

• Decoding for three analog multi-channel systems (A2)

and satellite sound

• Adaptive de-emphasis for satellite

All A2 (analog 2-carrier) and NICAM systems are

supported. M standard (with mono or BTSC stereo sound)

can be received and processed in mono sound mode.

• Programmable identification (B/G, D/K and M standard)

and different identification times

• FM pilot carrier presence detector

The AM sound of L/L’ standard is normally demodulated in

the 1st sound IF. The resulting AF signal has to be entered

into the mono audio input of the TDA9874A. A second

possibility is to use the internal AM demodulator stage

(with 6.5 MHz intercarrier), which gives limited

performance.

• Optional AM demodulation for L standard,

simultaneously with NICAM

• Monitor selection for FM/AM demodulator outputs and

FM and NICAM signals with peak option

• Automatic FM dematrixing option

Korea has a stereo sound system similar to Europe which

is supported by the TDA9874A. Differences include

deviation, modulation contents and identification. It is

based on M standard.

• Digital crossbar switch

• I²S-bus serial audio output with matrix, level adjust and

mute

• Dual audio Digital-to-Analog Converter (DAC) from

digital crossbar switch to analog crossbar switch,

bandwidth 15 kHz

For all FM standards a high deviation mode for a single

carrier monaural sound demodulation is selectable.

An overview of the supported standards, sound systems

and their key parameters is given in Tables 1 to 3.

• Automatic Volume Level (AVL) control

• Analog crossbar switch with inputs for mono and stereo

• Output selection of mono, stereo, dual, dual A or dual B

• Additional mono output with automatic select

• 20 kHz bandwidth for analog path

The analog multi-channel systems are sometimes also

referred to as 2-carrier systems (2CS).

• Standby mode

• Automatic output selection for TV applications.

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

2.1.1

ANALOG 2-CARRIER SYSTEMS

Table 1 Frequency modulation

CARRIER

FREQUENCY

(MHz)

FM DEVIATION (kHz)

NOM. MAX. OVER.

MODULATION

BANDWIDTH/

DE-EMPHASIS

(kHz/µs)

SOUND

STANDARD

SYSTEM

SC1

mono

SC2

mono

4.5

−

15/75

4.5/4.724

5.5/5.742

6.0

¹⁄₂(L + R)

mono

¹⁄₂(L − R)

15/75 (Korea)

15/50

B/G

−

mono

15/50

D/K (2)

D/K (1)

D/K (3)

6.5/6.742

6.5/6.258

6.5/5.742

¹⁄₂(L + R)

15/50

Table 2 Identiﬁcation for A2 systems

PARAMETER

A2; A2*

A2+ (KOREA)

Pilot frequency

54.6875 kHz = 3.5 × line frequency

55.0699 kHz = 3.5 × line frequency

Stereo identiﬁcation frequency

line frequency

117.5 Hz =

149.9 Hz =

--------------------------------------

133

--------------------------------------

105

Dual identiﬁcation frequency

AM modulation depth

line frequency

--------------------------------------

line frequency

--------------------------------------

274.1 Hz =

276.0 Hz =

50%

2.1.2

2-CARRIER SYSTEMS WITH NICAM

Table 3 NICAM

SC1

MODULATION

SC2

ROLL-

OFF (%) CODING

NICAM

DEVIATION

(kHz)

STANDARD

(MHz) DE-EMPHASIS

NICAM

FREQUENCY

INDEX (%)

TYPE

(MHz)

NOM MAX NOM MAX

B/G

5.5

6.0

6.5

−

5.85

6.552

5.85

J17

100

note 1

note 2

note 1

D/K

−

100

5.85

Notes

1. See “EBU NICAM 728 specification” or equivalent specification.

2. Not yet officially defined.

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

2.1.3

SATELLITE SYSTEMS

An important specification for satellite TV reception is the Astra specification. The TDA9874A is suitable for the reception

of Astra and other satellite signals, with sound carrier frequencies from 4 to 9.2 MHz.

Table 4 FM satellite sound

CARRIER

FREQUENCY

(MHz)

MAXIMUM

FM DEVIATION

(kHz)

BANDWIDTH/

DE-EMPHASIS

(kHz/µs)

MODULATION

INDEX

CARRIER TYPE

MODULATION

Main

Sub

6.50⁽¹⁾

0.26

0.15

85⁽²⁾

mono

m/st/d⁽⁴⁾

15/50⁽³⁾

15/adaptive⁽⁵⁾

7.02/7.20

7.38/7.56

7.74/7.92

8.10/8.28

Notes

1. For other satellite systems, frequencies of e.g. 5.80, 6.60 or 6.65 MHz can also be received.

2. Main channels with high deviation can also be handled.

3. A de-emphasis of 60 µs, or in accordance with J17, is available.

4. m/st/d = mono or stereo or dual language sound.

5. Adaptive de-emphasis is compatible to transmitter specification.

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

VERSION

TDA9874APS

TDA9874AH

SDIP42

QFP44

plastic shrink dual in-line package; 42 leads (600 mil)

SOT270-1

SOT205-1

plastic quad ﬂat package; 44 leads (lead length 2.35 mm);

body 14 × 14 × 2.2 mm

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

BLOCK DIAGRAM

SIF2

SIF1

29 (25)

handbook, full pagewidth

27 (23)

41 (37)

4 (42)

(21) 25

DEC

(20) 24

SSA2

18 (13)

23 (19)

33 (29)

34 (30)

(28) 32

ADDR1

I C-BUS

SUPPLY

SIF

DDA3

(27) 31

INTERFACE

ADDR2

SCL

SSA3

INPUT SWITCH

AGC, ADC

(24) 28

ref1

(18) 22

SDA

ref

(10) 15

NICAM

(12) 17

FM/AM

DEMODULATION

NICAM

DEMODULATION

IDENTIFICATION

PCLK

(8)

n.c.

20 (15)

19 (14)

38 (34)

(7) 13

XTALI

XTALO

SSD2

NICAM

DECODER

(6) 12

DEMATRIX

CLOCK

DDD1

(5) 11

SYSCLK

DIGITAL

SUPPLY

SSD1

(35) 39

DDD3

(36) 40

2-CHANNEL

ANALOG/

SATELLITE

DECODER

SSD3

(26) 30

LEVEL

ADJUST

PEAK

DETECTION

CRESET

(3) 9

DDA1

SUPPLY

DACs

OPAMPS

(4) 10

SSA1

(44) 6

35 (31)

36 (32)

37 (33)

SDO

SSA4

I S-BUS

POST FILTER

3 DACs

DIGITAL

SELECTOR

INTERFACE

(41) 3

REFERENCE

SCK

ref2

(39) 1

TDA9874APS

(TDA9874AH)

EXTIR

ANALOG

CROSSBAR

SWITCH

(40) 2

EXTIL

(38) 42

MONOIN

26 (22)

21 (17)

16 (11)

14 (9)

(16)

TEST1

TEST2

TP1

MONO

2-CHANNEL

OUTPUT

BUFFERS

TEST

CHANNEL

OUTPUT

BUFFERS

TP2

TP3

5 (43)

7 (1)

8 (2)

MHB584

OUTM

OUTL OUTR

The pin numbers given in parenthesis refer to the TDA9874AH.

Fig.1 Block diagram.

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

PINNING

SYMBOL

DESCRIPTION

SDIP42

QFP44

EXTIR

EXTIL

V_ref2

external audio input right channel

external audio input left channel

analog reference voltage for DAC and operational ampliﬁers

second general purpose I/O pin

OUTM

V_SSA4

OUTL

OUTR

V_DDA1

V_SSA1

V_SSD1

V_DDD1

V_SSD2

n.c.

analog output mono

analog ground supply 4 for analog back-end circuitry

analog output left

analog output right

analog supply voltage 1; back-end circuitry 5 V

analog ground supply 1; back-end circuitry

digital ground supply 1; core circuitry

digital supply voltage 1; core voltage regulator circuitry

digital ground supply 2; core circuitry

not connected

−

TP2

−

additional test pin 2; connected to V_SSDfor normal operation

serial NICAM data output (at 728 kHz)

additional test pin 1; connected to V_SSDfor normal operation

NICAM clock output (at 728 kHz)

NICAM

TP1

PCLK

ADDR1

XTALO

XTALI

TP3

ﬁrst I²C-bus slave address modiﬁer input

crystal oscillator output

crystal oscillator input

additional test pin 3; connected to V_SSDfor normal operation

test pin 2; connected to V_SSDfor normal operation

resistor for reference current generation; front-end circuitry

second I²C-bus slave address modiﬁer input

analog ground supply 2; analog front-end circuitry

analog front-end circuitry supply voltage decoupling

test pin 1; connected to V_SSDfor normal operation

sound IF input 2

TEST2

I_ref

ADDR2

V_SSA2

V_DEC

TEST1

SIF2

V_ref1

reference voltage; for analog front-end circuitry

sound IF input 1

SIF1

CRESET

V_SSA3

V_DDA3

SCL

capacitor for Power-on reset

digital ground supply 3; front-end circuitry

analog front-end circuitry regulator supply voltage 3 (5 V)

I²C-bus serial clock input

I²C-bus serial data input/output

I²S-bus serial data output

SDA

SDO

I²S-bus word select input/output

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

SYMBOL

DESCRIPTION

SDIP42

QFP44

SCK

I²S-bus clock input/output

system clock output

SYSCLK

V_DDD3

V_SSD3

digital supply voltage 3; digital I/O pads

digital ground supply 3; digital I/O pads

ﬁrst general purpose I/O pin

MONOIN

analog mono input

handbook, halfpage

EXTIR

MONOIN

EXTIL

ref2

SSD3

DDD3

OUTM

SYSCLK

SCK

SSA4

OUTL

OUTR

SDO

SDA

DDA1

SCL

SSA1

TDA9874APS

SSD1

DDA3

DDD1

SSA3

CRESET

SIF1

SSD2

TP2

NICAM

TP1

ref1

SIF2

PCLK

TEST1

ADDR1

XTALO

XTALI

TEST2

DEC

SSA2

ADDR2

ref

MHB585

Fig.2 Pin configuration (SDIP42).

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

handbook, full pagewidth

33 SCK

OUTL

OUTR

31 SDO

30 SDA

DDA1

SSA1

29 SCL

SSD1

DDD1

DDA3

SSA3

TDA9874AH

SSD2

n.c.

26 CRESET

25 SIF1

TP2

NICAM 10

TP1 11

ref1

23 SIF2

MHB586

Fig.3 Pin configuration (QFP44).

FUNCTIONAL DESCRIPTION

The AGC can be controlled via the I²C-bus; details are

given in Sections 7.3.2, 7.3.3 and 7.4.6.

6.1

Description of the demodulator and decoder

section

6.1.3

MIXER

6.1.1

SIF INPUTS

The digitized input signal is fed to the mixers, which mix

one or both input sound carriers down to zero IF. A 24-bit

control word for each carrier sets the required frequency.

Access to the mixer control word registers is via the

I²C-bus (see Sections 7.3.5 and 7.3.6) or via Easy

Standard Programming (ESP, see Section 7.3.23). When

receiving NICAM programs, a feedback signal is added to

the control word of the second carrier mixer to establish a

carrier-frequency loop.

Two inputs are provided, pin SIF1 and pin SIF2. For higher

SIF signal levels the SIF input can be attenuated with an

internal switchable −10 dB resistor divider. As no specific

filters are integrated, both inputs have the same

specification giving flexibility in application. The selected

signal is passed through an AGC circuit and then digitized

by an 8-bit ADC operating at 24.576 MHz.

6.1.2

AGC

6.1.4

FM AND AM DEMODULATION

The gain of the AGC amplifier is controlled from the ADC

output by means of a digital control loop employing

hysteresis. The AGC has a fast attack behaviour to

prevent ADC overloads, and a slow decay behaviour to

prevent AGC oscillations. For AM demodulation the AGC

must be switched off. When switched off, the control loop

is reset and fixed gain settings can be chosen

(see Table 14).

An FM or AM input signal is fed through a switchable

band-limiting filter into a demodulator that can be used for

either FM or AM demodulation. Apart from the standard

(fixed) de-emphasis characteristic, an adaptive

de-emphasis is available for Wegener-Panda 1 encoded

satellite programs.

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

6.1.5

FM DECODING

The status of the NICAM decoder can be read out from the

NICAM status register by the user (see Section 7.4.2). The

OSB bit indicates that the decoder has locked to the

NICAM data. The VDSP bit indicates that the decoder has

locked to the NICAM data and that the data is valid sound

data. The C4 bit indicates that the sound conveyed by the

FM mono channel is identical to the sound conveyed by

the NICAM channel.

A 2-carrier stereo decoder recovers the left and right signal

channels from the demodulated sound carriers. Both the

European and Korean stereo systems are supported.

Automatic FM dematrixing is also supported, which means

that the FM sound mode identification (mono, stereo or

dual) switches the FM dematrix directly. No loop via the

microcontroller is needed.

The error byte contains the number of sound sample errors

(resulting from parity checking) that occurred in the past

128 ms period. The Bit Error Rate (BER) can be calculated

using the following equation:

For highly overmodulated signals, a high deviation mode

for monaural audio sound single carrier demodulation can

be selected.

bit errors

total bits

≈ error byte × 1.74 × 10^–5

NICAM decoding is still possible in high deviation mode.

BER =

-----------------------

6.1.6

FM IDENTIFICATION

6.1.9

NICAM AUTO-MUTE

The identification of the FM sound mode is performed by

AM synchronous demodulation of the pilot and

narrow-band detection of the identification frequencies.

The result is available via the I²C-bus interface. A selection

can be made via the I²C-bus for B/G, D/K and M

standards, and for three different time constants that

represent different trade-offs between speed and reliability

of identification. A pilot detector allows the control software

to identify an analog 2-carrier (A2) transmission within

approximately 0.1 s.

This function is enabled by setting bit AMUTE to logic 0

(see Section 7.3.12). Upper and lower error limits may be

defined by writing appropriate values to two registers in the

I²C-bus section (see Sections 7.3.14 and 7.3.15). When

the number of errors in a 128 ms period exceeds the upper

error limit, the auto-mute function will switch the output

sound from NICAM to whatever sound is on the first sound

carrier (FM or AM) or to the analog mono input. When the

error count is smaller than the lower error limit, the NICAM

sound is restored.

Automatic FM dematrixing, depending on the

identification, is possible.

The auto-mute function can be disabled by setting

bit AMUTE to logic 1. In this case clicks become audible

when the error count increases. The user will hear a signal

of degrading quality.

6.1.7

NICAM DEMODULATION

The NICAM signal is transmitted in a DQPSK code at a bit

rate of 728 kbits/s. The NICAM demodulator performs

DQPSK demodulation and passes the resulting bitstream

and clock signal to the NICAM decoder and, for evaluation

purposes, to various pins.

If no NICAM sound is received, the outputs are switched

from the NICAM channel to the 1st sound carrier.

A decision to enable or disable the auto-mute is taken by

the microprocessor based on an interpretation of the

application control bits C1, C2, C3 and C4, and possibly

any additional strategy implemented by the user in the

microcontroller software.

A timing loop controls the frequency of the crystal oscillator

to lock the sampling instants to the symbol timing of the

NICAM data.

When the AM sound in NICAM L systems is demodulated

in the 1st sound IF and the audio signal connected to the

mono input of the TDA9874A, the controlling

microprocessor has to ensure switching from NICAM

reception to mono input, if auto-muting is desired. This can

be achieved by setting bit AMSEL = 1 and bit AMUTE = 0.

6.1.8

NICAM DECODING

The device performs all decoding functions in accordance

with the “EBU NICAM 728 specification”. After locking to

the frame alignment word, the data is descrambled by

applying the defined pseudo-random binary sequence.

The device then synchronizes to the periodic frame flag

bit C0.

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

6.1.10 CRYSTAL OSCILLATOR

It should be noted that the internal ESD protection diode

does not help here as it only conducts at higher voltages.

Under difficult power supply conditions (e.g. very slow or

non-monotonic ramp-up), it is recommended to drive the

reset line from a microcontroller port or the like.

The digital controlled crystal oscillator (DCXO) is fully

integrated. Only an external 24.576 MHz crystal is

required.

6.1.11 TEST PINS

All test pins are active HIGH. In normal operation of the

device they can be left open-circuit, as they have internal

pull-down resistors. Test functions are for manufacturing

tests only and are not available to customers.

MHB587

handbook, halfpage

> 4.5 V

DDD

6.1.12 POWER FAIL DETECTOR

The power fail detector monitors the internal power supply

for the digital part of the device. If the supply has

temporarily been lower than the specified lower limit, the

power failure register bit PFR in subaddress 0 (see

Section 7.4.1), will be set to logic 1. Bit CLRPFR, slave

Power-on reset flip-flop to logic 0. If this is detected, an

initialization of the TDA9874A has to be performed to

ensure reliable operation.

< 0.3V

DDD

CRESET

1.5

reset active

guaranteed

Fig.4 Reset at Power-on.

6.2

Description of the DSP

6.1.13 POWER-ON RESET

6.2.1

LEVEL SCALING

The reset is active LOW. In order to perform a reset at

power-up, a simple RC circuit may be used which consists

of an integrated passive pull-up resistor and an external

capacitor connected to ground. The pull-up resistor has a

nominal value of 50 kΩ, which can easily be measured

between pins CRESET and V_DDD3. Before the supply

voltage has reached a certain minimum level, the state of

the circuit is completely undefined and remains in this

undefined state until a reset is applied.

All input channels to the digital crossbar switch are

equipped with a level adjustment facility to change the

signal level in a range of ±15 dB. Adjusting the signal level

is intended to compensate for the different modulation

parameters of the various TV standards. Under nominal

conditions it is recommended to scale all input channels to

be 15 dB below full-scale. This will create sufficient

headroom to cope with overmodulation and avoids

changes of the volume impression when switching from

FM to NICAM or vice versa.

The reset is guaranteed to be active when:

• The power supply is within the specified limits

(4.5 to 5.5 V)

6.2.2

NICAM PATH

• The crystal oscillator (DCXO) is functioning

The NICAM path has a switchable J17 de-emphasis.

• The voltage at pin CRESET is below 0.3V_DDD(1.5 V if

V_DDD= 5.0 V, typically below 1.8 V).

6.2.3

NICAM AUTO-MUTE

The required capacitor value depends on the gradient of

the rising power supply voltage. The time constant of the

RC circuit should be clearly larger than the rise time of the

power supply [to make sure that the reset condition is

always satisfied (see Fig.4)], even when considering

tolerance spreading. To avoid problems with a too slow

discharging of the capacitor at power-down, it may be

If NICAM is received, the auto-mute is enabled and the

signal quality becomes poor. The digital crossbar switches

automatically to FM, channel 1 or the analog mono input,

as selected by bit AMSEL. This automatic switching

depends on the NICAM bit error rate. The auto-mute

function can be disabled via the I²C-bus.

helpful to add a diode from pin CRESET to V_DDD

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

6.2.4

FM (AM) PATH

6.2.7

DIGITAL AUDIO OUTPUT

A high-pass filter suppresses DC offsets from the

FM demodulator that may occur due to carrier frequency

offsets, and supplies the FM monitor function with DC

values, e.g. for the purpose of microprocessor controlled

carrier search or fine tuning functions.

The digital audio output interface comprises an I²S-bus

output port and a system clock output. The I²S-bus port is

equipped with a level adjustment facility that can change

the signal level in a ±15 dB range in 1 dB steps. Muting is

possible, too, and outputs can be disabled to improve EMC

performance.

An adaptive de-emphasis is available for

Wegener-Panda 1 encoded satellite programs.

The I²S-bus output matrix provides the functions for forced

mono, stereo, channel swap, channel 1 or channel 2.

The de-emphasis stage offers a choice of settings for the

supported TV standards.

Automatic selection for TV applications is possible. In this

case the microcontroller program only has to provide a

user controlled sound A or sound B selection.

The 2-channel decoder performs the dematrixing of

¹⁄₂(L + R), R to L and R signals of ¹⁄₂(L + R) and ¹⁄₂(L − R)

to L and R signals or of channel 1 and channel 2 to

L and R signals, as demanded by the different TV

standards or user preferences.

6.2.8

STEREO CHANNEL TO THE ANALOG CROSSBAR PATH

A level adjustment function is provided with control

positions of 0 dB, +3 dB, +6 dB and +9 dB in combination

with the audio DACs. The Automatic Volume Level (AVL)

function provides a constant output level of

−20 dB (full-scale) for input levels between

0 dB (full-scale) and −26 dB (full-scale). There are some

ﬁxed decay time constants to choose from, i.e.

2, 4 or 8 seconds.

Automatic FM dematrixing is also supported.

Using the high deviation mode, only channel 1 (mono) can

be demodulated. The scaling is −6 dB compared to

2-channel decoding.

6.2.5

MONITOR

This function provides data words from the

FM demodulator outputs and FM and NICAM signals for

external use, such as carrier search or fine tuning.

The peak level of these signals can also be observed.

Source selection and data read out are performed via the

I²C-bus.

Automatic selection for TV applications is possible. In this

case the microcontroller program only has to provide a

user controlled sound A or sound B selection.

6.2.9

GENERAL

The level adjustment functions can provide signal gain at

multiple locations. Great care has to be taken when using

gain with large input signals, e.g., due to overmodulation,

in order not to exceed the maximum possible signal swing,

which would cause severe signal distortion. The nominal

signal level of the various signal sources to the digital

crossbar switch should be 15 dB below digital full-scale

(−15 dB full-scale).

6.2.6

DIGITAL CROSSBAR SWITCH

The input channels are derived from the FM and NICAM

paths, while the output channels comprise I²S-bus and the

audio DACs to the analog crossbar switch. It should be

noted that there is no connection from the external analog

audio inputs to the digital crossbar switch.

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LEVEL

ADJUST

FIXED

DE-EMPHASIS

stereo DACs

mono DAC

NICAM

LEVEL

ADJUST

DIGITAL

CROSSBAR

SELECT

LEVEL

ADJUST

FILTER

ADAPTIVE

DE-EMPHASIS

FIXED

DE-EMPHASIS

2-CHANNEL

DECODER

MATRIX

I S-bus

I C-bus

MONITOR

MHB588

Fig.5 DSP data flow diagram.

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

6.3

Description of the analog audio section

6.3.2

EXTERNAL AND MONO INPUTS

6.3.1

ANALOG CROSSBAR SWITCH AND ANALOG MATRIX

The external and mono inputs accept signal levels of up to

1.4 V (RMS). By adding external series resistors to

provide suitable attenuation, the external input could be

used as a SCART input. Whenever the external or mono

input is selected, the output of the DAC is muted to

improve the crosstalk performance.

The TDA9874A has one external analog stereo input, one

mono input, one 2-channel and one single-channel output

port. Analog source selector switches are employed to

provide the desired analog signal routing capability, which

is done by the analog crossbar switch section.

The basic signal routing philosophy of the TDA9874A is

that each switch handles two signal channels at the same

time (e.g. left and right, language A and B) directly at the

source. For an overview of the signal flow see Fig.7.

6.3.3

AUDIO DACS

The TDA9874A comprises a 2-channel audio DAC and an

additional single-channel audio DAC for feeding signals

from the DSP section to the analog crossbar switch. These

DACs have a resolution of 15 bits and employ four-times

oversampling and noise shaping.

Each source selector switch is followed by an analog

matrix to perform further selection tasks, such as putting a

signal from one input channel, say language A, to both

output channels or for swapping left and right channels.

The analog matrix provides the functions given in Table 5.

Automatic matrixing for TV applications is also supported.

6.3.4

AUDIO OUTPUT BUFFERS

The output buffers provide a gain of 0 dB and offer a

muting possibility. The post filter capacitors of the audio

DACs are connected to the buffer outputs.

All switches and matrices are controlled via the I²C-bus.

Table 5 Analog matrix functions

6.3.5

STANDBY MODE

The standby mode (see Section 7.3.3) disables most

functions and reduces power dissipation of the

TDA9874A. It provides no other function.

MATRIX OUTPUT

MODE

L OUTPUT

R OUTPUT

L input

R input

L input

R input

L input

R input

Internal registers may lose their information in standby

mode. Therefore, the device needs to be initialized on

returning to normal operation. This can be accomplished in

the same way as after a Power-on reset.

handbook, full pagewidth

source select

matrix

mono (AM)

EXTIL

OUTL

EXTIR

DACL

DACR

OUTR

OUTM

DACM

MHB589

Fig.6 Switch diagram for the analog audio section.

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mono

STEREO

OUTPUT

MATRIX

BUFFER

ANALOG

CROSSBAR

SWITCH

external

LEVEL

ADJUST

NICAM

DEMODULATOR

LEVEL

ADJUST

NICAM

DECODER

MONO

OUTPUT

DE-EMPHASIS

DACs

NICAM

FM/AM

AVL

DIGITAL

CROSSBAR

SELECT

FM/AM

DEMODULATOR

2-CHANNEL

DECODER

LEVEL

ADJUST

ADAPTIVE

DE-EMPHASIS

FIXED

DE-EMPHASIS

LEVEL

ADJUST

MATRIX

I S-bus

MHB590

Fig.7 Audio signal flow.

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

I²C-BUS CONTROL

Introduction

7.2

Power-up state

After Power-on reset respectively at power-up the device

is in the following state:

7.1

The TDA9874A is controlled only via the I²C-bus. Control

is exercised by writing data to one or more internal

registers. Status information can be read from an array of

registers to let the controlling microprocessor determine

whether any action is required.

• All outputs muted

• No sound carrier frequency loaded

• General purpose I/O pins ready for input (HIGH)

• Input SIF1 selected with:

The device has an I²C-bus slave transceiver in

accordance with the fast-mode specification with a

maximum speed of 400 kbits/s. Information about the

I²C-bus can be found in brochure “I²C-bus and how to use

it” (order number 9398 393 40011). To avoid conflicts in a

real application with other ICs providing similar or

complementing functions, there are four possible slave

addresses available, which can be selected by

pins ADDR1 and ADDR2 (see Table 6).

– AGC on

– SIF 10 dB attenuator off

– Small hysteresis.

• Demodulators for both sound carriers set to FM with:

– Identification for B/G, D/K, identification mode ‘slow’

– Level adjustment set to 0 dB

– De-emphasis 50 µs

– Dematrix set to mono

Table 6 Possible slave addresses

– Adaptive de-emphasis off.

SLAVE ADDRESS

ADDR2 ADDR1

• Analog outputs are muted and connected to DACs

• Digital audio interface all outputs off

• Monitor set to carrier 1 DC output.

A6 A5 A4 A3 A2 A1 A0

After Power-on reset or power-up, a device initialization

has to be performed via the I²C-bus to put the TDA9874A

into the proper mode of operation, in accordance with the

desired TV standard, etc. This can be done by writing to all

registers with a single I²C-bus transmission (such as a

refresh operation) or by writing selectively only to those

registers, the contents of which need to be changed with

regard to the power-up state. Easy Standard Programming

(ESP) can also be used.

The I²C-bus interface remains operational in the standby

mode of the TDA9874A to allow the device to be

reactivated via the I²C-bus.

The device will not respond to a ‘general call’ on the

I²C-bus, i.e. when a slave address of 0000 000 is sent by

a master.

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Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

7.3

Slave receiver mode

If an attempt is made to write data to a non-existing

subaddress, the device acknowledges with A (not

acknowledge), therefore telling the I²C-bus master to abort

the transmission. There is no ‘wrap-around’ of

subaddresses.

As a slave receiver, the TDA9874A provides 26 registers

for storing commands and data. Each register is accessed

via a so-called subaddress. A subaddress can be thought

of as a pointer to an internal memory location.

Commands and data will be processed as soon as they

have been received completely. Functions requiring more

than one byte will thus be executed only after all bytes for

that function have been received. If the transmission is

terminated (STOP condition) before all bytes have been

received, the incomplete data for that function is ignored.

Detailed descriptions of the slave receiver registers are

given in Sections 7.3.2 to 7.3.21.

It is allowed to send more than one data byte per

transmission to the TDA9874A. In this event, the

subaddress is automatically incremented after each data

byte, resulting in storing the sequence of data bytes at

successive register locations, starting at SUBADDRESS.

A transmission can start at any valid subaddress. Each

byte that is properly stored, is acknowledged with

A (acknowledge).

Data patterns sent to the various subaddresses are not

checked for being illegal or not at that address, except for

the level adjustment functions.

Detection of a STOP condition without a preceding

acknowledge bit is regarded as a bus error. In this case,

the last operation will not be executed.

Table 7 I²C-bus; slave address, subaddress, data format

SLAVE ADDRESS

SUBADDRESS

DATA

Table 8 Explanation of Table 7

BIT

FUNCTION

START condition

SLAVE ADDRESS

7-bit device address

data direction bit (write to device)

acknowledge

SUBADDRESS

address of register to write to

data byte to be written into register

STOP condition

DATA

Table 9 Format for a transmission employing auto-increment of subaddresses

SLAVE ADDRESS

SUBADDRESS

DATA

BYTE A⁽¹⁾

DATA

Note

1. n data bytes with auto-increment of subaddresses.

PROGRAMMING VIA THE I²C-BUS

7.3.1.1

Programming via subaddresses 0 to 24

7.3.1

While programming the TDA9874A, by writing to

subaddresses 0 to 24, it is not allowed to access

subaddress 255. Writing data to subaddress 255 will

overwrite the data previously written to subaddresses

3 to 10. This may cause unwanted effects.

The TDA9874A can be programmed in the same way as

its predecessor (TDA9874H) using the

subaddresses 0 to 24 or by using ESP.

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Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

7.3.1.2

Using Easy Standard Programming (ESP)

When using ESP it is recommended not to write data to

subaddresses 3 to 10.

This facility simplifies programming by reducing the

amount of data to be set-up and transferred via the

I²C-bus.

A possible programming flow for using ESP and automatic

FM dematrixing (bit TVSM = 1 and bit IDSWFM = 1) is

shown in Table 10. It should be noted that the NICAM

conﬁguration register and the level adjustment registers for

FM and NICAM are not affected by ESP.

Subaddress 255 gives control of most standard dependent

settings of the IC; see ESP register in Section 7.3.23.

Table 10 Programming the TDA9874A by using ESP and automatic FM dematrixing

CONTENT OF REGISTER

NUMBER

NAME

AGCGR

Set AGCGR = 20H for using the −10 dB attenuator at the SIF input, otherwise write a 00H to

this register.

GCONR

Select the chosen SIF input pin by writing data to bit SIFSEL (bit 0) and choose the AGC

decay time corresponding to your application by writing the appropriate data to

bit AGCSLOW (bit 2).

MSR

set this register according to your sound mode detection algorithm

do NOT write data to these registers while using ESP

set FMMR = 80H to choose automatic FM dematrixing

see Table 36

3 to 10

−

FMMR

C1OLAR

C2OLAR

NCONR

NOLAR

NLELR

NUELR

see Table 37

set NCONR = 04H to select FM source automatically if NICAM is not available

see Table 40

set NLELR = 14H (default setting after Power-on reset) if no other value is chosen

set NUELR = 50H (default setting after Power-on reset) if no other value is chosen

AMCONR set AMCONR = F9H to enable all analog outputs

SDACOSR set SDACOSR = 81H to select +6 dB gain (see Table 46) and NICAM or FM output

AOSR

To select an internal source set AOSR = 80H to select dual A or set AOSR = C0H to select

dual B (if dual mode is transmitted) to all analog outputs. For selecting an external source

see Section 7.3.18.

DAICONR use only for I²S-bus output, see detailed description in Section 7.3.19

I²SOSR

I²SOLAR

use only for I²S-bus output, see detailed description in Section 7.3.20

use only for I²S-bus output, see detailed description in Section 7.3.21

MDACOSR Set MDACOSR = 82H to select dual A or set MDACOSR = 83H to select dual B (if dual

mode is transmitted) to all analog outputs. For selecting an external source see

Section 7.3.22.

255

ESP

see detailed description in Section 7.3.23

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Table 11 Overview of the slave receiver registers

DATA

SUBADDRESS

(DECIMAL)

FUNCTION

AGCLEV

AGC gain selection

(ignored if AGC on)

P2OUT

PEAK

P1OUT

STDBY

INIT

MCSM1

CLRPFR AGCSLOW AGCOFF

SIFSEL

MSS0

general conﬁguration

monitor select

MCSM0

MSS1

carrier 1 frequency;

MS part

carrier 1 frequency

carrier 1 frequency;

LS part

carrier 2 frequency;

MS part

carrier 2 frequency

carrier 2 frequency;

LS part

IDMOD1

IDMOD0

IDAREA

FILTBW1 CH2MOD1 CH2MOD0 FILTBW0 CH1MODE demodulator

conﬁguration

ADEEM2

IDSWFM

FMDSC23 FMDSC22 FMDSC21 ADEEM1 FMDSC13 FMDSC12 FMDSC11 FM de-emphasis

FDMS2

FDMS1

FDMS0

FM dematrix

channel 1 output level

adjustment

channel 2 output level

adjustment

DCXOPULL DCXOTEST

DOUTEN

AMSEL

NDEEM

AMUTE

NICAM conﬁguration

NICAM output level

adjustment

NICAM lower error limit

NICAM upper error limit

audio mute control

MUTI2S

MUTSOUT MUTMOUT

SDGS1

AVL1

AVL0

SDGS0

SDOS1

SDOS0

stereo DAC output

select

TVSM

CSM2

CSM1

CSM0

MOS1

MOS0

SSS1

SSS0

analog output select

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DATA

SUBADDRESS

(DECIMAL)

FUNCTION

SYSCL1

SYSCL0

SYSOUT

I2SFORM

IS2OUT digital audio interface

conﬁguration

TVSMIIS

ICSM2

ICSM1

ICSM0

ISS1

ISS0

I²S-bus output select

I²S-bus output level

adjustment

MDGS1

MDGS0

MDOS1

MDOS0 mono DAC output select

reserved

ESP

255

FILTBW1

FILTBW0

IDMOD1

IDMOD0

EPB3

EPB2

EPB1

EPB0

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

7.3.2

AGC GAIN REGISTER (AGCGR)

If the AGC input level shift bit AGCLEV is set to logic 1 the

input signal is scaled with −10 dB. The bit AGCLEV is also

active if the AGC function is enabled.

If the AGC function is switched off in the general

configuration register (see Section 7.3.3), the contents of

this register defines a fixed gain of the SIF input stage. The

input voltages given are meant to generate a nearly

full-scale output from the SIF ADC. If the AGC is on, the

AGC gain setting is ignored. After switching off the AGC

function, the latest gain control setting is copied to the

AGC gain register.

The default setting after Power-on reset is 0000 0000.

In Table 14 the stated step number corresponds with the

SIF level read from subaddress 7 (see Section 7.4.6); the

input voltages should be considered as approximate target

values.

Table 12 AGC gain register (subaddress 0)

AGCLEV

AGCB4

AGCB3

AGCB2

AGCB1

AGCB0

Table 13 Description of the AGC gain register bits

BIT

NAME

DESCRIPTION

−

this bit is not used and should be set to a logic 0

AGCLEV

If the AGC input level shift bit AGCLEV = 1 the input signal is scaled with −10 dB.

Bit AGCLEV is also active if the automatic gain function is enabled.

AGCB4

AGCB3

AGCB2

AGCB1

AGCB0

If the automatic gain control function is switched off in the general conﬁguration register,

the contents of this register will deﬁne a ﬁxed gain of the AGC stage.

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Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

Table 14 AGC gain register

AGC GAIN

(dB)

MAX. SIF INPUT

VOLTAGE [mV (RMS)]

−

AGCLEV AGCB4 AGCB3 AGCB2 AGCB1 AGCB0

0/1

0.0

0.8

333/1052

304/963

278/881

255/806

233/737

213/674

195/617

178/564

163/516

149/472

136/432

125/395

114/361

104/330

96/302

87/276

80/253

73/231

67/212

61/194

56/177

51/162

47/148

43/135

39/124

36/113

33/104

30/95

1.5

2.3

3.1

3.9

4.6

5.4

6.2

7.0

7.7

8.5

9.3

10.1

10.8

11.6

12.4

13.2

13.9

14.7

15.5

16.3

17.0

17.8

18.6

19.4

20.1

20.9

21.7

22.5

23.2

24.0

27/87

25/79

23/73

21/66

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Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

7.3.3

GENERAL CONFIGURATION REGISTER (GCONR)

The default setting after Power-on reset is 1100 0000.

Table 15 General conﬁguration register (subaddress 1)

P2OUT

P1OUT

STDBY

INIT

CLRPFR

AGCSLOW

AGCOFF

SIFSEL

Table 16 Description of the general conﬁguration register bits

BIT

SYMBOL

DESCRIPTION

P2OUT

P1OUT

General purpose I/O pins 1 and 2: these bits control the general purpose input/output

pins. The contents of these bits is written directly to the corresponding pins. If an input is

desired, the bits must be set to 1 to allow the pins to be pulled to LOW levels externally.

Input from the pins is reﬂected in the device status register (see Section 7.4.1).

Bit P1OUT is recommended to be used for switching an SIF trap for the adjacent picture

carrier in designs that employ such a trap.

STDBY

INIT

Standby mode on/off: if bit STDBY = 1 the TDA9874A is set to the standby mode. Most

functions are disabled and power dissipation is somewhat reduced. If bit STDBY = 0 the

TDA9874A is in its normal mode of operation. On return from standby mode, the device

is in its Power-on reset mode and needs to be re-initialized with data deﬁned by the

user.

Initialize to default settings: if bit INIT = 1 it causes initialization of the TDA9874A to its

default settings. This has the same effect as a Power-on reset. In the event of a conﬂict

between the default settings and any bit set to logic 1 in this register, the bits actually

written to this register will overwrite the default settings. This bit is automatically reset

to 0 after initialization has been completed. When set to logic 0, the TDA9874A is in its

normal mode of operation.

CLRPFR

Clear power failure register: if bit CLRPFR = 1 it resets the clear power failure register.

This bit is automatically reset to logic 0 after bit PFR in the device status register has

been read.

AGCSLOW AGC decay time: if bit AGCSLOW = 1 a longer decay time and larger hysteresis are

selected for input signals with strong video modulation (conventional intercarrier). This

bit has only an effect, If bit AGCOFF = 0. If bit AGCSLOW = 0 it selects normal attack

and decay times for the AGC and a small hysteresis.

AGCOFF

AGC on/off: if bit AGCOFF = 1 it forces the AGC block to a ﬁxed gain as deﬁned in the

AGC gain register (see Section 7.3.2). If bit AGCOFF = 0 the AGC function is enabled

and the contents of the AGC gain register are ignored.

SIFSEL

SIF input select: if bit SIFSEL = 1 it selects pin SIF2 for input (recommended for satellite

tuner). If bit SIFSEL = 0 it selects pin SIF1 (recommended for terrestrial TV).

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Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

7.3.4

MONITOR SELECT REGISTER (MSR)

This register is used to define the signal source (the level of which is to be monitored) and the signal channel. Data can

be monitored e.g. before or after the DC filter at the FM/AM demodulator outputs. The peak level of signals can also be

observed. The last available data sample can be read out in the I²C-bus slave transmitter mode (see Section 7.4.5).

Phase means the differentiated phase output of the FM demodulator and is provided when the demodulator operates in

FM mode. The magnitude is supplied in AM mode.

The default setting after Power-on reset is 0000 0000.

Table 17 Monitor select register (subaddress 2)

PEAK

MCSM1

MCSM0

MSS1

MSS0

Table 18 Description of the monitor select register bits

BIT

SYMBOL

DESCRIPTION

PEAK

Peak level select: if bit PEAK = 1 it selects the rectiﬁed peak level of a source to be

monitored. Peak level value is reset to logic 0 after read-out (see read registers

5 and 6). After changing the monitor signal source for peak calculation it is advisable to

ignore the first read-out value due to stored data from previous calculations.

−

these bits are not used and should be set to logic 0

MCSM1

MCSM0

−

Signal channel select: the state of these bits determine which signal channel is

selected; see Table 19.

this bit is not used and should be set to logic 0

MSS1

MSS0

Signal source select: the state of these bits determine which signal source is selected;

see Table 20.

Table 19 Signal channel selection

MCSM1

MCSM0

SIGNAL CHANNEL

CH1 + CH2

-----------------------------

CH1

CH2

Table 20 Signal source selection

MSS1

MSS0

SIGNAL SOURCE

DC output of FM/AM demodulator

magnitude/phase output of FM/AM demodulator

FM/AM path output

NICAM path output

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TDA9874A

7.3.5

CARRIER 1 FREQUENCY REGISTER

where:

data = 24-bit frequency control word

This register should not be used when applying ESP.

Three bytes are required to define a 24-bit frequency

control word to represent the sound carrier (i.e. mixer)

frequency. These three bytes are stored at

subaddresses 3 to 5; subaddress 3 being the high byte.

Execution of the command starts only after all bytes have

been received. If an error occurs, e.g. a premature STOP

condition, partial data for this function is ignored. The

relation of the sound carrier frequency and the control

word is given in the following formula:

f_mix= desired sound carrier frequency

f_clk= 12288 MHz (clock frequency of mixer)

²⁴= 16777216 (number of steps in a 24-bit word size).

Example: A 5.5 MHz sound carrier frequency will be

generated by sending the following sequence of data

bytes to the TDA9874A (data = 7509333 in decimal

notation or 729555 in hexadecimal notation):

0111 0010 1001 0101 0101 0101.

The default setting after Power-on reset is 0000 0000 for

all three bytes.

data = ^mix× 2 ²⁴

--------

f_clk

Table 21 Carrier 1 frequency register high byte (subaddress 3)

Table 22 Carrier 1 frequency register middle byte (subaddress 4)

Table 23 Carrier 1 frequency register low byte (subaddress 5)

7.3.6

CARRIER 2 FREQUENCY REGISTER

If this register is used, it will be for either the second

FM sound carrier of a terrestrial or satellite FM program or

for the NICAM sound carrier.

This register should not be used when applying ESP. The

format is the same as for sound carrier 1, except

subaddresses 6 to 8 are used. Subaddress 6 holds the

high byte.

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Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

7.3.7

DEMODULATOR CONFIGURATION REGISTER

This register should not be used when applying ESP. The default setting after Power-on reset is 0000 0000.

Table 24 Demodulator conﬁguration register (subaddress 9)

IDMOD1

IDMOD0

IDAREA

FILTBW1

CH2MOD1

CH2MOD0

FILTBW0

CH1MODE

Table 25 Description of the demodulator conﬁguration register bits

BIT

SYMBOL

DESCRIPTION

Identiﬁcation mode for FM sound: these bits deﬁne the integrator time of the

FM identiﬁcation. A valid result may be expected after twice this time has expired, at the

latest. The longer the time, the more reliable the identiﬁcation; see Table 26.

IDMOD1

IDMOD0

IDAREA

Application area for FM identiﬁcation: if bit IDAREA = 1 it selects the FM identiﬁcation

frequencies in accordance with the speciﬁcation for Korea. If bit IDAREA = 0 the

frequencies for Europe are selected (B/G and D/K standard).

FILTBW1

this bit selects the ﬁlter bandwidth in accordance with Table 28

CH2MOD1 Channel 2 receive mode: these bits control the hardware for the second sound carrier in

accordance with Table 27. The NICAM mode employs a wider bandwidth of the

decimation ﬁlters than the FM mode.

CH2MOD0

FILTBW0

this bit selects the ﬁlter bandwidth in accordance with Table 28

CH1MODE Channel 1 receive mode: if bit CH1MODE = 1 it selects the hardware for the ﬁrst sound

carrier to operate in AM mode. If bit CH1MODE = 0 the FM mode is assumed. This

applies to both terrestrial and satellite FM reception.

Table 26 Identiﬁcation mode

IDMOD1

IDMOD0

IDENTIFICATION MODE

slow

medium

fast

off/reset, recommended during use of high deviation mode

Table 27 Channel 2 receive mode

CH2MOD1

CH2MOD0

CHANNEL 2

NICAM

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TDA9874A

Table 28 Filter bandwidth for channel 1 and channel 2; note 1

FILTER BANDWIDTH

FILTBW1

FILTBW0

FILTER MODES

CHANNEL 1 CHANNEL 2

narrow

recommended for nominal terrestrial broadcast

conditions and SAT with 2 carriers

extra wide

narrow

Recommended for highly overmodulated single

FM carriers. Only channel 1 is available for

FM demodulation in this mode. NICAM can still be

processed on channel 2.

medium

wide

medium

wide

recommended for moderately overmodulated

broadcast conditions

recommended for strongly overmodulated broadcast

conditions

Note

1. It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial

2-carrier sound. Switching the identification off will reset the associated hardware to a defined state.

7.3.8

FM DE-EMPHASIS REGISTER

This register should not be used when applying ESP. This register is used to select the proper de-emphasis

characteristics as appropriate for the standard of the received carrier. Bits 3 to 0 apply to sound carrier 1, bits 7 to 4 apply

to sound carrier 2. In the event of A2 reception, both groups must be set to the same characteristics.

The default setting after Power-on reset is 0000 0000.

Table 29 FM de-emphasis register (subaddress 10)

ADEEM2

FMDSC23

FMDSC22

FMDSC21

ADEEM1

FMDSC13

FMDSC12

FMDSC11

Table 30 Description of the FM de-emphasis register bits

BIT

SYMBOL

DESCRIPTION

ADEEM2 Adaptive de-emphasis on/off sound carrier 2: if bit ADEEM2 = 1 it activates the adaptive

de-emphasis function (for Wegener-Panda 1 encoded programs), which is required for

certain satellite FM channels. The standard FM de-emphasis must then be set to 75 µs.

If bit ADEEM2 = 0 the adaptive de-emphasis is off.

FMDSC23 FM de-emphasis: the state of these bits determines the FM de-emphasis for sound

carrier 2; see Table 31.

FMDSC22

FMDSC21

ADEEM1

Adaptive de-emphasis on/off sound carrier 1: if bit ADEEM1 = 1 it activates the adaptive

de-emphasis function (for Wegener-Panda 1 encoded programs), which is required for

certain satellite FM channels. The standard FM de-emphasis must then be set to 75 µs.

If bit ADEEM1 = 0 the adaptive de-emphasis is off.

FMDSC13 FM de-emphasis: the state of these bits determines the FM de-emphasis for sound

carrier 1; see Table 31.

FMDSC12

FMDSC11

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Table 31 De-emphasis

FMDSC23

FMDSC13

FMDSC22

FMDSC12

FMDSC21

FMDSC11

DE-EMPHASIS⁽¹⁾

50 µs

60 µs

75 µs

J17⁽²⁾

off

Notes

1. The FM de-emphasis gain is 0 dB at 40 Hz.

2. Not used in any known terrestrial TV sound standard. NICAM de-emphasis is selected in the NICAM configuration

7.3.9

FM DEMATRIX REGISTER (FMMR)

This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received

carrier and the related sound mode identification. For the dematrixing, it is assumed that the output from sound carrier 1

is on channel 1 input. Bits 3 to 6 are not used.

The default setting after Power-on reset is 0000 0000.

Table 32 FM dematrix register (subaddress 11)

IDSWFM

FDMS2

FDMS1

FDMS0

Table 33 Description of the FM dematrix register bits

BIT

SYMBOL

DESCRIPTION

IDSWFM

Automatic FM-dematrix switching: if set to logic 1, the FM dematrix is switched

automatically in dependence on the current FM identiﬁcation result. In case of stereo,

the type of stereo dematrixing (Europe or Korea) is determined by bit IDAREA in

subaddress 9. Bits FDMS2, FDMS1 and FDMS0 are ignored and the dematrix output is

set according to Table 35. With channel 2 in NICAM mode, mono (channel 1) is always

selected.

−

these bits are not used and should be set to logic 0

−

FDMS2

FDMS1

FDMS0

Dematrixing characteristics select: the state of these bits select the dematrixing

characteristics; see Table 34.

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Table 34 Selection of the dematrixing characteristics (manual mode)

FDMS2

FDMS1

FDMS0

L OUTPUT

R OUTPUT

MODE

CH1

CH2

CH1

CH2

CH1

CH2

mono 1

mono 2

CH1

dual

CH2

dual swapped

stereo Europe

stereo Korea −6 dB

2CH1 − CH2

CH1 + CH2

-----------------------------

CH1 – CH2

-----------------------------

CH1 + CH2

CH1 − CH2

stereo Korea

Table 35 Setting of the dematrixing characteristics (automatic mode)

IDENTIFICATION MODE

L OUTPUT

R OUTPUT

Mono

CH1

2CH1 − CH2

CH1 + CH2

CH1

CH2

Stereo

Europe

Korea

CH1 − CH2

CH2

Dual

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7.3.10 CHANNEL 1 OUTPUT LEVEL ADJUSTMENT REGISTER (C1OLAR)

This register is used to correct for standard and station-dependent differences of signal levels. Table 36 applies to the

FM dematrix output channel 1.

The default setting after Power-on reset is 0000 0000.

Table 36 Channel 1 output level adjustment register (subaddress 12)

The selected gain is also applied to the FM signal channel 1 for input to the mono channel.

GAIN SETTING (dB)

+15

+14

+13

+12

+11

+10

not deﬁned

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

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7.3.11 CHANNEL 2 OUTPUT LEVEL ADJUSTMENT REGISTER (C2OLAR)

This register is used to correct for standard and station-dependent differences of signal levels. Table 37 applies to the

FM dematrix output channel 2 in its FM and AM modes. In the event of FM stereo or FM dual language reception,

channels 1 and 2 should be adjusted to the same level. The default setting after Power-on reset is 0000 0000.

Table 37 Channel 2 output level adjustment register (subaddress 13)

The gain chosen is also applied to the FM signal channel 1 for input to the mono channel.

GAIN SETTING (dB)

+15

+14

+13

+12

+11

+10

not deﬁned

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

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7.3.12 NICAM CONFIGURATION REGISTER (NCONR)

The default setting after Power-on reset is 0000 0000.

Table 38 NICAM conﬁguration register (subaddress 14)

DCXOPULL DCXOTEST

DOUTEN

AMSEL

NDEEM

AMUTE

Table 39 Description of the NICAM conﬁguration register bits; see notes 1 to 4

BIT

SYMBOL

DESCRIPTION

DCXOPULL DCXO frequency select: this bit selects the DCXO lower or upper test frequency during

DCXO test mode. If bit DCXOPULL = 1 it sets the DCXO to the lower DCXO frequency.

If bit DCXOPULL = 0 it sets the DCXO to its higher frequency.

DCXOTEST DCXO test mode enable: if bit DCXOTEST = 1 it enables the DCXO test mode

(available only during FM mode). In this mode frequency pulling via bit DCXOPULL is

enabled. If bit DCXOTEST = 0 it enables normal operation.

−

this bit is not used and should be set to logic 0

DOUTEN

Data output enable: if bit DOUTEN = 1 it enables the output of the NICAM serial data

stream from the DQPSK demodulator and of the associated clock, PCLK.

If bit DOUTEN = 0 both outputs will be 3-stated.

−

this bit is not used and should be set to logic 0

AMSEL

Auto-mute select: if bit AMSEL = 1 the auto-mute will switch between NICAM sound and

the analog mono input. This bit only has an effect when the auto-mute function is

enabled and when the DAC has been selected in the analog output select register

(see Section 7.3.18). If bit AMSEL = 0 the auto-mute will switch between NICAM sound

and the sound on the ﬁrst sound carrier (i.e. FM mono or AM).

NDEEM

AMUTE

De-emphasis on/off: if bit NDEEM = 1 it switches the NICAM J17 de-emphasis off.

If bit NDEEM = 0 it switches the NICAM J17 de-emphasis on.

Auto-muting on/off: if bit AMUTE = 1 automatic muting is disabled. This bit only has an

effect when the second sound carrier is set to NICAM. If bit AMUTE = 0 it enables the

automatic switching between NICAM and the program on the ﬁrst sound carrier (i.e.

FM mono or AM), depending on the NICAM bit error rate. The FM dematrix should be

set to the mono position or IDSWFM (subaddress 11) should be set.

Notes

1. The decision of whether auto-muting is permitted will be taken by the controlling microprocessor based on

information contained in the TDA9874A’s status registers. Thus, it depends on the strategy implemented in the

software whether the auto-mute function is in accordance with “NICAM 728 ETS Revised for Data Applications” or

any other preference.

2. The NICAM de-emphasis gain is 0 dB at 40 Hz.

3. The bit AMSEL has only an effect on the analog sound outputs (pins OUTL, OUTR and OUTM). With regard to the

digital sound output (I²S-bus), the auto-mute will only switch between NICAM and the first sound carrier.

4. The DCXO test mode is intended for checking the DCXO control range with the actually used PCB layout and crystal

type. During normal operation, the DCXO test mode should not be used.

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7.3.13 NICAM OUTPUT LEVEL ADJUSTMENT REGISTER (NOLAR)

This register is used to correct for standard and station-dependent differences of signal levels. Table 40 applies to both

NICAM sound outputs. The default setting after Power-on reset is 0000 0000.

Table 40 NICAM output level adjustment register (subaddress 15)

GAIN SETTING (dB)

+15

+14

+13

+12

+11

+10

not deﬁned

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

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7.3.14 NICAM LOWER ERROR LIMIT REGISTER (NLELR)

The difference between the upper and lower error limit

constitutes a hysteresis to avoid frequent switching

between NICAM and the program on the 1st sound carrier.

When the auto-mute function is enabled

(see Section 7.3.12) and the NICAM bit error count is

lower than the value contained in this register, the NICAM

signal is selected (again) for reproduction; see also

Section 7.3.15.

The default setting after Power-on reset is 0101 0000.

Table 42 NICAM upper error limit register

(subaddress 17)

The default setting after Power-on reset is 0001 0100.

Table 41 NICAM lower error limit register

(subaddress 16)

7.3.16 AUDIO MUTE CONTROL REGISTER (AMCONR)

Only bits 6, 2 and 1 are used. When any of these bits is set

to logic 1, the corresponding pair of output channels will be

muted. A bit set to logic 0 allows normal signal output.

7.3.15 NICAM UPPER ERROR LIMIT REGISTER (NUELR)

When the auto-mute function is enabled and the NICAM bit

error count is higher than the value contained in this

or AM sound) or the analog mono input is selected for

reproduction.

The unused bits should be set to logic 1

The default setting after Power-on reset is 1111 1111.

Table 43 Audio mute control register (subaddress 18)

MUTI²S

MUTSOUT

MUTMOUT

Table 44 Description of the audio mute control register bits

BIT

SYMBOL

DESCRIPTION

this bit is not used and should be set to logic 1

Mute I²S-bus output: if bit MUTI²S = 1 the I²S-bus output is muted

−

MUTI²S

−

these bits are not used and should be set to logic 1

MUTSOUT Mute Stereo Output: if bit MUTSOUT = 1 the analog stereo output is muted

MUTMOUT Mute Mono Output: if bit MUTMOUT = 1 the analog mono output is muted

−

this bit is not used and should be set to logic 1

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7.3.17 STEREO DAC OUTPUT SELECT REGISTER

(SDACOSR)

Table 47 AVL control mode

The AVL attack time is always 10 ms.

This register is used to define the signal source to be

entered into the DAC. The stereo DAC output can be

routed to the analog stereo output pins, depending on the

setting in the AOSR; see Section 7.3.18.

AVL1

AVL0

AVL MODE

off or reset

short decay (2 s)

medium decay (4 s)

long decay (8 s)

A simplified setting is possible, if automatic FM dematrix

switching (see Section 7.3.9) and auto-select is applied.

The two combinations of FM and NICAM shown in

Table 48 apply to the (rare) condition that three different

languages are being broadcast in an FM + NICAM system.

They allow for a two-out-of-three selection for special

applications. It should be noted that the controlling

microprocessor has to assure that the FM dematrix is set

to the mono position or that bit IDSWFM is set to logic 1.

Table 48 Signal source left and right

SIGNAL SOURCE STEREO

DAC

SDOS1 SDOS0

LEFT

FM/AM

RIGHT

FM/AM

NICAM left

FM/AM

NICAM right

NICAM M1

NICAM M2

An additional Automatic Volume Level (AVL) control

function is implemented, which provides a constant output

level of −23 dB (full-scale) for input levels between 0 and

−29 dB (full-scale). There are some fixed decay time

constants to choose from, i.e. 2, 4 or 8 s.

FM/AM

The auto-select function is available only if bits SDOS1

and SDOS0 are set to logic 00 or 01. Matrixing can be set

in the analog output select register.

The automatic stereo DAC switching, operating similar to

the mono DAC switching, is shown in Table 54.

The default setting after Power-on reset is 0000 0000.

Bits 2 and 6 are not used and should be set to logic 0.

7.3.18 ANALOG OUTPUT SELECT REGISTER (AOSR)

This register is used to define both the signal source to be

output at the analog outputs and the output channel

selector mode.

Table 45 Stereo DAC output select register

(subaddress 19)

The DAC outputs are automatically muted in the event that

one of the analog inputs is selected for output.

SDGS1 0 AVL AVL SDGS0 0 SDOS1 SDOS0

L + R

The

position of the matrix applies only to the DAC

-------------

Table 46 Selection of stereo DAC gain

outputs, it is not available for analog input signals.

The default setting after Power-on reset is 0000 0000.

DAC GAIN

(dB)

SDGS1

SDGS0

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Table 49 Analog output select register (subaddress 20)

TVSM

CSM2

CSM1

CSM0

MOS1

MOS0

SSS1

SSS0

Table 50 Description of the analog output select register bits

BIT

SYMBOL

DESCRIPTION

TVSM

Auto-select function: for TV applications, only in combination with bit IDSWFM = 1. If set

to logic 1, it switches the matrix automatically depending on bits IDSTE and IDDUA for

FM and the bits S/MB, D/SB for NICAM (see Sections 7.4.1 and 7.4.2).

CSM2

CSM1

CSM0

MOS1

MOS0

SSS1

SSS0

Output channel selection mode, stereo output: these bits select the output channel

selection mode; see Table 51

Signal source for mono output: these bits select the signal source for the mono output;

see Table 52

Signal source for stereo output: these bits select the signal source for the stereo output;

see Table 53

Table 51 Output channel selection mode for stereo output (bit TVSM = 0)

CSM2

CSM1

CSM0

L OUTPUT

R OUTPUT

REMARK

L input

R input

L input

R input

L input

−

not allowed during use of high

deviation mode

L input + R input

------------------------------------------

L input + R input

------------------------------------------

Table 52 Signal source selection analog mono output

MOS1

MOS0

SIGNAL SOURCE

mono DAC

external input L

external input R

mono input

Table 53 Signal source selection stereo output

SSS1

SSS0

SIGNAL SOURCE

DAC

reserved

external input

mono input

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Table 54 Auto-select function (bit TVSM = 1 and bit IDSWFM = 1): FM mode/NICAM mode for stereo DAC

OUTPUT CHANNEL SELECTION

FM IDENT/NICAM SOUND MODE

AUTO-MUTE = HIGH;

MODE

CSM1

CH2MOD = 10

CSM2

CSM0

MONO

STEREO

DUAL

X⁽¹⁾

M/M

L/R

A/A

B/B

FM/AM: M/M

Note

1. X = don’t care.

Signal source selection bits SDOS1 and SDOS0 must be set to logic 0X for FM mode (including FM mode by switching

if auto-mute select is set to logic 0) or to logic 01 for NICAM mode, when using the auto-select function.

7.3.19 DIGITAL AUDIO INTERFACE CONFIGURATION REGISTER (DAICONR)

The default setting after Power-on reset is 0000 0000.

Table 55 Digital audio interface conﬁguration register (subaddress 21)

SYSCL1

SYSCL0

SYSOUT

I2SFORM

I2SOUT

Table 56 Description of the digital audio interface conﬁguration register bits

BIT

SYMBOL

DESCRIPTION

these bits are not used and should be set to logic 0

−

SYSCL1

SYSCL0

SYSOUT

System clock frequency select: these bits select the frequency of the system clock;

see Table 57.

System clock output on/off: if bit SYSOUT = 1 it enables the output of a system (or

master) clock signal at pin SYSCLK. If bit SYSOUT = 0 the output will be off, thereby

improving EMC performance.

I2SFORM Serial output format: if bit I2SFORM = 1 it selects an MSB-aligned, MSB-ﬁrst output

format, i.e. a level change at the word select pin indicates the beginning of a new audio

sample. If bit I2SFORM = 0 it selects the standard I²S-bus output format.

I2SOUT

I²S-bus output on/off: if bit I2SOUT = 1 it enables the output of serial audio data (2 pins)

plus serial bit clock and word select in a format determined by the bit I2SFORM.

The TDA9874A then is an I²S-bus master. If bit I2SOUT = 0 the outputs mentioned will

be 3-stated, thereby improving EMC performance.

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Table 57 System clock frequency select

FREQUENCY

SYSCL1

SYSCL0

SYSCLK OUTPUT

(MHz)

256f_s

384f_s

512f_s

768f_s

8.192

12.288

16.384

24.576

7.3.20 I²S-BUS OUTPUT SELECT REGISTER (I²SOSR)

They allow for a two-out-of-three selection for special

applications. It should be noted that the controlling

microprocessor has to assure that the FM dematrix is set

to the mono position or bit IDSWFM is set to logic 1. If the

I²S-bus signal source is set to FM left or FM right it is

influenced by the automatic FM dematrix switching

(see subaddress 11).

This register is used to define both the signal source to be

output at the I²S-bus port and the mode of the digital matrix

for signal selection.

The two combinations of FM and NICAM shown in

Table 60 apply to the (rare) condition that three different

languages are being broadcast in an FM + NICAM system.

The default setting after Power-on reset is 0000 0000.

Table 58 I²S-bus output select register (subaddress 22)

TVSMIIS

ICSM2

ICSM1

ICSM0

ISS1

ISS0

Table 59 Description of the I²S-bus output select register bits

BIT

SYMBOL

DESCRIPTION

TVSMIIS

Auto-select function: for TV applications, only in combination with bit IDSWFM = 1. If

this bit is set to logic 1 it switches the matrix automatically, depending on the bits IDSTE

and IDDUA for FM and the bits S/MB, D/SB for NICAM in transmitters

subaddresses 0 and 1 (see Sections 7.4.1 and 7.4.2).

ICSM2

ICSM1

ICSM0

−

Output channel selection mode: these bits select the output channel selection mode;

see Table 60.

these bits are not used and should be set to logic 0

−

ISS1

ISS0

Signal source: these bits select the signal source; see Table 60.

Table 60 Mode of the digital matrix for signal selection (bit TVSMIIS = 0)

ICSM2

ICSM1

ICSM0

L OUTPUT

R OUTPUT

REMARK

L input

R input

L input

R input

L input

−

not allowed during use of high

deviation mode

L input + R input

------------------------------------------

L input + R input

------------------------------------------

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Table 61 Signal source left and right; note 1

SIGNAL SOURCE I²S-BUS OUTPUT

ISS1

ISS0

LEFT

RIGHT

FM/AM left

NICAM left

FM/AM

FM/AM right

NICAM right

NICAM M1

NICAM M2

FM/AM

Note

1. The auto-select function is available only if bits ISS1 and ISS0 are set to logic 00 or 01.

Table 62 Auto-select function (bit TVSMIIS = 1 and bit IDSWFM = 1): FM mode/NICAM mode for I²S-bus output

I²S-BUS OUTPUT

ICSM1

FM IDENT/NICAM SOUND MODE

AUTO-MUTE = HIGH;

CH2MOD = 10

ICSM2

ICSM0

MONO

STEREO

DUAL

X⁽¹⁾

M/M

L/R

A/A

B/B

FM/AM: M/M

Note

1. X = don’t care.

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7.3.21 I²S-BUS OUTPUT LEVEL ADJUSTMENT REGISTER (I²SOLAR)

This register is used to adjust the output level at the I²S-bus port. Left and right signal channels are treated identically.

The default setting after Power-on reset is 0000 0000.

Table 63 I²S-bus output level adjustment register (subaddress 23)

GAIN SETTING (dB)

+15

+14

+13

+12

+11

+10

not deﬁned

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

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7.3.22 MONO DAC OUTPUT SELECT REGISTER

(MDACOSR)

The level adjustment for an FM source is determined by

the channel 1 output level adjustment register

(subaddress 12) for mono/dual A, or by the channel 2

output level adjustment register (subaddress 13) for

dual B, or by the NICAM output level adjustment register

(subaddress 15) if a NICAM source is selected.

This register is used to define the signal source to be

entered into the mono DAC. The mono DAC is used for

signal output from digital sources.

For the mono DAC output auto-matrix switching is always

active.

Some extra gain can be introduced at the input to the DAC

to provide a coarse level adjustment function.

L + R

The default setting after Power-on reset is 0000 0000.

In stereo mode

is chosen automatically. Selecting

-------------

Bits 2, 4, 5 and 6 are don’t care and should be set to

logic 0.

Language B (bits MDOS1 and MDOS0 set to

logic 01 or 11) will only show effect, while a dual

transmission via FM A2 or NICAM is being received.

Settings in the FM dematrix register have no effect on the

source selection for the mono DAC.

Table 64 Mono DAC output select register (subaddress 24)

MDGS1

MDGS0

MDOS1

MDOS0

Table 65 Selection of DAC gain

MDGS1

MDGS0

DAC GAIN (dB)

Table 66 Signal source

MDOS1

MDOS0

MONO DAC OUTPUT

L + R

FM/AM

or mono/dual A

-------------

FM/AM dual B if dual mode transmission, otherwise mono

L + R

NICAM

or mono/dual A

-------------

NICAM mono 2 if dual mode transmission, otherwise

mono

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7.3.23 EASY STANDARD PROGRAMMING (ESP) REGISTER

If ESP is not used, the ESP register should not be

accessed in the refresh routine.

This register is used to simplify the setting of different TV

sound standards via the I²C-bus. Writing to this register

will overwrite the contents of registers 3 to 10 with the

settings needed to demodulate one of the standards

shown in Table 68. After power-up, the default setting has

no effect on the settings of registers 3 to 10. Old values of

registers 3 to 10 are not stored. Demodulators filter the

bandwidth and identification time constants are also set

independently from the chosen standard selected in this

Demodulators filter bandwidth and identification time

constants are also set independently in this register.

The default setting after Power-on reset is 0000 0000.

For a description of the bits IDMOD0 and IDMOD1

(FM identification mode), FILTBW0 and FILTBW1

(demodulator filter bandwidth) refer to Section 7.3.7.

Bits IDMOD0 and IDMOD1 (FM identification mode),

FILTBW0 and FILTBW1 (demodulator filter bandwidth) are

identical in registers 255 and 9.

This means for I²C-bus refreshing: using the ESP option,

registers 3 to 10 should not be overwritten during a

refresh.

Table 67 Easy standard programming register (subaddress 255)

FILTBW1

FILTBW0

IDMOD1

IDMOD0

EPB3

EPB2

EPB1

EPB0

Table 68 Available standards for easy standard programming

STANDARD

EPB3

EPB2

EPB1

EPB0

NUMBER

NAME

A2, B/G

A2, M (Korea)

A2, D/K (1)

A2, D/K (2)

A2, D/K (3)

NICAM, I

NICAM, B/G

NICAM, D/K

NICAM, L

reserved

Astra satellite stereo

(7.02/7.20 MHz)

reserved

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7.4

Slave transmitter mode

Each data byte in a read sequence, except for the last one,

is acknowledged with Am. The subaddresses ‘wrap

around’ from decimal 255 to 0. If an attempt is made to

read from a non-existing subaddress, the device will send

a data pattern of all ones, i.e. FF in hexadecimal notation.

As a slave transmitter, the TDA9874A provides

12 registers with status information and data, a part of

which is for Philips internal purposes only. Each register is

accessed by means of a subaddress.

Detailed descriptions of the slave transmitter registers are

given in Sections 7.4.1 to 7.4.9.

Reading of data can start at any valid subaddress. It is

allowed to read more than 1 data byte per transmission

from the TDA9874A. In this case, the subaddress is

automatically incremented after each data byte, resulting

in reading the sequence of data bytes from successive

Table 69 General format for reading data from the TDA9874A

SLAVE ADDRESS

SUBADDRESS

Sr SLAVE ADDRESS

DATA NAm

Table 70 Explanation of Tables 69 and 71

BIT

FUNCTION

START condition

7-bit device address

SLAVE ADDRESS

data direction bit (write to device)

acknowledge (by the slave)

address of register to read from

repeated START condition

SUBADDRESS

data direction bit (read from device)

data byte read from register

not acknowledge (by the master)

acknowledge (by the master)

STOP condition

DATA

NAm

Table 71 Format of a transmission using automatic incrementing of subaddresses

S SLAVE ADDRESS 0 A SUBADDRESS A Sr SLAVE ADDRESS 1 A

DATA BYTE

Am⁽¹⁾

DATA NAm P

Note

1. n data bytes with auto-increment of subaddresses.

2000 Aug 04

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Table 72 Overview of the slave transmitter registers

DATA

SUBADDRESS

(DECIMAL)⁽¹⁾

FUNCTION

P2IN

P1IN

RSSF

AD5

−

AMSTAT

VDSP

OSB

IDDUA

CFC

IDSTE

S/MB

PFR

D/SB

device status (identiﬁcation, etc.)

NICAM status

NICAM error count

additional data (LSB)

additional data (MSB)

level read-out (MSB)

level read-out (LSB)

SIF level

AD7

OVW

AD6

SAD

AD4

CI1

AD3

CI2

AD2

AD10

AD1

AD9

AD0

AD8

−

IDPILOT

−

252

253

254

255

test register 2

test register 1

device identiﬁcation code

software identiﬁcation code

Note

1. Registers from subaddress 252 to 255 are for Philips internal purposes only. They are considered as a set of registers for the identification of

individual members and some key parameters in a family of devices.

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

7.4.1

DEVICE STATUS REGISTER (DSR)

Table 73 Device status register (subaddress 0)

P2IN

P1IN

RSSF

AMSTAT

VDSP

IDDUA

IDSTE

PFR

Table 74 Description of the device status register bits

BIT

SYMBOL

DESCRIPTION

Input from Port 2: this bit reﬂects the status of the general purpose port pin P2;

P2IN

see Section 7.3.3. If bit P2IN = 1 the general purpose port pin P2 is at HIGH level.

If bit P2IN = 0 the general purpose port pin P2 is at LOW level.

P1IN

Input from Port 1: this bit reﬂects the status of the general purpose port pin P1;

see Section 7.3.3. If bit P1IN = 1 then the general purpose port pin P1 is at HIGH level.

If bit P1IN = 0 the general purpose port pin P1 is at LOW level.

RSSF

Reserve sound switching ﬂag: if bit RSSF = 1 it is a copy of bit C4 in the NICAM status

matches the digital transmission and auto-muting should be enabled. If bit RSSF = 0

auto-muting should be disabled, as analog and digital sound are different.

AMSTAT

VDSP

Auto-mute status: if bit AMSTAT = 1 it indicates that the auto-muting function has

switched from NICAM to the program of the ﬁrst sound carrier (i.e. FM mono or AM in

NICAM L systems).

Identiﬁcation of NICAM sound: if bit VDSP = 1 it indicates that digital transmission is a

sound source. If bit VDSP = 0 it indicates that the transmission is either data or a

currently undeﬁned format.

IDDUA

Identiﬁcation of FM dual sound; A2 systems: if bit IDDUA = 1 an FM dual-language

signal has been identiﬁed. When neither bit IDSTE = 1 nor bit IDDUA = 1 the received

signal is assumed to be FM mono (A2 systems only).

IDSTE

PFR

Identiﬁcation of FM stereo; A2 systems: if bit IDSTE = 1 an FM stereo signal has been

identiﬁed (A2 systems only).

Power failure register: the power supply for the digital part of the device (V_DDD1) has

temporarily been lower than the speciﬁed lower limit. If this is detected an initialization of

the device has to be carried out to ensure reliable operation.

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

7.4.2

NICAM STATUS REGISTER (NSR)

Table 75 NICAM status register (subaddress 1)

OSB

CFC

S/MB

D/SB

Table 76 Description of the NICAM status register bits; notes 1 and 2

BIT

SYMBOL

DESCRIPTION

NICAM application control bits: these bits correspond to the control bits C1 to C4 in the

NICAM transmission.

OSB

Synchronization bit: if bit OSB = 1 it indicates that the device has both frame and C0

(16 frame) synchronization. If bit OSB = 0 it indicates that the audio output from the

NICAM part is digital silence.

CFC

Conﬁguration change: if bit CFC = 1 it indicates a conﬁguration change at the 16 frame

(C0) boundary.

S/MB

D/SB

Identiﬁcation of NICAM stereo: if bit S/MB = 1 it indicates stereo mode.

Identiﬁcation of NICAM dual mono: if bit D/SB = 1 it indicates dual mono mode.

Notes

1. The TDA9874A does not support the extended control modes. Therefore, the program of the first sound carrier

(i.e. FM mono or AM) is selected for reproduction in case bit C3 is set to logic 1, independent of bit AMUTE in the

NICAM configuration register being set or not.

2. When a NICAM transmitter is switched off, the device will lose synchronization. In that case the program of the first

sound carrier is selected for reproduction, independent of bit AMUTE being set or not.

7.4.3

NICAM ERROR COUNT REGISTER (NECR)

Bits B7 to B0 contain the number of errors occurring in the previous 128 ms period. The register is updated every

128 ms.

Table 77 NICAM error count register (subaddress 2)

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

7.4.4

DATA REGISTERS DR1 AND DR2

The contents of these two registers provide information on the additional data bits. AD byte 0 is stored at subaddress 3.

Table 78 Data register DR1 (subaddress 3)

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Table 79 Description of the data register DR1 bits

BIT

SYMBOL

DESCRIPTION

the lower 8 bits of the additional data word

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Table 80 Data register DR2 (subaddress 4)

OVW

SAD

−

CI1

CI2

AD10

AD9

AD8

Table 81 Description of the data register DR2 bits

BIT

SYMBOL

DESCRIPTION

OVW

If this bit is logic 1 new additional data bits are written to the IC without the previous bits

being read.

SAD

If bit SAD = 1 new additional data is written into the IC. This bit is reset when the

additional data bits are read.

−

this bit is undeﬁned

CI1

These bits are CI bits decoded by majority logic from the parity checks of the last ten

samples in a frame.

CI2

AD10

AD9

AD8

the upper 3 bits of the additional data word

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Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

7.4.5

LEVEL READ-OUT REGISTERS (LRRA AND LRRB)

Table 84 SIF level register (subaddress 7)

These two bytes constitute a word that provides data from

a location that has been specified with the monitor select

the data is stored at subaddress 5.

IDPILOT

−

Table 85 Description of the SIF level register bits

Table 82 Level read-out register A (subaddress 5)

BIT

SYMBOL

DESCRIPTION

IDPILOT Bit IDPILOT: if this bit is logic 1

it indicates that an FM pilot

carrier in the 2nd channel is

detected; note 1

B7⁽¹⁾

Note

−

this bit is undeﬁned

1. B7 is the most significant bit or sign bit of the word.

−

Table 83 Level read-out register B (subaddress 6)

SIF level data bits: these bits

correspond to the input level at

the selected SIF input

B0⁽¹⁾

Note

1. B0 is the least significant bit of the word.

Note

7.4.6 SIF LEVEL REGISTER (SIFLR)

1. The pilot detector is faster than the stereo/dual

identification, but not as reliable and slightly less

sensitive. By means of the pilot detector bit, the control

software is able to identify an analog 2-carrier (A2)

standard transmission within approximately 0.1 s and

even in the event of a mono transmission (second

sound carrier with pilot). Certain NICAM test signals

may trigger a wrong pilot indication, therefore the pilot

detector bit should not be evaluated at channel 2 mixer

frequencies that correspond to NICAM carriers

(5.85 and 6.552 MHz). For detailed information,

please contact a Philips representative.

When the SIF AGC is on, bits B4 to B0 of this register

contain a number that gives an indication of the SIF input

level. That number can be interpreted in the same way as

the AGC gain register setting (see Section 7.3.2), i.e. if the

SIF AGC were set to a fixed gain and the same number

loaded into the AGC gain register, the current SIF input

signal level would generate a SIF ADC output close to

full-scale.

When the SIF AGC is off, this register returns the contents

of the AGC gain register.

Bits B5 and B6 are don’t care.

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Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

I²S-BUS DESCRIPTION

7.4.7

TEST REGISTER 2 (TR2)

This register contains, as a binary number, the highest

subaddress used for slave receiver registers.

The digital audio interface of the TDA9874A consists of a

serial audio output and associated clock signals. It can be

used to supply digital audio signals from received

TV programs to a suitable output device, e.g. a DAC or an

AES/EBU transmitter.

The first version will have the identification 0010 1101.

Table 86 Test register 2 (subaddress 252)

Two serial audio formats are supported at the digital audio

interface, the I²S-bus format and a very similar

MSB-aligned format. The difference is illustrated in Fig.8.

In both formats the left audio channel of a stereo sample

pair is output first, and is on the Serial Data line (SDO)

when the Word Select line (WS) is at LOW level. Data is

written on the trailing edge of SCK and read on the leading

edge of SCK. The most significant bit is sent first.

7.4.8

TEST REGISTER 1 (TR1)

This register contains, as a binary number, the highest

subaddress used for slave transmitter (status) registers.

The first version will have the identification 0000 0111.

After Power-on reset, the outputs of the digital audio

interface are 3-stated to reduce EMC and allow for

combinations with other ICs. If an output is desired, it has

to be activated by means of an I²C-bus command.

Table 87 Test register 1 (subaddress 253)

When the output is enabled, serial audio data can be taken

from pin SDO. Depending on the signal source, switch and

matrix positions, the output can be either mono, stereo or

dual language.

7.4.9

DEVICE IDENTIFICATION CODE (DIC)

There will be several devices in the digital TV sound

processor family, with TDA9874A being the second

member. This byte is used to identify the individual family

members.

The Word Select output (WS) is clocked with the audio

sample frequency of 32 kHz. The Serial Clock output

(SCK) is clocked at a frequency of 2.048 MHz. This means

that there are 64 clock pulses per pair of stereo output

samples, or 32 clock pulses per sample. There are

18 significant bits used on the Serial Data Output (SDO).

The first version will have the identification 0001 0001.

Table 88 Device identiﬁcation code (subaddress 254)

A symmetrical system clock output (SYSCLK) is available

from the TDA9874A as a master clock for external digital

audio devices. After Power-on reset, the clock is off. It can

be enabled and the output frequency set via an I²C-bus

command. Available output frequencies are 8.192, 12.288,

16.384 and 24.576 MHz.

7.4.10 SOFTWARE IDENTIFICATION CODE (SIC)

It is likely that during the life time of this family of devices

several versions of the DSP software will be made, e.g. to

incorporate new application concepts, respond to

customer wishes, etc. This byte is used to identify the

different releases.

The first version will have the identification 0000 0010.

Table 89 Software identiﬁcation code (subaddress 255)

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

handbook, full pagewidth

SCK

LSB

MSB

LSB

MSB

SDO

MGK758

one sample

a. I²S-bus format.

handbook, full pagewidth

SCK

LSB

MSB

LSB

MSB

SDO

MGK759

one sample

b. MSB-aligned format.

Fig.8 Serial audio interface formats.

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL

PARAMETER

CONDITIONS

MIN. MAX. UNIT

V_DDx

∆V_DDx

I_IK

DC supply voltage

−0.5

−

+6.5

550

±10

voltage differences between two V_DDxpins

DC input clamp diode current

V_i< −0.5 V or

−

V_i> V_DD+ 0.5 V

I_OK

DC output clamp diode current output type 4 mA

V_o< −0.5 V or

−

±20

V_o> V_DD+ 0.5 V

I_o

_DDD, I_SSDDC V_DDDor V_SSDcurrent per digital supply pin

I_DDA, I_SSADC V_DDAor V_SSAcurrent per analog supply pin

DC output source or sink current; output type 4 mA −0.5 V < V_O< V_DD+ 0.5 V

−

±20

±96

±50

−

I_lu(prot)

P/out

P_tot

latch-up protection current

power dissipation per output

total power dissipation

storage temperature

100

−

100

0.75

−

T_stg

−55

−20

2000

200

+125 °C

T_amb

V_es

ambient temperature

+70

−

°C

electrostatic handling voltage

note 1

note 2

−

Notes

1. Human body model: C = 100 pF and R = 1.5 kΩ.

2. Machine model: C = 200 pF, L = 0.75 µH and R = 0 Ω.

10 THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

in free air

VALUE

UNIT

R_th(j-a)

thermal resistance from junction to ambient

K/W

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

11 CHARACTERISTICS

V_DD= 5 V; T_amb= 25 °C; settings in accordance with B/G standard; FM deviation ±50 kHz; f_mod= 1 kHz; FM sound

parameters in accordance with system A2; NICAM in accordance with “EBU NICAM 728 speciﬁcation”;

1 kΩ measurement source resistance for AF inputs; V_SIF= 300 mV (p-p); bit AGCOFF = 0; bit AGCSLOW = 1;

level and gain settings according to note 1 with external components of Fig.9; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Digital supplies

V_DDD1

V_SSD1

I_DDD1

digital supply voltage 1

digital ground supply 1

digital supply current 1

4.5

5.0

5.5

−

0.0

−

V_DDD1= 5.5 V

−

V_DDD1= 5.0 V

V_SSD2

V_DDD3

V_SSD3

I_DDD3

digital ground supply 2

digital supply voltage 3

digital ground supply 3

digital supply current 3

0.0

5.0

0.0

4.5

−

5.5

−

V_DDD3= 5.5 V; SYSCLK off

V_DDD3= 5.0 V; SYSCLK off

Power failure register

V_pfr

power failure response voltage

−

4.0

−

Demodulator supplies and references

V_DDA3

V_SSA3

I_DDA3

analog supply voltage 3 for

demodulator part

4.5

5.0

0.0

5.5

analog ground supply 3 for

demodulator part

−

analog supply current 3 for

demodulator part

V_DDA3= 5.5 V

_DDA3= 5.0 V

−

3.3

−

V_DEC1

analog supply decoupling

voltage for front-end

V_SSA2

V_ref1

analog ground supply 2

−

0.0

−

analog reference voltage for

demodulator part

I_ref1(sink)

sink current at pin V_ref1

−

200

−

µA

Audio supplies and references

V_DDA1

V_SSA1

I_DDA1

analog supply voltage 1 for

operational ampliﬁers

4.5

5.0

0.0

5.5

analog ground supply 1 for

operational ampliﬁers

−

analog supply current 1 for

operational ampliﬁers

V_DDA1= 5.5 V

_DDA1= 5.0 V

−

V_SSA4

V_ref2

analog ground supply 4 for

audio DAC part

0.0

reference voltage 2 for audio

referenced to V_DDA1and

−

DACs and operational ampliﬁers V_SSA1

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Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Z_{(Vref2-VDDA3)}impedance between pins V_ref2

and V_DDA3

−

kΩ

Z_{(Vref2-VSSA3)}impedance between pins V_ref2

and V_SSA3

kΩ

Digital inputs and outputs

INPUTS

CMOS level input, high drive, pull-down (pins TEST1, TEST2, TP1 and TP2)

V_IL

V_IH

C_i

LOW-level input voltage

HIGH-level input voltage

input capacitance

−

0.3V_DDD

0.7V_DDD

−

kΩ

Z_i

input impedance

CMOS level input, hysteresis, high drive, pull-up (pin CRESET)

V_IL

V_IH

V_hys

C_i

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

−

0.3V_DDD

0.7V_DDD

−

1.3

−

input capacitance

−

kΩ

Z_i

input impedance

INPUTS/OUTPUTS

I²C-bus level input with Schmitt trigger, open-drain output stage (pins SCL and SDA)

V_IL

V_IH

V_hys

I_LI

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

−

0.3V_DDD

−

0.7V_DDD

−

0.05V_DDD

−

input leakage current

input capacitance

−

±10

µA

C_i

V_OL

C_L

LOW-level output voltage

load capacitance

0.6

400

TTL/CMOS level, high drive, 4 mA 3-state output stage, pull-up (pins PCLK, NICAM, ADDR1, ADDR2, P1, P2, SCK,

WS and SDO)

V_IL

V_IH

C_i

LOW-level input voltage

HIGH-level input voltage

input capacitance

−

0.8

−

2.0

−

0.4

−

V_OL

V_OH

C_L

LOW-level output voltage

HIGH-level output voltage

load capacitance

I_OL= 3 mA

−

I_OH= −3 mA

active pull-up

2.4

−

100

−

kΩ

Z_i

input impedance

−

OUTPUTS

4 mA 3-state output stage (pin SYSCLK)

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

I_OL= 2 mA

−

0.3V_DDD

I_OH= −2 mA

0.7V_DDD

−

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Digital TV sound demodulator/decoder

TDA9874A

SYMBOL

C_L

I_LOZ

PARAMETER

load capacitance

3-state leakage current

CONDITIONS

MIN.

TYP.

MAX.

100

UNIT

−

V_i= 0 to V_DDD

±10

µA

SIF1 and SIF2 analog inputs

V_{SIF(max)(p-p)}maximum composite SIF input

voltage before clipping

SIF input level adjustment

0 dB

−

941

2976

−

(peak-to-peak value)

SIF input level adjustment

−10 dB

V_{SIF(min)(p-p)}minimum composite SIF input

voltage for lower limit of AGC

(peak-to-peak value)

SIF input level adjustment

0 dB

SIF input level adjustment

188

−10 dB

AGC

f_i

AGC range

−

input frequency

input resistance

input capacitance

FM deviation

9.2

−

MHz

kΩ

R_i

AGCLEV = 0

−

C_i

−

7.5

−

∆f_FM

∆f_FM(FS)

B/G standard; THD < 1%

±100

±150

kHz

FM deviation full-scale level

terrestrial FM; level

adjustment 0 dB;

−

demodulator ﬁlter bandwidth

set to narrow

∆f_FM(max)

C/N_FM

C/N_N

maximum FM deviation in high B/G standard; THD < 1%;

±335

−

kHz

deviation mode

demodulator ﬁlter bandwidth

set to extra wide

FM carrier-to-noise ratio

N_FMbandwidth = 6 MHz;

white noise for S/N = 40 dB;

“CCIR468-2”; quasi peak

−

------

NICAM carrier-to-noise ratio

N_Nbandwidth = 6 MHz;

bit error rate = 10⁻³;

white noise

−

------

α_ct

crosstalk attenuation

SIF1 to SIF2

f_i= 4 to 9.2 MHz

Demodulator performance

V_o(nom)(rms)

nominal level output voltage

(RMS value)

note 1

400

500

0.3

600

0.5

THD + N

total harmonic distortion plus

noise

from FM source to any

output; f_i= 1 kHz; bandwidth

20 Hz to 20 kHz;

−

V_o= 1 V (RMS)

from NICAM source to any

output; f_i= 1 kHz; bandwidth

20 Hz to 20 kHz;

−

0.1

0.3

V_o= 1 V (RMS)

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TDA9874A

SYMBOL

S/N

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

signal-to-noise ratio

SC1 from FM source to any 64

output; V_o= 1 V (RMS);

“CCIR468-2”; quasi peak

−

SC2 from FM source to any 60

output; V_o= 1 V (RMS);

“CCIR468-2”; quasi peak

SC1 during use of high

deviation mode from

FM source to any output;

V_o= 1 V (RMS);

“CCIR468-2”; quasi peak

NICAM source;

V_o= 1 V (RMS);

NICAM in accordance with

“EBU speciﬁcation”; note 2

“CCIR468-2”; quasi peak

B_−3dB

−3 dB bandwidth

from FM source to any

output

14.5

−2

−

kHz

from NICAM source to any

output

−

f_res

frequency response

20 Hz to 14 kHz

from FM/NICAM to any

output; reference 1 kHz

α_cs(dual)

α_cs(stereo)

α_AM

dual signal channel separation

stereo channel separation

AM suppression for FM

note 3

note 4

−

AM: 1 kHz, 30% modulation; 50

reference: f_i= 1 kHz; 50 kHz

deviation

dm_AM

AM demodulation

SIF level 100 mV (RMS);

54% AM; 1 kHz AF;

−

“CCIR468-2”; quasi peak

IDENTIFICATION FOR FM SYSTEMS

mod_p

C/N_p

pilot modulation for identiﬁcation

pilot sideband carrier-to-noise

ratio for identiﬁcation start

−

------

hys_(tun)

f_ident

hysteresis

−

identiﬁcation window

B/G stereo

slow mode

medium mode

fast mode

116.85

116.11

114.65

−

118.12 Hz

118.89 Hz

120.46 Hz

B/G dual

slow mode

medium mode

fast mode

273.44

−

274.81 Hz

276.20 Hz

277.60 Hz

272.07

270.73

t_ident(on)

total identiﬁcation time on

slow mode

medium mode

fast mode

−

0.5

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Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

SYMBOL

PARAMETER

CONDITIONS

slow mode

MIN.

TYP.

MAX.

UNIT

t_ident(off)

total identiﬁcation time off

−

medium mode

fast mode

0.5

Mono and external inputs

V_i(nom)(rms)

V_i(clip)(rms)

R_i

nominal level input voltage

(RMS value)

note 1

−

500

1400

−

kΩ

clipping level input voltage

(RMS value)

THD < 3%; note 5

note 5

1250

−

input resistance

Analog audio outputs

V_o(clip)(rms)

clipping level output voltage

THD < 3%

1400

−

(RMS value)

R_o

output resistance

AC load resistor

150

−

250

−

375

−

Ω

R_L(AC)

R_L(DC)

C_L

kΩ

DC load resistor

output load capacitor

static DC offset voltage

mute suppression

−

V_offset(DC)

α_mute

−

nominal input signal from

any source; f_i= 1 kHz;

note 1

B_line

bandwidth

from external and mono

−

kHz

source; −3 dB bandwidth

G_ro

roll-off gain at 14.5 kHz

from any source

−3

−2

−

PSRR

power supply ripple rejection

f_ripple= 70 Hz;

V_ripple= 100 mV (peak);

C_Vref= 47 µF; signal from

I²S-bus

Audio performance

THD + N total harmonic distortion plus

V_i= V_o= 1 V (RMS);

f_i= 1 kHz; bandwidth

20 Hz to 20 kHz; from

external or mono input to

output copy

−

0.1

0.3

noise

S/N

signal-to-noise ratio

reference voltage

−

V_o= 1.4 V (RMS);

f_i= 1 kHz; “CCIR468-2”;

quasi peak; from external or

mono input to output copy

α_ct

crosstalk attenuation

channel separation

between any analog input

pairs; f_i= 1 kHz

−

α_cs

between left and right of

external input pair

between left and right of

output pair

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Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Crystal speciﬁcation (fundamental mode)

f_xtal

C_L

crystal frequency

load capacitance

series capacitance

parallel capacitance

pulling sensitivity

note 6

−

24.576

−

MHz

C₁

C₀

−

Φ_pull

C_Lchanged from

18 to 16 pF

10^–6

-----------

R_R

R_N

equivalent series resistance

at nominal frequency

−

Ω

equivalent series resistance of

unwanted mode

2R_R

−

∆T

X_J

temperature range

adjustment tolerance

drift

−20

−

+25

−

+70

±30

±5

°C

10⁻⁶

X_D

X_A

across temperature range

−

ageing

−

10^–6

-----------

year

Notes

1. Definition of levels and level setting:

a) The full-scale level for analog audio signals is 1.4 V (RMS).

b) The nominal level at the digital crossbar switch is defined at −15 dB (full-scale).

c) Nominal audio input levels: external, mono: 500 mV (RMS); −9 dB (full-scale).

2. Audio performance is limited by the dynamic range of the NICAM 728 system. Due to companding, the quantization

noise is never lower than −62 dB with respect to the input level.

3. FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output;

V_o= 1 V (RMS) of modulated channel.

4. FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output;

V_o= 1 V (RMS) of modulated channel.

5. If the supply voltage for the TDA9874A is switched off, because of the ESD protection circuitry, all audio input pins

are short-circuited.

6. The Philips crystal (order number 9922 520 20106) is suitable for this application.

2000 Aug 04

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Table 90 Level setting FM, AM and NICAM at 0 dB (full-scale) = 1.4 V (RMS)

LEVEL

ADJUSTMENT

SETTING

TRANSMITTERNOMINAL

MODULATION DEPTH

NOMINAL LEVEL AT

DEMODULATOR OUTPUT

NOMINAL LEVEL DAC GAIN NOMINAL OUTPUT

SOURCE

AT CROSSBAR

SETTING

VOLTAGE V_O

M standard

15 kHz deviation

27 kHz deviation

−24 dB (full-scale)

−19 dB (full-scale)

+9 dB

−15 dB (full-scale) +6 dB

(spread of ±0.5 dB

due to different

transmitter

references)

500 mV (RMS)

B/G, D/K, I

standard

+4 dB

L/L accent

standard

54%

−19 dB (full-scale)

−18 dB (full-scale)

−23 dB (full-scale)

+4 dB

+3 dB

+8 dB

NICAM

B/G, D/K,

L standard

−11.2 dB (full-scale)

−15.8 dB (full-scale)

NICAM

I standard

Table 91 Level setting SAT FM at 0 dB (full-scale) = 1.4 V (RMS)

TRANSMITTER

NOMINAL LEVEL AT

LEVEL

ADJUSTMENT

SETTING

MAXIMUM LEVEL DAC GAIN MAXIMUMOUTPUT

SOURCE MAXIMUM MODULATION

DEMODULATOR OUTPUT

DEPTH

AT CROSSBAR

SETTING

VOLTAGE V_O

SAT FM

stereo

50 kHz deviation

−13 dB (full-scale)

+4 dB

−9 dB (full-scale)

+6 dB

1 V (RMS)

SAT FM

mono

85 kHz deviation

−9 dB (full-scale)

0 dB

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

12 APPLICATION DIAGRAMS

handbook, full pagewidth

470 nF

EXTIR

MONOIN

470 nF

EXTIL

47 µF

SSD3

ref2

(2)

470 nF

DDD3

5 V

3.3 Ω

2.2 µF

SYSCLK

SCK

OUTM

SSA4

2.2 µF

OUTL

OUTR

I S-bus

SDO

SDA

10 Ω

DDA1

5 V

I C-bus

470

SCL

SSA1

SSD1

10 Ω

DDA3

5 V

TDA9874APS

470 nF

470

SSA3

DDD1

5 V

(2)

(1)

1 µF

CRESET

SIF1

SSD2

47 pF

TP2

NICAM

TP1

100 nF

50 Ω

ref1

47 pF

SIF2

TEST1

PCLK

(1)

DEC

ADDR1

XTALO

XTALI

TEST2

decoupling

capacitor

470 nF

SSA2

24.576

MHz

ADDR2

8.2 kΩ

ref

(1)

MHB591

All analog and digital supply ground pins are connected internally and should be connected via a massive external ground plate.

(1) TP1, TP2, TEST1 and TEST2 should be connected to V_SSDduring normal operation.

(2) Lx: ferrite bead, e.g. Murata type BLM 31A601S.

Fig.9 Application diagram (SDIP42 version).

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

5 V

handbook, full pagewidth

external input

3.3 Ω

470

µF

470

2.2 µF

(2)

2.2 µF

OUTL

OUTR

SCK

I S-bus

10 Ω

DDA1

SDO

SDA

5 V

470

SSA1

SSD1

I C-bus

SCL

470

10 Ω

DDA3

DDD1

5 V

TDA9874AH

5 V

(2)

470 nF

SSD2

n.c.

SSA3

1 µF

CRESET

SIF1

47 pF

TP2

(1)

100 nF

50 Ω

NICAM

ref1

47 pF

TP1

SIF2

(1)

470 nF

8.2 kΩ

decoupling

capacitor

24.576

MHz

(1)

MHB592

All analog and digital supply ground pins are connected internally and should be connected via a massive external ground plate.

(1) TP1, TP2, TP3, TEST1 and TEST2 should be connected to V_SSDduring normal operation.

(2) Lx: ferrite bead, e.g. Murata type BLM 31A601S.

Fig.10 Application diagram (QFP44 version).

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

13 PACKAGE OUTLINES

SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)

SOT270-1

(e )

w M

pin 1 index

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

max.

(1)

UNIT

min.

max.

1.3

0.8

0.53

0.40

0.32

0.23

38.9

38.4

14.0

13.7

3.2

2.9

15.80

15.24

17.15

15.90

5.08

0.51

4.0

1.778

15.24

0.18

1.73

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-02-04

99-12-27

SOT270-1

MS-020

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm

SOT205-1

(A )

w M

pin 1 index

detail X

w M

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

7^o

0^o

0.25 2.3

0.05 2.1

0.50 0.25 14.1 14.1

0.35 0.14 13.9 13.9

19.2 19.2

18.2 18.2

2.0

1.2

2.4

1.8

2.4

1.8

2.60

0.25

2.35

0.3 0.15 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

97-08-01

99-12-27

SOT205-1

133E01

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

14 SOLDERING

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 230 °C.

14.1 Introduction

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

14.3.2 WAVE SOLDERING

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mount components are mixed on

one printed-circuit board. However, wave soldering is not

always suitable for surface mount ICs, or for printed-circuit

boards with high population densities. In these situations

reflow soldering is often used.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

14.2 Through-hole mount packages

14.2.1 SOLDERING BY DIPPING OR BY SOLDER WAVE

• For packages with leads on two sides and a pitch (e):

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joints for more than 5 seconds. The total contact

time of successive solder waves must not exceed

5 seconds.

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

The footprint must incorporate solder thieves at the

downstream end.

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

14.2.2 MANUAL SOLDERING

Apply the soldering iron (24 V or less) to the lead(s) of the

package, either below the seating plane or not more than

2 mm above it. If the temperature of the soldering iron bit

is less than 300 °C it may remain in contact for up to

10 seconds. If the bit temperature is between

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

300 and 400 °C, contact may be up to 5 seconds.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

14.3 Surface mount packages

14.3.1 REFLOW SOLDERING

14.3.3 MANUAL SOLDERING

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating

method.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

14.4 Suitability of IC packages for wave, reﬂow and dipping soldering methods

SOLDERING METHOD

WAVE

REFLOW⁽¹⁾DIPPING

suitable⁽²⁾

not suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable⁽³⁾

MOUNTING

PACKAGE

Through-hole mount DBS, DIP, HDIP, SDIP, SIL

−

suitable

Surface mount

BGA, SQFP

suitable

−

PLCC⁽⁴⁾, SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended⁽⁴⁾⁽⁵⁾

not recommended⁽⁶⁾

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

15 DATA SHEET STATUS

PRODUCT

DATA SHEET STATUS

STATUS

DEFINITIONS ⁽¹⁾

Objective speciﬁcation

Development This data sheet contains the design target or goal speciﬁcations for

product development. Speciﬁcation may change in any manner without

notice.

Preliminary speciﬁcation Qualiﬁcation

This data sheet contains preliminary data, and supplementary data will be

published at a later date. Philips Semiconductors reserves the right to

make changes at any time without notice in order to improve design and

supply the best possible product.

Product speciﬁcation

Production

This data sheet contains ﬁnal speciﬁcations. Philips Semiconductors

reserves the right to make changes at any time without notice in order to

improve design and supply the best possible product.

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

16 DEFINITIONS

17 DISCLAIMERS

Short-form specification

The data in a short-form

Life support applications

These products are not

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the

products, including circuits, standard cells, and/or

software, described or contained herein in order to

improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for

the use of any of these products, conveys no licence or title

under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that

these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified.

Application information

Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

18 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

NOTES

2000 Aug 04

Philips Semiconductors

Product speciﬁcation

Digital TV sound demodulator/decoder

TDA9874A

NOTES

2000 Aug 04

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Pakistan: see Singapore

Belgium: see The Netherlands

Brazil: see South America

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 68 9211, Fax. +359 2 68 9102

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,

Tel. +48 22 5710 000, Fax. +48 22 5710 001

Portugal: see Spain

Romania: see Italy

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Colombia: see South America

Czech Republic: see Austria

Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. +45 33 29 3333, Fax. +45 33 29 3905

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,

Tel. +27 11 471 5401, Fax. +27 11 471 5398

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

South America: Al. Vicente Pinzon, 173, 6th floor,

04547-130 SÃO PAULO, SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 821 2382

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 93 301 6312, Fax. +34 93 301 4107

Hungary: see Austria

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,

Tel. +91 22 493 8541, Fax. +91 22 493 0966

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2741 Fax. +41 1 488 3263

Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,

Tel. +66 2 361 7910, Fax. +66 2 398 3447

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,

ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),

Tel. +39 039 203 6838, Fax +39 039 203 6800

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Middle East: see Italy

Tel. +381 11 3341 299, Fax.+381 11 3342 553

For all other countries apply to: Philips Semiconductors,

Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,

The Netherlands, Fax. +31 40 27 24825

Internet: http://www.semiconductors.philips.com

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

753504/02/pp68

Date of release: 2000 Aug 04

Document order number: 9397 750 06927

Go to Philips Semiconductors' home page

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Description

Consumer Multimedia

Systems

Communications

The TDA9874A is a single-chip Digital TV Sound Demodulator/Decoder (DTVSD) for analog and digital multi-channel sound systems in

TV/VCR sets and satellite receivers.

PC/PC-peripherals

Cross reference

Supported standards

Models

Packages

The multi-standard/multi-stereo capability of the TDA9874A is of interest in Europe, Hong Kong/PR China and South East Asia. This

includes B/G, D/K, I, M and L standards. In other application areas there exist subsets of the standard combinations or only single

standards are transmitted.

Application notes

Selection guides

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