935230190112 [NXP]
IC TELEPHONE SPEECH CKT, PDIP16, 0.300 INCH, PLASTIC, SOT-38, DIP-16, Telephone Circuit;
| 型号： | 935230190112 |
| 厂家： | 
NXP |
| 描述： | IC TELEPHONE SPEECH CKT, PDIP16, 0.300 INCH, PLASTIC, SOT-38, DIP-16, Telephone Circuit 电信 光电二极管 电信集成电路 |
| 文件： | 总30页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TEA1062; TEA1062A
Low voltage transmission circuits
with dialler interface
1997 Sep 03
Product specification
Supersedes data of 1996 Dec 04
File under Integrated Circuits, IC03
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
FEATURES
GENERAL DESCRIPTION
• Low DC line voltage; operates down to 1.6 V (excluding
polarity guard)
The TEA1062 and TEA1062A are integrated circuits that
perform all speech and line interface functions required in
fully electronic telephone sets. They perform electronic
switching between dialling and speech. The ICs operate at
line voltage down to 1.6 V DC (with reduced performance)
to facilitate the use of more telephone sets connected in
parallel.
• Voltage regulator with adjustable static resistance
• Provides a supply for external circuits
• Symmetrical high-impedance inputs (64 kΩ) for
dynamic, magnetic or piezoelectric microphones
• Asymmetrical high-impedance input (32 kΩ) for electret
microphones
All statements and values refer to all versions unless
otherwise specified.
• DTMF signal input with confidence tone
• Mute input for pulse or DTMF dialling
– TEA1062: active HIGH (MUTE)
– TEA1062A: active LOW (MUTE)
• Receiving amplifier for dynamic, magnetic or
piezoelectric earpieces
• Large gain setting ranges on microphone and earpiece
amplifiers
• Line loss compensation (line current dependent) for
microphone and earpiece amplifiers
• Gain control curve adaptable to exchange supply
• DC line voltage adjustment facility.
QUICK REFERENCE DATA
SYMBOL
VLN
PARAMETER
CONDITIONS
Iline = 15 mA
MIN.
TYP. MAX. UNIT
line voltage
3.55
4.0
4.25
V
Iline
operating line current
normal operation
11
1
−
140
11
mA
mA
mA
with reduced performance
internal supply current
supply voltage for peripherals
TEA1062
−
ICC
VCC = 2.8 V
Iline = 15 mA
−
0.9
1.35
VCC
Ip = 1.2 mA; MUTE = HIGH 2.2
Ip = 0 mA; MUTE = HIGH
Ip = 1.2 mA; MUTE = LOW 2.2
2.7
3.4
2.7
3.4
−
−
−
−
V
V
V
V
−
TEA1062A
Ip = 0 mA; MUTE = LOW
−
Gv
voltage gain
microphone amplifier
receiving amplifier
44
−
−
−
52
dB
dB
°C
20
31
Tamb
operating ambient temperature
−25
+75
Line loss compensation
∆Gv
gain control
−
5.8
−
−
dB
V
Vexch
Rexch
exchange supply voltage
exchange feeding bridge resistance
36
0.4
60
1
−
kΩ
1997 Sep 03
2
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TEA1062
DIP16
DIP16
plastic dual in-line package; 16 leads (300 mil)
plastic dual in-line package; 16 leads (300 mil)
SOT38-1
TEA1062M1
SOT38-4 or
SOT38-9
TEA1062A
DIP16
DIP16
plastic dual in-line package; 16 leads (300 mil)
plastic dual in-line package; 16 leads (300 mil)
SOT38-1
TEA1062AM1
SOT38-4 or
SOT38-9
TEA1062T
SO16
SO16
plastic small outline package; 16 leads; body width 3.9 mm
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
SOT109-1
TEA1062AT
BLOCK DIAGRAM
V
LN
1
CC
13
10
5
IR
GAR
4
QR
TEA1062A
7
6
MIC
2
3
GAS1
GAS2
MIC
11
12
DTMF
MUTE
dB
(1)
SUPPLY AND
REFERENCE
CONTROL
CURRENT
LOW VOLTAGE
CIRCUIT
CURRENT
REFERENCE
9
14
15
8
16
SLPE
MBA359 - 1
V
REG AGC
STAB
EE
(1) Pin 12 is active HIGH (MUTE) for TEA1062.
Fig.1 Block diagram for TEA1062A.
1997 Sep 03
3
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
PINNING
SYMBOL
LN
PIN
DESCRIPTION
positive line terminal
1
2
GAS1
GAS2
QR
gain adjustment; transmitting
amplifier
handbook, halfpage
3
4
5
gain adjustment; transmitting
amplifier
1
2
3
4
5
6
7
8
16 SLPE
15 AGC
LN
GAS1
GAS2
QR
non-inverting output; receiving
amplifier
14
13
12
REG
GAR
gain adjustment; receiving
amplifier
V
CC
TEA1062A
GAR
MIC
MUTE
MIC−
MIC+
STAB
VEE
6
inverting microphone input
non-inverting microphone input
current stabilizer
11 DTMF
10 IR
7
8
MIC
9
negative line terminal
STAB
9
V
EE
IR
10
11
12
13
14
15
16
receiving amplifier input
MBA354 - 1
DTMF
MUTE
VCC
dual-tone multi-frequency input
mute input (see note 1)
positive supply decoupling
voltage regulator decoupling
automatic gain control input
slope (DC resistance) adjustment
REG
AGC
SLPE
Fig.2 Pin configuration for TEA1062A.
Note
1. Pin 12 is active HIGH (MUTE) for TEA1062.
1997 Sep 03
4
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
FUNCTIONAL DESCRIPTION
Supplies VCC, LN, SLPE, REG and STAB
LN
Power for the IC and its peripheral circuits is usually
obtained from the telephone line. The supply voltage is
derived from the line via a dropping resistor and regulated
by the IC. The supply voltage VCC may also be used to
supply external circuits e.g. dialling and control circuits.
handbook, halfpage
L
R1
V
R
eq
V
p
REG
CC
ref
Decoupling of the supply voltage is performed by a
capacitor between VCC and VEE. The internal voltage
regulator is decoupled by a capacitor between REG and
R9
20 Ω
C3
4.7 µF
C1
100 µF
V
VEE
.
EE
MBA454
The DC current flowing into the set is determined by the
exchange supply voltage Vexch, the feeding bridge
resistance Rexch and the DC resistance of the telephone
Leq = C3 × R9 × Rp.
Rp = 16.2 kΩ.
line Rline
.
The circuit has an internal current stabilizer operating at a
level determined by a 3.6 kΩ resistor connected between
STAB and VEE (see Fig.9). When the line current (Iline) is
more than 0.5 mA greater than the sum of the IC supply
current (ICC) and the current drawn by the peripheral
circuitry connected to VCC (Ip) the excess current is
shunted to VEE via LN.
Fig.3 Equivalent impedance circuit.
At line currents below 9 mA the internal reference voltage
is automatically adjusted to a lower value (typically 1.6 V
at 1 mA). This means that more sets can be operated in
parallel with DC line voltages (excluding the polarity guard)
down to an absolute minimum voltage of 1.6 V. At line
currents below 9 mA the circuit has limited sending and
receiving levels. The internal reference voltage can be
adjusted by means of an external resistor (RVA).
This resistor when connected between LN and REG will
decrease the internal reference voltage and when
connected between REG and SLPE will increase the
internal reference voltage.
The regulated voltage on the line terminal (VLN) can be
calculated as:
VLN = Vref + ISLPE × R9
VLN = Vref + {(Iline − ICC − 0.5 × 10−3 A) − Ip} × R9
Vref is an internally generated temperature compensated
reference voltage of 3.7 V and R9 is an external resistor
connected between SLPE and VEE
.
In normal use the value of R9 would be 20 Ω.
Current (Ip) available from VCC for peripheral circuits
depends on the external components used. Fig.10 shows
this current for VCC > 2.2 V. If MUTE is LOW (TEA1062) or
MUTE is HIGH (TEA1062A) when the receiving amplifier
is driven, the available current is further reduced. Current
availability can be increased by connecting the supply IC
(TEA1081) in parallel with R1 as shown in Fig.19 and
Fig.20, or by increasing the DC line voltage by means of
an external resistor (RVA) connected between REG and
SLPE (Fig.18).
Changing the value of R9 will also affect microphone gain,
DTMF gain, gain control characteristics, sidetone level,
maximum output swing on LN and the DC characteristics
(especially at the lower voltages).
Under normal conditions, when ISLPE >> ICC + 0.5 mA + Ip,
the static behaviour of the circuit is that of a 3.7 V regulator
diode with an internal resistance equal to that of R9. In the
audio frequency range the dynamic impedance is largely
determined by R1. Fig.3 shows the equivalent impedance
of the circuit.
1997 Sep 03
5
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
Microphone inputs MIC+ and MIC− and gain pins
Receiving amplifier IR, QR and GAR
GAS1 and GAS2
The receiving amplifier has one input (IR) and a
non-inverting output (QR). Earpiece arrangements are
illustrated in Fig.12. The IR to QR gain is typically 31 dB
(when R4 = 100 kΩ). It can be adjusted between
20 and 31 dB to match the sensitivity of the transducer in
use. The gain is set with the value of R4 which is
connected between GAR and QR. The overall receive
gain, between LN and QR, is calculated by subtracting the
anti-sidetone network attenuation (32 dB) from the
amplifier gain. Two external capacitors, C4 and C7, ensure
stability. C4 is normally 100 pF and C7 is 10 times the
value of C4. The value of C4 may be increased to obtain a
first-order low-pass filter. The cut-off frequency will depend
on the time constant R4 × C4.
The circuit has symmetrical microphone inputs. Its input
impedance is 64 kΩ (2 × 32 kΩ) and its voltage gain is
typically 52 dB (when R7 = 68 kΩ, see Figures 14
and 15). Dynamic, magnetic, piezoelectric or electret (with
built-in FET source followers) can be used. Microphone
arrangements are illustrated in Fig.11.
The gain of the microphone amplifier can be adjusted
between 44 dB and 52 dB to suit the sensitivity of the
transducer in use. The gain is proportional to the value of
R7 which is connected between GAS1 and GAS2.
Stability is ensured by two external capacitors, C6
connected between GAS1 and SLPE and C8 connected
between GAS1 and VEE. The value of C6 is 100 pF but this
may be increased to obtain a first-order low-pass filter.
The value of C8 is 10 times the value of C6. The cut-off
frequency corresponds to the time constant R7 × C6.
The output voltage of the receiving amplifier is specified for
continuous-wave drive. The maximum output voltage will
be higher under speech conditions where the peak to RMS
ratio is higher.
Input MUTE (TEA1062)
Automatic Gain Control input AGC
When MUTE is HIGH the DTMF input is enabled and the
microphone and receiving amplifier inputs are inhibited.
The reverse is true when MUTE is LOW or open-circuit.
MUTE switching causes only negligible clicking on the line
and earpiece output. If the number of parallel sets in use
causes a drop in line current to below 6 mA the speech
amplifiers remain active independent to the DC level
applied to the MUTE input.
Automatic line loss compensation is achieved by
connecting a resistor (R6) between AGC and VEE
.
The automatic gain control varies the gain of the
microphone amplifier and the receiving amplifier in
accordance with the DC line current. The control range is
5.8 dB which corresponds to a line length of 5 km for a
0.5 mm diameter twisted-pair copper cable with a DC
resistance of 176 Ω/km and average attenuation of
1.2 dB/km). Resistor R6 should be chosen in accordance
with the exchange supply voltage and its feeding bridge
resistance (see Fig.13 and Table 1). The ratio of start and
stop currents of the AGC curve is independent of the value
of R6. If no automatic line-loss compensation is required
the AGC pin may be left open-circuit. The amplifiers, in this
condition, will give their maximum specified gain.
Input MUTE (TEA1062A)
When MUTE is LOW or open-circuit, the DTMF input is
enabled and the microphone and receiving amplifier inputs
are inhibited. The reverse is true when MUTE is HIGH.
MUTE switching causes only negligible clicking on the line
and earpiece output. If the number of parallel sets in use
causes a drop in line current to below 6 mA the DTMF
amplifier becomes active independent to the DC level
applied to the MUTE input.
Dual-tone multi-frequency input DTMF
When the DTMF input is enabled dialling tones may be
sent on to the line. The voltage gain from DTMF to LN is
typically 25.5 dB (when R7 = 68 kΩ) and varies with R7 in
the same way as the microphone gain. The signalling
tones can be heard in the earpiece at a low level
(confidence tone).
1997 Sep 03
6
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
Sidetone suppression
EXAMPLE
The anti-sidetone network, R1//Zline, R2, R3, R8, R9 and
Zbal, (see Fig.4) suppresses the transmitted signal in the
earpiece. Maximum compensation is obtained when the
following conditions are fulfilled:
The balance impedance Zbal at which the optimum
suppression is present can be calculated by:
Suppose Zline = 210 Ω + (1265 Ω//140 nF) representing a
5 km line of 0.5 mm diameter, copper, twisted-pair cable
matched to 600 Ω (176 Ω/km; 38 nF/km).
R8 × Zbal
R9 × R2 = R1 × R3 +
(1)
------------------------
R8 + Zbal
When k = 0.64 then R8 = 390 Ω;
Z
bal = 130 Ω + (820 Ω//220 nF).
Zbal
Z line
-------------------------
line + R1
=
(2)
------------------------
Z
bal + R8
Z
The anti-sidetone network for the TEA1060 family shown
in Fig.4 attenuates the signal received from the line by
32 dB before it enters the receiving amplifier.
The attenuation is almost constant over the whole
audio-frequency range.
If fixed values are chosen for R1, R2, R3 and R9, then
condition (1) will always be fulfilled when |R8//Zbal| << R3.
To obtain optimum sidetone suppression, condition (2) has
to be fulfilled which results in:
Figure 5 shows a conventional Wheatstone bridge
anti-sidetone circuit that can be used as an alternative.
Both bridge types can be used with either resistive or
complex set impedances. (More information on the
balancing of anti-sidetone bridges can be obtained in our
publication “Applications Handbook for Wired telecom
systems, IC03b”, order number 9397 750 00811.)
R8
R1
Z bal
=
× Z
= k × Zline
line
-------
R8
-------
R1
Where k is a scale factor; k =
The scale factor k, dependent on the value of R8, is
chosen to meet the following criteria:
• compatibility with a standard capacitor from the E6 or
E12 range for Zbal
•
Zbal//R8 << R3 fulfilling condition (a) and thus
ensuring correct anti-sidetone bridge operation
•
Zbal + R8 >> R9 to avoid influencing the transmit gain.
In practise Zline varies considerably with the line type and
length. The value chosen for Zbal should therefore be for
an average line length thus giving optimum setting for
short or long lines.
1997 Sep 03
7
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
LN
R1
R2
Z
line
IR
i
m
V
R
EE
t
R3
Z
R9
R8
bal
SLPE
MSA500 - 1
Fig.4 Equivalent circuit of TEA1060 family anti-sidetone bridge.
LN
o
Z
R1
bal
Z
line
IR
i
m
V
R
EE
t
R9
R8
R
A
SLPE
MSA501 - 1
Fig.5 Equivalent circuit of an anti-sidetone network in a Wheatstone bridge configuration.
8
1997 Sep 03
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VLN
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
positive continuous line voltage
−
−
12
V
VLN(R)
repetitive line voltage during switch-on
or line interruption
13.2
V
VLN(RM)
repetitive peak line voltage for a 1 ms
pulse per 5 s
R9 = 20 Ω; R10 = 13 Ω;
see Fig.18
−
28
V
Iline
VI
line current
R9 = 20 Ω; note 1
−
−
−
140
mA
V
input voltage on all other pins
positive input voltage
negative input voltage
R9 = 20 Ω; note 2
VCC + 0.7
−0.7
V
Ptot
total power dissipation
TEA1062; TEA1062A
−
−
−
666
617
454
+75
+125
125
mW
mW
mW
°C
TEA1062M1; TEA1062AM1
TEA1062T; TEA1062AT
operating ambient temperature
storage temperature
Tamb
Tstg
Tj
−25
−40
−
°C
junction temperature
°C
Notes
1. Mostly dependent on the maximum required Tamb and on the voltage between LN and SLPE (see Figs 6, 7 and 8).
2. Calculated for the maximum ambient temperature specified (Tamb = 75 °C) and a maximum junction temperature of
125 °C.
HANDLING
This device meets class 2 ESD test requirements [Human Body Model (HBM)], in accordance with
“MIL STD 883C - method 3015”.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-a
thermal resistance from junction to ambient in free air
TEA1062; TEA1062A
75
81
K/W
K/W
K/W
TEA1062M1; TEA1062AM1
TEA1062T; TEA1062AT (note 1)
110
Note
1. Mounted on glass epoxy board 28.5 × 19.1 × 1.5 mm.
1997 Sep 03
9
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
MLC200
MLC201
150
150
handbook, halfpage
handbook, halfpage
I
I
LN
LN
(mA)
130
(mA)
130
(1)
110
90
110
90
(1)
(2)
(2)
(3)
(4)
(3)
(4)
70
70
50
30
50
30
2
2
4
6
8
10
12
4
6
8
10
12
V
(V)
V
(V)
V
V
LN
SLPE
LN
SLPE
(1) Tamb = 45 °C; Ptot = 1068 mW.
(2) Tamb = 55 °C; Ptot = 934 mW.
(3) Tamb = 65 °C; Ptot = 800 mW.
(4) Tamb = 75 °C; Ptot = 666 mW.
(1) Tamb = 45 °C; Ptot = 988 mW.
(2) Tamb = 55 °C; Ptot = 864 mW.
(3) Tamb = 65 °C; Ptot = 741 mW.
(4) Tamb = 75 °C; Ptot = 617 mW.
Fig.6 TEA1062 and TEA1062A safe operating
area.
Fig.7 TEA1062M1 and TEA1062AM1 safe
operating area.
MLC202
150
handbook, halfpage
I
LN
(mA)
130
110
90
(1)
(2)
(3)
(4)
70
50
30
2
4
6
8
10
12
V
(V)
V
LN
SLPE
(1) Tamb = 45 °C; Ptot = 727 mW.
(2) Tamb = 55 °C; Ptot = 636 mW.
(3) Tamb = 65 °C; Ptot = 545 mW.
(4) Tamb = 75 °C; Ptot = 454 mW.
Fig.8 TEA1062T and TEA1062AT safe operating
area.
1997 Sep 03
10
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
CHARACTERISTICS
Iline = 11 to 140 mA; VEE = 0 V; f = 800 Hz; Tamb = 25 °C; unless otherwise specified.
SYMBOL
Supplies LN and VCC (pins 1 and 13)
VLN voltage drop over circuit between LN
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
MIC inputs open-circuit
and VEE
I
line = 1 mA
−
1.6
1.9
4.0
5.7
−
−
V
Iline = 4 mA
−
−
V
Iline = 15 mA
3.55
4.9
−
4.25
6.5
7.5
−
V
I
I
line = 100 mA
line = 140 mA
V
V
∆VLN/∆T variation with temperature
Iline = 15 mA
Iline = 15 mA
−
−0.3
mV/K
VLN
voltage drop over circuit between LN
and VEE with external resistor RVA
R
VA (LN to REG) = 68 kΩ
−
3.5
4.5
0.9
−
V
RVA (REG to SLPE) = 39 kΩ −
−
V
ICC
supply current
VCC = 2.8 V
−
1.35
mA
VCC
supply voltage available for peripheral
circuitry
Iline = 15 mA; MUTE = HIGH
TEA1062
Ip = 1.2 mA
2.2
2.7
3.4
−
−
V
V
Ip = 0 mA
−
VCC
supply voltage available for peripheral
circuitry
Iline = 15 mA; MUTE = LOW
TEA1062A
Ip = 1.2 mA
Ip = 0 mA
2.2
2.7
3.4
−
−
V
V
−
Microphone inputs MIC− and MIC+ (pins 6 and 7)
Zi
input impedance
differential
between MIC− and MIC+
MIC− or MIC+ to VEE
−
64
−
kΩ
kΩ
dB
dB
dB
single-ended
−
32
−
CMRR
Gv
common mode rejection ratio
voltage gain MIC+ or MIC− to LN
−
82
−
Iline = 15 mA; R7 = 68 kΩ
50.5
−
52.0
±0.2
53.5
−
∆Gvf
gain variation with frequency
referenced to 800 Hz
f = 300 and 3400 Hz
∆GvT
gain variation with temperature
without R6; Iline = 50 mA;
−
±0.2
−
dB
referenced to 25 °C
Tamb = −25 and +75 °C
DTMF input (pin 11)
|Zi|
input impedance
−
20.7
25.5
±0.2
−
kΩ
dB
dB
Gv
voltage gain from DTMF to LN
Iline = 15 mA; R7 = 68 kΩ
24.0
−
27.0
−
∆Gvf
gain variation with frequency
referenced to 800 Hz
f = 300 and 3400 Hz
∆GvT
gain variation with temperature
Iline = 50 mA;
−
±0.2
−
dB
referenced to 25 °C
Tamb = −25 and +75 °C
1997 Sep 03
11
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Gain adjustment inputs GAS1 and GAS2 (pins 2 and 3)
∆Gv
transmitting amplifier gain variation by
adjustment of R7 between
GAS1 and GAS2
−8
−
0
dB
Sending amplifier output LN (pin 1)
VLN(rms)
output voltage (RMS value)
THD = 10%
I
I
line = 4 mA
line = 15 mA
−
0.8
2.3
−69
−
−
−
V
1.7
−
V
Vno(rms)
noise output voltage (RMS value)
Iline = 15 mA; R7 = 68 kΩ;
200 Ω between MIC− and
MIC+; psophometrically
weighted (P53 curve)
dBmp
Receiving amplifier input IR (pin 10)
Zi input impedance
Receiving amplifier output QR (pin 4)
−
21
−
kΩ
Zo
Gv
output impedance
−
4
−
Ω
voltage gain from IR to QR
Iline = 15 mA; RL = 300 Ω
29.5
31
32.5
dB
(from pin 9 to pin 4)
∆Gvf
gain variation with frequency
referenced to 800 Hz
f = 300 and 3400 Hz
−
−
±0.2
±0.2
−
−
dB
dB
∆GvT
Vo(rms)
gain variation with temperature
referenced to 25 °C
without R6; Iline = 50 mA;
Tamb = −25 and +75 °C
output voltage (RMS value)
THD = 2%; sine wave drive;
R4 = 100 kΩ; Iline = 15 mA;
Ip = 0 mA
RL = 150 Ω
RL = 450 Ω
0.22
0.3
−
0.33
0.48
15
−
−
−
V
V
Vo(rms)
output voltage (RMS value)
THD = 10%; R4 = 100 kΩ;
RL = 150 Ω; Iline = 4 mA
mV
Vno(rms)
noise output voltage (RMS value)
Iline = 15 mA; R4 = 100 kΩ;
IR open-circuit
−
50
−
µV
psophometrically weighted
(P53 curve); RL = 300 Ω
Gain adjustment input GAR (pin 5)
∆Gv receiving amplifier gain variation by
adjustment of R4 between GAR and QR
Mute input (pin 12)
−11
−
0
dB
VIH
HIGH level input voltage
1.5
−
−
−
8
VCC
0.3
15
V
VIL
LOW level input voltage
input current
V
IMUTE
−
µA
1997 Sep 03
12
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Reduction of gain
∆Gv
MIC+ or MIC− to LN
TEA1062
MUTE = HIGH
−
70
70
−
−
dB
dB
TEA1062A
MUTE = LOW
−
Gv
voltage gain from DTMF to QR
TEA1062
R4 = 100 kΩ; RL = 300 Ω
MUTE = HIGH
−
−
−17
−17
−
−
dB
dB
TEA1062A
MUTE = LOW
Automatic gain control input AGC (pin 15)
∆Gv
controlling the gain from IR to QR
R6 = 110 kΩ
and the gain from MIC+, MIC− to LN
(between AGC and VEE
Iline = 70 mA
)
gain control range
−
−
−
−5.8
23
−
−
−
dB
IlineH
IlineL
highest line current for maximum gain
lowest line current for minimum gain
mA
mA
61
R
I
line
line
0.5 mA
R1
I
I
CC
SLPE
LN
V
TEA1062
CC
TEA1062A
R
I
p
exch
DC
AC
0.5 mA
peripheral
circuits
C1
V
exch
V
REG
C3
STAB
SLPE
R9
EE
I
SLPE
R5
MBA357 - 1
Fig.9 Supply arrangement.
1997 Sep 03
13
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
MSA504
2.4
handbook, halfpage
(1)
I
p
(mA)
(2)
1.6
0.8
0
0
1
2
3
4
V
(V)
CC
The supply possibilities can be increased by setting the voltage drop over the circuit VLN to a higher value by resistor RVA connected between REG and
SLPE.
VCC > 2.2 V; Iline = 15 mA at VLN = 4 V; R1 = 620 Ω; R9 = 20 Ω.
(1) Ip = 2.1 mA. Is valid when the receiving amplifier is not driven or when MUTE = HIGH (TEA1062), MUTE = LOW (TEA1062A).
(2) Ip = 1.7 mA. Is valid when MUTE = LOW (TEA1062), MUTE = HIGH (TEA1062A) and the receiving amplifier is driven; Vo(rms) = 150 mV,
RL = 150 Ω.
Fig.10 Typical current Ip available from VCC for peripheral circuitry.
1997 Sep 03
14
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
a
13
V
7
CC
MIC
6
7
7
MIC
MIC
(1)
6
MIC
6
MIC
MIC
V
EE
9
MSA505
(a)
(b)
(c)
(a) Magnetic or dynamic microphone.
(b) Electret microphone.
(c) Piezoelectric microphone.
(1) Resistor may be connected to reduce the terminating impedance.
Fig.11 Alternative microphone arrangements.
h
(1)
4
(2)
4
4
9
QR
EE
QR
QR
9
9
V
V
V
EE
EE
MSA506
(a)
(b)
(c)
(a) Dynamic earpiece.
(b) Magnetic earpiece.
(c) Piezoelectric earpiece.
(1) Resistor may be connected to prevent distortion (inductive load).
(2) Resistor is required to increase the phase margin (capacitive load).
Fig.12 Alternative receiver arrangements.
15
1997 Sep 03
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
0
MSA507 - 1
R6 = ∞
∆G
v
(dB)
2
4
78.7 kΩ 110 kΩ 140 kΩ
6
0
20
40
60
80
100
120
140
(mA)
I
line
R9 = 20 Ω.
Fig.13 Variation of gain as a function of line current with R6 as a parameter.
Table 1 Values of resistor R6 for optimum line-loss compensation at various values of exchange supply voltage
(Vexch) and exchange feeding bridge resistance (Rexch); R9 = 20 Ω.
R6 (kΩ)
Vexch (V)
Rexch = 400 Ω
Rexch = 600 Ω
Rexch = 800 Ω
Rexch = 1000 Ω
36
48
60
100
140
−
78.7
110
−
−
−
93.1
120
82
102
1997 Sep 03
16
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
I
R1
line
620 Ω
13
1
LN
10
7
V
CC
100 µF
IR
V
R
600 Ω
o
L
MIC
4
QR
V
i
C4
100 pF
6
R4
100 kΩ
MIC
5
2
GAR
11
12
TEA1062
100 µF
DTMF
MUTE
C7 1 nF
C1
GAS1
10 to 140 mA
C8
1 nF
R7
68 kΩ
10 µF
3
C6
GAS2
V
i
100 pF
V
EE REG AGC STAB SLPE
9
14
15
8
16
C3
4.7
µF
R5
3.6
kΩ
R9
20 Ω
R6
MSA508
Voltage gain is defined as Gv = 20 log Vo/Vi .
For measuring gain from MIC+ and MIC− the MUTE input should be LOW or open-circuit.
For measuring the DTMF input, the MUTE input should be HIGH.
Inputs not being tested should be open-circuit.
Fig.14 Test circuit for defining TEA1062 voltage gain of MIC+, MIC− and DTMF inputs.
1997 Sep 03
17
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
I
R1
line
620 Ω
13
1
LN
10
7
V
CC
100 µF
IR
V
R
600 Ω
o
L
MIC
4
QR
V
i
C4
100 pF
6
R4
100 kΩ
MIC
5
2
GAR
TEA1062A
11
12
100 µF
DTMF
MUTE
C7 1 nF
C1
GAS1
10 to 140 mA
C8
1 nF
R7
68 kΩ
10 µF
3
C6
100 pF
GAS2
V
i
V
EE REG AGC STAB SLPE
9
16
14
15
8
C3
4.7
µF
R5
3.6
kΩ
R9
20 Ω
R6
MBA355
Voltage gain is defined as Gv = 20 log Vo/Vi .
For measuring gain from MIC+ and MIC− the MUTE input should be HIGH.
For measuring the DTMF input, the MUTE input should be LOW or open-circuit.
Inputs not being tested should be open-circuit.
Fig.15 Test circuit for defining TEA1062A voltage gain of MIC+, MIC− and DTMF inputs.
1997 Sep 03
18
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
I
R1
line
620 Ω
13
1
100 µF
600 Ω
LN
10
7
V
CC
IR
C2
Z
L
4
QR
MIC
V
o
10 µF
V
6
i
R4
100
C4
100 pF
MIC
kΩ
5
2
TEA1062
11
12
GAR
DTMF
MUTE
C7 1 nF
C1
100 µF
GAS1
10 to 140 mA
C8
1 nF
R7
3
C6
100 pF
GAS2
V
EE REG AGC STAB SLPE
9
14
15
8
16
C3
4.7
µF
R5
3.6
kΩ
R9
20 Ω
R6
MSA509
Voltage gain is defined as Gv = 20 log Vo/Vi .
Fig.16 Test circuit for defining TEA1062 voltage gain of the receiving amplifier.
I
R1
line
620 Ω
13
1
100 µF
LN
10
7
V
CC
IR
600 Ω
C2
Z
L
4
QR
MIC
V
o
10 µF
V
6
i
C4
100 pF
R4
100
MIC
kΩ
5
2
TEA1062A
11
12
GAR
DTMF
MUTE
C7 1 nF
C1
100 µF
GAS1
10 to 140 mA
C8
1 nF
R7
3
C6
100 pF
GAS2
V
EE REG AGC STAB SLPE
9
14
15
8
16
C3
4.7
µF
R5
3.6
kΩ
R9
20 Ω
R6
MBA356
Voltage gain is defined as Gv = 20 log Vo/Vi .
Fig.17 Test circuit for defining TEA1062A voltage gain of the receiving amplifier.
19
1997 Sep 03
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
APPLICATION INFORMATION
BMA35-81
a n f u l l p a g e w i d t h
A“paHnkWfirdcolety,smI3C0b”
1997 Sep 03
20
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
R1
620 Ω
V
LN
V
CC
DD
DTMF
TONE
cradle
contact
TEA1062
M1
PCD3310
MUTE
DP/FLO
V
V
EE
SS
telephone
line
BSN254A
MLC203
(a) DTMF pulse set with CMOS bilingual dialling circuit PCD3310. The dashed line shows an optional flash (register recall by timed loop break).
Fig.19 Typical simplified application of the TEA1062.
R1
620 Ω
V
LN
V
CC
DD
DTMF
TONE
cradle
contact
TEA1062A
M1
PCD3310T
DP/FLO
MUTE
V
V
EE
SS
telephone
line
BSN254A
MLC204
(a) DTMF pulse set with CMOS bilingual dialling circuit PCD3310T. The dashed line shows an optional flash (register recall by timed loop break).
Fig.20 Typical simplified application of the TEA1062A.
1997 Sep 03
21
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
max.
min.
max.
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
3.9
3.4
8.25
7.80
9.5
8.3
4.7
0.51
3.7
2.54
0.10
7.62
0.30
0.254
0.01
2.2
0.021
0.015
0.013
0.009
0.86
0.84
0.32
0.31
0.055
0.045
0.26
0.24
0.15
0.13
0.37
0.33
inches
0.19
0.020
0.15
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-10-02
95-01-19
SOT38-1
050G09
MO-001AE
1997 Sep 03
22
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.030
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-14
SOT38-4
1997 Sep 03
23
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-9
M
E
D
A
2
A
A
L
1
c
e
b
1
w M
Z
(e )
1
M
H
b
b
2
16
9
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
(1)
Z
A
min.
A
2
A
(1)
(1)
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
1
2
E
max.
max.
max.
1.65
1.40
0.51
0.41
1.14
0.76
0.36
0.20
19.30
18.80
6.45
6.24
3.81
2.92
8.23
7.62
9.40
8.38
4.32
0.17
0.38
3.56
2.54
0.10
7.62
0.30
0.254
0.01
0.76
0.065 0.020 0.045 0.014
0.055 0.016 0.030 0.008
0.76
0.74
0.254
0.246
0.150 0.324
0.115 0.300
0.37
0.33
inches
0.015
0.14
0.030
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-07-24
SOT38-9
1997 Sep 03
24
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT109-1
076E07S
MS-012AC
1997 Sep 03
25
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
SOLDERING
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Plastic dual in-line packages
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
Apply the soldering iron below the seating plane (or not
more than 2 mm above it). If its temperature is below
300 °C, it must not be in contact for more than 10 s; if
between 300 and 400 °C, for not more than 5 s.
Plastic small-outline packages
BY WAVE
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
1997 Sep 03
26
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Sep 03
27
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Belgium: see The Netherlands
Brazil: see South America
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 247 9145, Fax. +7 095 247 9144
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Colombia: see South America
Czech Republic: see Austria
Slovakia: see Austria
Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580/xxx
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417027/1200/05/pp28
Date of release: 1997 Sep 03
Document order number: 9397 750 02819
Go to Philips Semiconductors' home page
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Discrete semiconductors
Audio
TEA1062; TEA1062A; Low voltage transmission circuits with dialler interface
Clocks and Watches
Data communications
Microcontrollers
Peripherals
Standard analog
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Wired communications
Wireless communications
Description
Catalog by System
Automotive
Consumer Multimedia
Systems
Communications
The TEA1062 and TEA1062A are integrated circuits that perform all speech and line interface functions required in fully electronic
telephone sets. They perform electronic switching between dialling and speech. The ICs operate at line voltage down to 1.6 V DC (with
reduced performance) to facilitate the use of more telephone sets connected in parallel.
PC/PC-peripherals
Cross reference
All statements and values refer to all versions unless otherwise specified.
Models
Packages
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
Features
l Low DC line voltage; operates down to 1.6 V (excluding polarity guard)
l Voltage regulator with adjustable static resistance
l Provides a supply for external circuits
l Symmetrical high-impedance inputs (64 kW) for dynamic, magnetic or piezoelectric microphones
l Asymmetrical high-impedance input (32 kW) for electret microphones
l DTMF signal input with confidence tone
l Mute input for pulse or DTMF dialling
- TEA1062: active HIGH (MUTE)
- TEA1062A: active LOW (MUTE)
l Receiving amplifier for dynamic, magnetic or piezoelectric earpieces
l Large gain setting ranges on microphone and earpiece amplifiers
l Line loss compensation (line current dependent) for microphone and earpiece amplifiers
l Gain control curve adaptable to exchange supply
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TEA1062; TEA1062A
TEA1062; TEA1062A
l DC line voltage adjustment facility.
Datasheet
File
size
(kB)
Publication
release date Datasheet status
Page
count
Type nr.
Title
Datasheet
Download
TEA1062; TEA1062A Low voltage transmission circuits with 03-Sep-97
dialler interface
Product
Specification
28
211
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
TEA1062/C4
9350 787 40112 Standard Marking * Bulk Pack SOT38 Full production
9351 512 50112 Standard Marking * Bulk Pack SOT38 Full production
9350 792 30112 Standard Marking * Bulk Pack SOT38 Full production
9352 301 90112 Standard Marking * Bulk Pack SOT38 Full production
9350 832 20112 Standard Marking * Bulk Pack SOT109 Full production
Standard Marking * Reel Pack,
-
-
TEA1062/C4/M1
TEA1062A/C4
TEA1062A/C4/M1
TEA1062AT/C4
TEA1062AN
-
TEA1062ATD
TEA1062ATD-T
TEA1062TD
9350 832 20118
SOT109 Full production
SMD, 13"
TEA1062T/C4
9350 832 10112 Standard Marking * Bulk Pack SOT109 Full production
Standard Marking * Reel Pack,
SMD, 13"
TEA1062TD-T
9350 832 10118
SOT109 Full production
Please read information about some discontinued variants of this product.
Find similar products:
TEA1062; TEA1062A links to the similar products page containing an overview of products that are similar in function or related to
the part number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection
guides and products from the same functional category.
Copyright © 2000
Royal Philips Electronics
All rights reserved.
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