935219470512 [NXP]
ALVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56;型号: | 935219470512 |
厂家: | NXP |
描述: | ALVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
文件: | 总20页 (文件大小:114K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74ALVT16601
18-bit universal bus transceiver; 3-state
Rev. 03 — 5 July 2005
Product data sheet
1. General description
The 74ALVT16601 is a high-performance Bipolar Complementary Metal Oxide
Semiconductor (BiCMOS) product designed for VCC operation at 2.5 V and 3.3 V with I/O
compatibility up to 5 V. This device is an 18-bit universal transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. Data
flow in each direction is controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A-bus
data is latched if CPAB is held at a HIGH or LOW level. If LEAB is LOW, the A-bus data is
stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW,
the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state.
The clocks can be controlled with the clock enable inputs (CEAB and CEBA).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2. Features
■ 18-bit bidirectional bus interface
■ 5 V I/O compatible
■ 3-state buffers
■ Output capability: +64 mA and −32 mA
■ TTL input and output switching levels
■ Input and output interface capability to systems at 5 V supply
■ Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
■ Live insertion and extraction permitted
■ Power-up reset
■ Power-up 3-state
■ No bus current loading when output is tied to 5 V bus
■ Positive-edge triggered clock inputs
■ Latch-up protection:
◆ JESD78: exceeds 500 mA
■ ESD protection:
◆ MIL STD 883, method 3015: exceeds 2000 V
◆ Machine model: exceeds 200 V
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C.
Symbol Parameter
VCC = 2.5 V
Conditions
Min
Typ
Max Unit
tPLH
propagation delay An to Bn or
Bn to An
CL = 30 pF
CL = 30 pF
-
-
1.8
2.2
-
-
ns
ns
tPHL
propagation delay An to Bn or
Bn to An
Ci
input capacitance of control pins VI = 0 V or VCC
4
8
-
-
pF
pF
Cio
input/output capacitance of
I/O pins
VI/O = 0 V or VCC
outputs disabled
;
ICC
supply current
outputs disabled
-
40
-
µA
VCC = 3.3 V
tPLH propagation delay An to Bn or
CL = 50 pF
CL = 50 pF
-
-
1.9
2
-
-
ns
ns
Bn to An
tPHL
propagation delay An to Bn or
Bn to An
Ci
input capacitance of control pins VI = 0 V or VCC
4
8
-
-
pF
pF
Cio
input/output capacitance of
I/O pins
VI/O = 0 V or VCC
outputs disabled
;
ICC
supply current
outputs disabled
-
60
-
µA
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
74ALVT16601DL
−40 °C to +85 °C
SSOP56
plastic shrink small outline package; 56 leads; body
width 7.5 mm
SOT371-1
74ALVT16601DGG −40 °C to +85 °C
TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
SOT364-1
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
2 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
5. Functional diagram
1
EN1
G2
OEAB
CEAB
CPAB
LEAB
56
55
2
2C3
C3
G2
3
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A0
B0
27
29
30
28
EN4
G5
OEBA
CEBA
CPBA
LEBA
5
A1
B1
6
A2
B2
5C6
8
A3
B3
C6
G5
9
A4
B4
10
A5
B5
12
A6
3
54
B6
1
A0
3D
4
B0
13
A7
B7
6D
14
A8
B8
5
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A1
A2
B1
15
A9
B9
6
16
B2
A10
B10
B11
B12
B13
B14
B15
B16
B17
8
17
A3
B3
A11
9
19
A4
B4
A12
20
10
12
13
14
15
16
17
19
20
21
23
24
26
A13
A5
B5
21
A14
A6
B6
23
A15
A7
B7
24
A16
A8
B8
26
A17
A9
B9
A10
A11
A12
A13
A14
A15
A16
A17
B10
B11
B12
B13
B14
B15
B16
B17
1
2 55 56 29 30 28 27
OEBA
LEBA
CPBA
OEAB
LEAB
CPAB
CEAB
CEBA
001aad316
001aad317
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
3 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
1
OEAB
CEAB
CPAB
LEAB
LEBA
CPBA
CEBA
OEBA
A0
56
55
2
28
30
29
27
3
CE
ID
54
B0
C1
CLK
CE
ID
C1
CLK
001aad249
to 17 other channels
Fig 3. Logic diagram
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
4 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
6. Pinning information
6.1 Pinning
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A0
CEAB
CPAB
B0
2
3
4
GND
A1
GND
B1
5
6
A2
B2
7
V
CC
V
CC
8
A3
B3
9
A4
A5
B4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
B5
GND
A6
GND
B6
A7
B7
A8
B8
16601
A9
B9
A10
A11
GND
A12
A13
A14
B10
B11
GND
B12
B13
B14
V
CC
V
CC
A15
A16
B15
B16
GND
A17
GND
B17
OEBA
LEBA
CPBA
CEBA
001aad247
Fig 4. Pin configuration
6.2 Pin description
Table 3:
Symbol
OEAB
LEAB
A0
Pin description
Pin
1
Description
A-to-B output enable input (active LOW)
A-to-B latch enable input
data input or output (A side)
ground (0 V)
2
3
GND
A1
4
5
data input or output (A side)
data input or output (A side)
voltage supply
A2
6
VCC
7
A3
8
data input or output (A side)
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
5 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
Table 3:
Symbol
A4
Pin description …continued
Pin
9
Description
data input or output (A side)
A5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
data input or output (A side)
ground (0 V)
GND
A6
data input or output (A side)
data input or output (A side)
data input or output (A side)
data input or output (A side)
data input or output (A side)
data input or output (A side)
ground (0 V)
A7
A8
A9
A10
A11
GND
A12
A13
A14
VCC
A15
A16
GND
A17
OEBA
LEBA
CEBA
CPBA
B17
GND
B16
B15
VCC
B14
B13
B12
GND
B11
B10
B9
data input or output (A side)
data input or output (A side)
data input or output (A side)
voltage supply
data input or output (A side)
data input or output (A side)
ground (0 V)
data input or output (A side)
B-to-A output enable input (active LOW)
B-to-A latch enable input
B-to-A clock enable (active LOW)
B-to-A clock input (active rising edge)
data input or output (B side)
ground (0 V)
data input or output (B side)
data input or output (B side)
voltage supply
data input or output (B side)
data input or output (B side)
data input or output (B side)
ground (0 V)
data input or output (B side)
data input or output (B side)
data input or output (B side)
data input or output (B side)
data input or output (B side)
data input or output (B side)
ground (0 V)
B8
B7
B6
GND
B5
data input or output (B side)
data input or output (B side)
data input or output (B side)
B4
B3
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
6 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
Table 3:
Symbol
VCC
Pin description …continued
Pin
50
51
52
53
54
55
56
Description
voltage supply
B2
data input or output (B side)
data input or output (B side)
ground (0 V)
B1
GND
B0
data input or output (B side)
A-to-B clock input (active rising edge)
A-to-B clock enable (active LOW)
CPAB
CEAB
7. Functional description
7.1 Function table
[1]
Table 4:
Control
CEAB
CEBA
X
Function table
Input
Output
Bn
An
Z
OEAB
OEBA
H
LEAB
LEBA
X
CPAB
CPBA
X
An
Bn
X
X
L
H
X
L
L
H
L
H
L
L
H
L
L
L
L
L
L
↑
L
H
X
H
H
L
Y[2]
Y[3]
Y[2]
X
X
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition
[2] Output level before the indicated steady-state input conditions were established.
[3] Output level before the indicated steady-state input conditions were established, provided that CPAB or
CPBA was LOW before LEAB or LEBA went LOW.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
−0.5
−0.5
Max
+4.6
+7.0
+7.0
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
[1]
[1]
V
VO
output in OFF-state or
HIGH-state
V
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
7 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
Table 5:
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
−50
−50
128
−64
+150
150
Unit
mA
mA
mA
mA
°C
IIK
IOK
IO
input diode current
VI < 0 V
-
output diode current
output current
VO < 0 V
-
output in LOW-state
output in HIGH-state
-
-
Tstg
Tj
storage temperature
junction temperature
−65
[2]
-
°C
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability.
9. Recommended operating conditions
Table 6:
Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max Unit
VCC = 2.5 V ± 0.2 V
VCC
VI
supply voltage
2.3
-
-
-
-
-
-
-
2.7
5.5
-
V
input voltage
0
V
VIH
VIL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
1.7
V
-
-
-
-
0.7
−8
8
V
mA
mA
mA
LOW-level output current none
current duty cycle ≤ 50 %;
24
f ≥ 1 kHz
∆t/∆V
input transition rise or fall outputs enabled
rate
-
-
-
10
ns/V
Tamb
ambient temperature
−40
+85
°C
VCC = 3.3 V ± 0.3 V
VCC
VI
supply voltage
3.0
-
-
-
-
-
-
-
3.6
5.5
-
V
input voltage
0
V
VIH
VIL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current none
2.0
V
-
-
-
-
0.8
−32
32
64
V
mA
mA
mA
current duty cycle ≤ 50 %;
f ≥ 1 kHz
∆t/∆V
input transition rise or fall outputs enabled
rate
-
-
-
10
ns/V
Tamb
ambient temperature
in free air
−40
+85
°C
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
8 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
10. Static characteristics
Table 7:
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
amb = −40 °C to +85 °C.
Static characteristics
T
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.5 V ± 0.2 V[1]
VIK
input diode voltage
VCC = 2.3 V; IIK = −18 mA
-
−0.85 −1.2
V
V
VOH
HIGH-level output voltage
VCC = 2.3 V to 3.6 V; IOH = −100 µA
VCC
0.2
−
-
VCC = 2.3 V; IOH = −8 mA
VCC = 2.3 V; IOL = 100 µA
VCC = 2.3 V; IOL = 24 mA
VCC = 2.3 V; IOL = 8 mA
1.8
-
V
V
V
V
V
VOL
LOW-level output voltage
-
-
-
-
0.07
0.2
0.5
0.3
-
-
0.4
[2]
VRST
ILI
power-up LOW-state output voltage VCC = 2.7 V; IO = 1 mA;
VI = VCC or GND
0.55
input leakage current
control pins
VCC = 2.7 V; VI = VCC or GND
VCC = 0 V or 2.7 V; VI = 5.5 V
VCC = 0 V or 2.7 V; VI = 5.5 V
VCC = 2.7 V; VI = VCC
-
0.1
0.1
0.1
0.1
+0.1
0.1
90
±1
10
20
10
−5
µA
µA
µA
µA
µA
[3]
[3]
[3]
I/O data pins
-
-
-
-
-
-
-
VCC = 2.7 V; VI = 0 V
IOFF
power-down leakage current
bus hold current data inputs
VCC = 0 V; VI or VO = 0 V to 4.5 V
VCC = 2.3 V; VI = 0.7 V
±100 µA
[4]
[4]
IHOLD
-
µA
µA
µA
VCC = 2.3 V; VI = 1.7 V
−75
10
-
IEX
external current into output
output in HIGH-state when VO > VCC
VO = 5.5 V; VCC = 2.3 V
;
125
[5]
IPU, IPD power-up/down 3-state output
current
V
CC ≤ 1.2 V; VO = 0.5 V to VCC
;
-
1
100
µA
VI = GND or VCC; OEAB or OEAB
don’t care
ICC
supply current
VCC = 2.7 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state
-
-
-
-
0.04
2.5
0.1
4.5
0.1
0.4
mA
mA
mA
mA
outputs LOW-state
[6]
[7]
outputs disabled
0.04
0.01
∆ICC
additional supply current per input VCC = 2.3 V to 2.7 V; one input at
pin
VCC − 0.6 V, other inputs at
VCC or GND
Ci
input capacitance of control pins
VI = 0 V or VCC
4
8
-
-
pF
pF
Cio
input/output capacitance of I/O pins VI/O = 0 V or VCC; outputs disabled
VCC = 3.3 V ± 0.3 V[8]
VIK
input diode voltage
HIGH-level output voltage
VCC = 3.0 V; IIK = −18 mA
-
−0.85 −1.2
V
V
VOH
VCC = 3.0 V to 3.6 V; IOH = −100 µA
VCC
0.2
−
VCC
-
VCC = 3.0 V; IOH = −32 mA
2.0
2.3
-
V
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
9 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
Table 7:
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
amb = −40 °C to +85 °C.
Static characteristics …continued
T
Symbol Parameter
Conditions
Min
Typ
0.07
0.25
0.3
0.4
-
Max
0.2
Unit
V
VOL
LOW-level output voltage
VCC = 3.0 V; IOL = 100 µA
VCC = 3.0 V; IOL = 16 mA
VCC = 3.0 V; IOL = 32 mA
VCC = 3.0 V; IOL = 64 mA
-
-
-
-
-
0.4
V
0.5
V
0.55
0.55
V
[2]
VRST
ILI
power-up LOW-state output voltage VCC = 2.7 V; IO = 1 mA;
VI = VCC or GND
V
input leakage current
control pins
VCC = 3.6 V; VI = VCC or GND
VCC = 0 V or 3.6 V; VI = 5.5 V
VCC = 3.6 V; VI = 5.5 V
-
0.1
0.1
0.1
0.5
+0.1
0.1
130
−140
-
±1
10
20
10
−5
µA
µA
µA
µA
µA
-
[3]
[3]
[3]
I/O data pins
-
VCC = 3.6 V; VI = VCC
-
VCC = 3.6 V; VI = 0 V
-
IOFF
power-down leakage current
bus hold current data inputs
VCC = 0 V; VI or VO = 0 V to 4.5 V
VCC = 3 V; VI = 0.8 V
-
±100 µA
[9]
[9]
[9]
IHOLD
75
-
µA
µA
µA
µA
VCC = 3 V; VI = 2.0 V
−75
±500
-
-
VCC = 0 V to 3.6 V; VCC = 3.6 V
-
IEX
external current into output
output in HIGH-state when VO > VCC
VO = 5.5 V; VCC = 2.3 V
;
10
125
[10]
IPU, IPD power-up/down 3-state output
current
V
CC ≤ 1.2 V; VO = 0.5 V to VCC
;
-
1
±100 µA
VI = GND or VCC; OEAB or OEAB
don’t care
ICC
supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state
-
-
-
-
0.06
3.5
0.1
5
mA
mA
mA
mA
outputs LOW-state
[6]
[7]
outputs disabled
0.06
0.04
0.1
0.4
∆ICC
additional supply current per input VCC = 3 V to 3.6 V; one input at
pin
VCC − 0.6 V, other inputs at
VCC or GND
Ci
input capacitance of control pins
VI = 0 V or VCC
4
8
-
-
pF
pF
Cio
input/output capacitance of I/O pins VI/O = 0 V or VCC; outputs disabled
[1] All typical values are at VCC = 2.5 V and Tamb = 25 °C.
[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3] Unused pins at VCC or GND.
[4] Not guaranteed.
[5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[6] ICC is measured with outputs pulled up to VCC or pulled down to ground.
[7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
[8] All typical values are at VCC = 3.3 V and Tamb = 25 °C.
[9] This is the bus hold overdrive current required to force the input to the opposite logic state.
[10] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
10 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
11. Dynamic characteristics
Table 8:
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
amb = −40 °C to +85 °C.
Dynamic characteristics
T
Symbol Parameter
Conditions
Min
Typ
Max Unit
VCC = 2.5 V ± 0.2 V[1]; CL = 30 pF
tPHL
propagation delay
An to Bn or Bn to An
see Figure 5
see Figure 6
see Figure 7
1.4
1.5
1.9
2.2
2.5
3.2
3.5
4.0
5.2
ns
ns
ns
LEAB to Bn or LEBA to An
CPAB to Bn or CPBA to An
propagation delay
tPLH
An to Bn or Bn to An
see Figure 5
see Figure 6
see Figure 7
see Figure 9
see Figure 10
see Figure 9
see Figure 10
1.0
1.5
2.2
2.2
1.6
2.3
1.9
1.8
2.5
3.5
3.1
2.3
3.6
2.9
3.0
4.0
5.0
4.4
3.4
4.8
4.4
ns
ns
ns
ns
ns
ns
ns
LEAB to Bn or LEBA to An
CPAB to Bn or CPBA to An
output disable time from HIGH-level
output disable time from LOW-level
output enable time to HIGH-level
output enable time to LOW-level
hold time HIGH
tPHZ
tPLZ
tPZH
tPZL
th(H)
An to CPAB or Bn to CPBA
An to LEAB or Bn to LEAB
CEAB to CPAB or CEBA to CPBA
hold time LOW
see Figure 8
see Figure 8
see Figure 8
0.0
1.5
2.0
−1.1
0.4
-
-
-
ns
ns
ns
0.4
th(L)
An to CPAB or Bn to CPBA
An to LEAB or Bn to LEAB
CEAB to CPAB or CEBA to CPBA
set-up time HIGH
see Figure 8
see Figure 8
see Figure 8
0.0
1.9
−0.3
-
-
-
ns
ns
ns
1.0
+0.8 −0.1
tsu(H)
An to CPAB or Bn to CPBA
An to LEAB or Bn to LEBA
CEAB to CPAB or CEBA to CPBA
set-up time LOW
see Figure 8
see Figure 8
see Figure 8
2.0
0.0
0.7
0.4
-
-
-
ns
ns
ns
−1.0
0.3
tsu(L)
An to CPAB or Bn to CPBA
An to LEAB or Bn to LEBA
CEAB to CPAB or CEBA to CPBA
pulse width HIGH
see Figure 8
see Figure 8
see Figure 8
2.0
1.5
1.2
0.4
-
-
-
ns
ns
ns
+0.3 −0.4
tWH
CPAB or CPBA
see Figure 7
see Figure 6
3.0
1.5
-
-
-
-
ns
ns
LEAB or LEBA
tWL
pulse width LOW
CPAB or CPBA
see Figure 7
3.0
-
-
ns
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
11 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
Table 8:
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
T
amb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min
Typ
Max Unit
VCC = 3.3 V ± 0.3 V[2]; CL = 50 pF
tPHL
propagation delay
An to Bn or Bn to An
see Figure 5
see Figure 6
see Figure 7
1.1
1.4
1.7
2.0
2.3
2.7
2.8
3.6
4.1
ns
ns
ns
LEAB to Bn or LEBA to An
CPAB to Bn or CPBA to An
propagation delay
tPLH
An to Bn or Bn to An
see Figure 5
see Figure 6
see Figure 7
see Figure 9
see Figure 10
see Figure 9
see Figure 10
1.2
1.5
2.1
2.7
2.1
2.2
1.6
1.9
2.5
3.1
3.6
2.8
3.2
2.5
2.9
3.8
4.5
4.9
4
ns
ns
ns
ns
ns
ns
ns
LEAB to Bn or LEBA to An
CPAB to Bn or CPBA to An
output disable time from HIGH-level
output disable time from LOW-level
output enable time to HIGH-level
output enable time to LOW-level
hold time HIGH
tPHZ
tPLZ
tPZH
tPZL
th(H)
4.2
3.8
An to CPAB or Bn to CPBA
An to LEAB or Bn to LEAB
CEAB to CPAB or CEBA to CPBA
hold time LOW
see Figure 8
see Figure 8
see Figure 8
+1.0 −0.5
-
-
-
ns
ns
ns
1.5
1.5
0.1
0.7
th(L)
An to CPAB or Bn to CPBA
An to LEAB or Bn to LEAB
CEAB to CPAB or CEBA to CPBA
set-up time HIGH
see Figure 8
see Figure 8
see Figure 8
+1.0 −0.3
1.5 0.5
+1.0 −0.3
-
-
-
ns
ns
ns
tsu(H)
An to CPAB or Bn to CPBA
An to LEAB or Bn to LEBA
CEAB to CPAB or CEBA to CPBA
set-up time LOW
see Figure 8
see Figure 8
see Figure 8
1.5
0.4
-
-
-
ns
ns
ns
+1.0 −0.5
1.5
1.5
0.3
0.6
tsu(L)
An to CPAB or Bn to CPBA
An to LEAB or Bn to LEBA
CEAB to CPAB or CEBA to CPBA
pulse width HIGH
see Figure 8
see Figure 8
see Figure 8
-
-
-
ns
ns
ns
+1.0 −0.1
1.0
−0.4
tWH
CPAB or CPBA
see Figure 7
see Figure 6
2.0
1.5
-
-
-
-
ns
ns
LEAB or LEBA
tWL
pulse width LOW
CPAB or CPBA
see Figure 7
2.0
-
-
ns
[1] All typical values are measured at VCC = 2.5 V and Tamb = 25 °C.
[2] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
12 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
12. Waveforms
V
I
input
An or Bn
V
V
M
M
t
0 V
t
PLH
PHL
V
OH
output
Bn or An
V
V
M
M
V
OL
001aad308
Measurement points are given in Table 9.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 5. Propagation delay input (An, Bn) to output (Bn, An) in transparent mode
V
I
input LEAB
or LEBA
V
V
V
M
M
M
0 V
t
WH
t
t
PLH
PHL
V
OH
output
An or Bn
V
V
M
M
V
OL
001aad310
Measurement points are given in Table 9.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable
(LEAB, LEBA) pulse width
1/f
max
V
V
I
input CPBA
or CPAB
V
V
M
M
M
0 V
t
t
WL
WH
t
t
PLH
PHL
V
OH
output
An or Bn
V
V
M
M
V
OL
001aad254
Measurement points are given in Table 9.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 7. Propagation delay clock input (CPAB, CPBA) to output (An, Bn), clock pulse width
(CPAB, CPBA) and maximum clock frequency (CPAB, CPBA)
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
13 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
V
I
input
LEAB or LEBA,
CPAB or CPBA
V
M
V
M
0 V
t
t
t
t
h(L)
su(H)
h(H)
su(L)
V
I
input An, Bn,
CEAB, CEBA
V
V
V
V
M
M
M
M
0 V
001aad255
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 8. Data set-up and hold times
V
I
input OEBA
or OEAB
V
V
M
M
t
0 V
t
PZH
PHZ
V
OH
V
Y
output
An or Bn
V
M
0 V
001aad309
Measurement points are given in Table 9.
VOH is typical voltage output drop that occur with the output load.
Fig 9. 3-state output enable time to HIGH-level and output disable time from HIGH-level
V
I
input OEBA
or OEAB
V
V
M
M
t
0 V
t
PZL
PLZ
3.0 V or V
CC
output
An or Bn
V
M
V
X
V
OL
001aad311
Measurement points are given in Table 9.
VOL is typical voltage output drop that occur with the output load.
Fig 10. 3-state output enable time to LOW-level and output disable time from LOW-level
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
14 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
Table 9:
Measurement points
Supply voltage
Input
VM
Output
VM
VX
VY
≥ 3 V
1.5 V
1.5 V
VOL + 0.3 V
VOL + 0.15 V
V
OH − 0.3 V
OH − 0.15 V
≤ 2.7 V
0.5 × VCC
0.5 × VCC
V
t
W
V
I
90 %
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
(t )
f
t
(t )
TLH r
THL
t
(t )
t
(t )
THL f
TLH
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
10 %
0 V
t
W
001aac221
Measurement points are given in Table 9.
a. Input pulse definition
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
C
L
R
L
R
T
mna616
Test data is given in Table 10.
Definitions test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
b. Test circuit
Fig 11. Load circuitry for switching times
Table 10: Test data
Input
Load
CL
VEXT
VI
fi
tW
tr, tf
RL
tPLZ, tPZL tPLH, tPHL tPHZ, tPZH
3.0 V or VCC
whichever is
less
≤ 10 MHz 500 ns ≤ 2.5 ns 30 pF 500 Ω 6 V or
open
GND
or
2 × VCC
50 pF
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
15 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
13. Package outline
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
D
E
A
X
c
y
H
v
M
A
E
Z
29
56
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
28
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 18.55
0.13 18.30
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT371-1
MO-118
Fig 12. Package outline SOT371-1 (SSOP56)
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
16 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
H
v
M
A
y
E
Z
56
29
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
28
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.5
0.1
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT364-1
MO-153
Fig 13. Package outline SOT364-1 (TSSOP56)
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
17 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
14. Revision history
Table 11: Revision history
Document ID
74ALVT16601_3
Modifications:
Release date Data sheet status
20050705 Product data sheet
Change notice Doc. number
Supersedes
-
-
74ALVT16601_2
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Section 2 “Features”: modified ‘JEDEC Std 17’ into ‘JESD78’.
• Table 8 “Dynamic characteristics”: changed values of propagation delay, output enable and
output disable time.
74ALVT16601_2
74ALVT16601_1
19980213
-
Product specification
-
-
-
9397 750 03571 74ALVT16601_1
-
-
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
18 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
16. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Trademarks
Notice — All referenced brands, product names, service names and
17. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74ALVT16601_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 5 July 2005
19 of 20
74ALVT16601
Philips Semiconductors
18-bit universal bus transceiver; 3-state
20. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 7
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information . . . . . . . . . . . . . . . . . . . . 19
9
10
11
12
13
14
15
16
17
18
19
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 5 July 2005
Document number: 74ALVT16601_3
Published in The Netherlands
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