74HCT4052DB,118 [NXP]
74HC(T)4052 - Dual 4-channel analog multiplexer/demultiplexer SSOP1 16-Pin;
| 型号： | 74HCT4052DB,118 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)4052 - Dual 4-channel analog multiplexer/demultiplexer SSOP1 16-Pin 光电二极管 |
| 文件： | 总27页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Rev. 06 — 11 January 2010
Product data sheet
1. General description
The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4052; 74HCT4052 is a dual 4-channel analog multiplexer/demultiplexer with
common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to
nY3) and a common input/output (pin nZ). The common channel select logics include two
digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When
pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0
and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state,
independent of pins S0 and S1.
VCC and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E).
The VCC to GND ranges are 2.0 V to 10.0 V for the 74HC4052 and 4.5 V to 5.5 V for the
74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC − VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
2. Features
Wide analog input voltage range from −5 V to +5 V
Low ON resistance:
80 Ω (typical) at VCC − VEE = 4.5 V
70 Ω (typical) at VCC − VEE = 6.0 V
60 Ω (typical) at VCC − VEE = 9.0 V
Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals
Typical ‘break before make’ built-in
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC4052
74HC4052D
−40 °C to +125 °C
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
SOT338-1
74HC4052DB
SSOP16
plastic shrink small outline package; 16 leads; body
width 5.3 mm
74HC4052N
−40 °C to +125 °C
−40 °C to +125 °C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HC4052PW
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HC4052BQ
−40 °C to +125 °C
DHVQFN16 plastic dual-in line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
74HCT4052
74HCT4052D
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
SOT338-1
74HCT4052DB −40 °C to +125 °C
74HCT4052N −40 °C to +125 °C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HCT4052PW −40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT4052BQ −40 °C to +125 °C
DHVQFN16 plastic dual-in line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
5. Functional diagram
10
9
0
0
3
4 ×
1
13
G4
6
1Z
1Y0
12
14
15
11
1
MDX
10
9
S0
S1
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
0
1
2
3
1
5
3
2
4
5
12
14
15
2
13
6
E
4
2Z
3
11
001aah824
001aah825
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
2 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
nYn
V
CC
V
EE
V
CC
V
CC
V
CC
V
EE
V
EE
nZ
from
logic
mnb043
Fig 3. Schematic diagram (one switch)
V
DD
16
13
1Z
12
14
15
11
1
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
10
9
S0
S1
E
LOGIC
LEVEL
CONVERSION
1-OF-4
DECODER
6
5
2
4
3
2Y3
2Z
8
7
001aah872
V
SS
V
EE
Fig 4. Functional diagram
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
3 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
74HC4052
74HCT4052
74HC4052
74HCT4052
terminal 1
index area
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y0
2Y2
2Z
V
CC
1Y2
1Y1
1Z
2
3
4
5
6
7
15
14
13
12
11
10
2Y2
2Z
1Y2
1Y1
1Z
2Y3
2Y1
E
2Y3
2Y1
E
1Y0
1Y3
S0
1Y0
1Y3
S0
(1)
V
CC
V
EE
V
EE
GND
S1
001aah823
001aah822
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration for DIP16, SO16 and
(T)SSOP16
Fig 6. Pin configuration for DHVQFN16
6.2 Pin description
Table 2.
Symbol
2Y0
2Y2
2Z
Pin description
Pin
1
Description
independent input or output 2Y0
independent input or output 2Y2
common input or output 2
independent input or output 2Y3
independent input or output 2Y1
enable input (active LOW)
negative supply voltage
2
3
2Y3
2Y1
E
4
5
6
VEE
GND
S1
7
8
ground (0 V)
9
select logic input 1
S0
10
11
12
13
14
15
16
select logic input 0
1Y3
1Y0
1Z
independent input or output 1Y3
independent input or output 1Y0
common input or output 1
independent input or output 1Y1
independent input or output 1Y2
positive supply voltage
1Y1
1Y2
VCC
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
4 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
Table 3.
Function table[1]
Input
Channel on
E
L
L
L
L
H
S1
L
S0
L
nY0 and nZ
nY1 and nZ
nY2 and nZ
nY3 and nZ
none
L
H
L
H
H
X
H
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to VEE = GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+11.0
±20
±20
±25
±20
50
Unit
V
[1]
supply voltage
−0.5
input clamping current
switch clamping current
switch current
VI < −0.5 V or VI > VCC + 0.5 V
VSW < −0.5 V or VSW > VCC + 0.5 V
−0.5 V < VSW < VCC + 0.5 V
-
mA
mA
mA
mA
mA
mA
°C
ISK
-
ISW
IEE
-
supply current
-
ICC
supply current
-
IGND
Tstg
Ptot
P
ground current
-
−50
+150
500
100
storage temperature
total power dissipation
power dissipation
−65
[2]
Tamb = −40 °C to +125 °C
-
-
mW
mW
per switch
[1] To avoid drawing VCC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must
not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of pins nYn. In this case there is no limit for the
voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed VCC or VEE
.
[2] For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
5 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
9. Recommended operating conditions
Table 5.
Symbol
Recommended operating conditions
Parameter
Conditions
74HC4052
Typ
74HCT4052
Typ
Unit
Min
Max
Min
Max
VCC
supply voltage
see Figure 7
and Figure 8
VCC − GND
VCC − VEE
2.0
5.0
5.0
-
10.0
10.0
VCC
VCC
+125
625
139
83
4.5
5.0
5.0
-
5.5
10.0
VCC
VCC
V
V
V
V
2.0
2.0
VI
input voltage
GND
GND
VSW
Tamb
Δt/ΔV
switch voltage
VEE
-
VEE
-
ambient temperature
−40
+25
1.67
1.67
1.67
1.67
−40
+25
1.67
1.67
1.67
1.67
+125 °C
input transition rise and fall
rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 10.0 V
-
-
-
-
-
-
-
-
139
139
139
139
ns/V
ns/V
ns/V
ns/V
31
mnb044
mnb045
12
12
V
CC
− GND
(V)
V
CC
− GND
(V)
10
8
8
4
0
operating area
6
operating area
4
2
0
0
4
8
12
0
4
8
12
V
CC
− V (V)
EE
V
CC
− V (V)
EE
Fig 7. Guaranteed operating area as a function of the
supply voltages for 74HC4052
Fig 8. Guaranteed operating area as a function of the
supply voltages for 74HCT4052
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
6 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
10. Static characteristics
Table 6.
RON resistance per switch for 74HC4052 and 74HCT4052
VI = VIH or VIL; for test circuit see Figure 9.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
For 74HC4052: VCC − GND or VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
For 74HCT4052: VCC − GND = 4.5 V and 5.5 V, VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
RON(peak) ON resistance (peak)
Vis = VCC to VEE
[2]
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA
VCC = 4.5 V; VEE = 0 V; ISW = 1000 μA
VCC = 6.0 V; VEE = 0 V; ISW = 1000 μA
VCC = 4.5 V; VEE = −4.5 V; ISW = 1000 μA
Vis = VEE
-
-
-
-
-
-
Ω
Ω
Ω
Ω
100
90
70
225
200
165
RON(rail) ON resistance (rail)
[2]
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA
VCC = 4.5 V; VEE = 0 V; ISW = 1000 μA
VCC = 6.0 V; VEE = 0 V; ISW = 1000 μA
VCC = 4.5 V; VEE = −4.5 V; ISW = 1000 μA
Vis = VCC
-
-
-
-
150
80
-
Ω
Ω
Ω
Ω
175
150
130
70
60
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA
VCC = 4.5 V; VEE = 0 V; ISW = 1000 μA
VCC = 6.0 V; VEE = 0 V; ISW = 1000 μA
VCC = 4.5 V; VEE = −4.5 V; ISW = 1000 μA
Vis = VCC to VEE
-
-
-
-
150
90
-
Ω
Ω
Ω
Ω
200
175
150
80
65
ΔRON
ON resistance mismatch
between channels
[2]
VCC = 2.0 V; VEE = 0 V
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
VCC = 4.5 V; VEE = 0 V
9
8
6
VCC = 6.0 V; VEE = 0 V
VCC = 4.5 V; VEE = −4.5 V
Tamb = −40 °C to +125 °C
RON(peak) ON resistance (peak)
Vis = VCC to VEE
[2]
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA
VCC = 4.5 V; VEE = 0 V; ISW = 1000 μA
VCC = 6.0 V; VEE = 0 V; ISW = 1000 μA
VCC = 4.5 V; VEE = −4.5 V; ISW = 1000 μA
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
270
240
195
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
7 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
Table 6.
RON resistance per switch for 74HC4052 and 74HCT4052 …continued
VI = VIH or VIL; for test circuit see Figure 9.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
os is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
V
For 74HC4052: VCC − GND or VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
For 74HCT4052: VCC − GND = 4.5 V and 5.5 V, VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
RON(rail) ON resistance (rail)
Vis = VEE
[2]
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA
VCC = 4.5 V; VEE = 0 V; ISW = 1000 μA
VCC = 6.0 V; VEE = 0 V; ISW = 1000 μA
VCC = 4.5 V; VEE = −4.5 V; ISW = 1000 μA
Vis = VCC
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
210
180
160
[2]
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA
VCC = 4.5 V; VEE = 0 V; ISW = 1000 μA
VCC = 6.0 V; VEE = 0 V; ISW = 1000 μA
VCC = 4.5 V; VEE = −4.5 V; ISW = 1000 μA
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
240
210
180
[1] All typical values are measured at Tamb = 25 °C.
[2] When supply voltages (VCC − VEE) near 2.0 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
2 V, it is recommended to use these devices only for transmitting digital signals.
001aai068
100
(1)
R
ON
(Ω)
80
60
40
20
0
(2)
(3)
V
sw
V
V
V
CC
from select
input
Sn
nYn
nZ
GND
EE
V
I
sw
is
0
1.8
3.6
5.4
7.2
9.0
V
is
(V)
001aah826
Vis = 0 V to (VCC − VEE).
Vis = 0 V to (VCC − VEE).
(1) VCC = 4.5 V
(2) VCC = 6 V
(3) VCC = 9 V
Vsw
--------
=
RON
Isw
Fig 9. Test circuit for measuring RON
Fig 10. Typical RON as a function of input voltage Vis
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
8 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
Table 7.
Static characteristics for 74HC4052
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIH
HIGH-level input
voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
4.7
0.8
2.1
2.8
4.3
-
V
V
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VCC = 9.0 V
6.3
-
VIL
LOW-level input
voltage
VCC = 2.0 V
-
-
-
-
0.5
1.35
1.8
2.7
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
II
input leakage current
VEE = 0 V; VI = VCC or GND
VCC = 6.0 V
-
-
-
-
±1.0
±2.0
μA
μA
VCC = 10.0 V
IS(OFF)
OFF-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 11
per channel
all channels
-
-
-
-
-
-
±1.0
±2.0
±2.0
μA
μA
μA
IS(ON)
ICC
ON-state leakage
current
VI = VIH or VIL; |VSW| = VCC − VEE;
VCC = 10.0 V; VEE = 0 V; see Figure 12
supply current
VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC
Vos = VCC or VEE
;
VCC = 6.0 V
-
-
-
-
-
-
80.0
μA
μA
pF
pF
pF
VCC = 10.0 V
-
160.0
CI
input capacitance
switch capacitance
3.5
5
-
-
-
Csw
independent pins nYn
common pins nZ
12
Tamb = −40 °C to +125 °C
VIH
VIL
II
HIGH-level input
voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VCC = 9.0 V
6.3
-
LOW-level input
voltage
VCC = 2.0 V
-
-
-
-
0.5
1.35
1.8
2.7
VCC = 4.5 V
VCC = 6.0 V
VCC = 9.0 V
input leakage current
VEE = 0 V; VI = VCC or GND
VCC = 6.0 V
-
-
-
-
±1.0
±2.0
μA
μA
VCC = 10.0 V
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
9 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
Table 7.
Static characteristics for 74HC4052 …continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
os is the output voltage at pins nZ or nYn, whichever is assigned as an output.
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IS(OFF)
OFF-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 11
per channel
all channels
-
-
-
-
-
-
±1.0
±2.0
±2.0
μA
μA
μA
IS(ON)
ICC
ON-state leakage
current
VI = VIH or VIL; |VSW| = VCC − VEE;
VCC = 10.0 V; VEE = 0 V; see Figure 12
supply current
VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC;
Vos = VCC or VEE
VCC = 6.0 V
-
-
-
-
160.0
320.0
μA
μA
VCC = 10.0 V
[1] All typical values are measured at Tamb = 25 °C.
Table 8.
Static characteristics for 74HCT4052
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIH
VIL
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
1.2
-
-
V
LOW-level input
voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
±1.0
V
II
input leakage current
VI = VCC or GND; VCC = 5.5 V; VEE = 0 V
μA
IS(OFF)
OFF-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 11
per channel
all channels
-
-
-
-
-
-
±1.0
±2.0
±2.0
μA
μA
μA
IS(ON)
ICC
ON-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 12
supply current
VI = VCC or GND; Vis = VEE or VCC
;
Vos = VCC or VEE
VCC = 5.5 V; VEE = 0 V
-
-
-
-
80.0
μA
μA
μA
VCC = 5.0 V; VEE = −5.0 V
-
160.0
202.5
ΔICC
additional supply
current
per input; VI = VCC − 2.1 V; other inputs at VCC
45
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V
CI
input capacitance
switch capacitance
-
-
-
3.5
5
-
-
-
pF
pF
pF
Csw
independent pins nYn
common pins nZ
12
Tamb = −40 °C to +125 °C
VIH
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
V
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
10 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
Table 8.
Static characteristics for 74HCT4052 …continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
os is the output voltage at pins nZ or nYn, whichever is assigned as an output.
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
LOW-level input
voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
V
ILI
input leakage current
VI = VCC or GND; VCC = 5.5 V; VEE = 0 V
-
-
±1.0
μA
IS(OFF)
OFF-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 11
per channel
all channels
-
-
-
-
-
-
±1.0
±2.0
±2.0
μA
μA
μA
IS(ON)
ICC
ON-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 12
supply current
VI = VCC or GND; Vis = VEE or VCC
;
Vos = VCC or VEE
VCC = 5.5 V; VEE = 0 V
-
-
-
-
-
-
160.0
320.0
220.5
μA
μA
μA
VCC = 5.0 V; VEE = −5.0 V
ΔICC
additional supply
current
per input; VI = VCC − 2.1 V; other inputs at VCC
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V
[1] All typical values are measured at Tamb = 25 °C.
V
V
CC
from select
input
Sn
I
I
sw
A
sw
A
nYn
nZ
GND
EE
V
V
os
is
001aah827
Vis = VCC and Vos = VEE
Vis = VEE and Vos = VCC
.
.
Fig 11. Test circuit for measuring OFF-state current
V
V
CC
HIGH
from select
Sn
nYn
I
sw
A
input
nZ
V
os
GND
EE
V
is
001aah828
Vis = VCC and Vos = open-circuit.
Vis = VEE and Vos = open-circuit.
Fig 12. Test circuit for measuring ON-state current
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
11 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
Table 9.
Dynamic characteristics for 74HC4052
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
[2]
[3]
[4]
tpd
propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13
VCC = 2.0 V; VEE = 0 V
-
-
-
-
14
5
75
15
13
10
ns
ns
ns
ns
VCC = 4.5 V; VEE = 0 V
VCC = 6.0 V; VEE = 0 V
4
VCC = 4.5 V; VEE = −4.5 V
4
ton
turn-on time
turn-off time
E, Sn to Vos; RL = ∞ Ω; see Figure 14
VCC = 2.0 V; VEE = 0 V
-
-
-
-
105
38
405
81
ns
ns
ns
ns
VCC = 4.5 V; VEE = 0 V
VCC = 6.0 V; VEE = 0 V
30
69
VCC = 4.5 V; VEE = −4.5 V
E, Sn to Vos; RL = 1 kΩ; see Figure 14
VCC = 2.0 V; VEE = 0 V
26
58
toff
-
-
-
-
-
74
27
22
22
57
315
63
54
48
-
ns
ns
ns
ns
pF
VCC = 4.5 V; VEE = 0 V
VCC = 6.0 V; VEE = 0 V
VCC = 4.5 V; VEE = −4.5 V
[5]
[2]
CPD
power dissipation per switch; VI = GND to VCC
capacitance
Tamb = −40 °C to +125 °C
tpd propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13
VCC = 2.0 V; VEE = 0 V
VCC = 4.5 V; VEE = 0 V
-
-
-
-
-
-
-
-
90
18
15
12
ns
ns
ns
ns
VCC = 6.0 V; VEE = 0 V
VCC = 4.5 V; VEE = −4.5 V
E, Sn to Vos; RL = ∞ Ω; see Figure 14
VCC = 2.0 V; VEE = 0 V
[3]
ton
turn-on time
-
-
-
-
-
-
-
-
490
98
ns
ns
ns
ns
VCC = 4.5 V; VEE = 0 V
VCC = 6.0 V; VEE = 0 V
83
VCC = 4.5 V; VEE = −4.5 V
69
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
12 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
Table 9.
Dynamic characteristics for 74HC4052 …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
os is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
V
Symbol Parameter
toff turn-off time
Conditions
Min
Typ
Max
Unit
[4]
E, Sn to Vos; RL = 1 kΩ; see Figure 14
VCC = 2.0 V; VEE = 0 V
VCC = 4.5 V; VEE = 0 V
VCC = 6.0 V; VEE = 0 V
VCC = 4.5 V; VEE = −4.5 V
-
-
-
-
-
-
-
-
375
75
ns
ns
ns
ns
64
57
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPHL and tPLH
.
[3] ton is the same as tPZH and tPZL
.
[4] toff is the same as tPHZ and tPLZ
.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ{(CL + Csw) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
N = number of inputs switching;
Σ{(CL + Csw) × VCC2 × fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
Table 10. Dynamic characteristics for 74HCT4052
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
[2]
[3]
[4]
tpd
propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13
VCC = 4.5 V; VEE = 0 V
-
-
5
4
15
10
ns
ns
VCC = 4.5 V; VEE = −4.5 V
ton
turn-on time
turn-off time
E, Sn to Vos; RL = 1 kΩ; see Figure 14
VCC = 4.5 V; VEE = 0 V
-
-
41
28
88
60
ns
ns
VCC = 4.5 V; VEE = −4.5 V
toff
E, Sn to Vos; RL = 1 kΩ; see Figure 14
VCC = 4.5 V; VEE = 0 V
-
-
-
26
21
57
63
48
-
ns
ns
pF
VCC = 4.5 V; VEE = −4.5 V
[5]
[2]
CPD
power dissipation per switch; VI = GND to VCC − 1.5 V
capacitance
Tamb = −40 °C to +125 °C
tpd
propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13
VCC = 4.5 V; VEE = 0 V
-
-
-
-
18
12
ns
ns
VCC = 4.5 V; VEE = −4.5 V
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
13 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
Table 10. Dynamic characteristics for 74HCT4052 …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
os is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
V
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[3]
ton
turn-on time
E, Sn to Vos; RL = 1 kΩ; see Figure 14
VCC = 4.5 V; VEE = 0 V
-
-
-
-
105
72
ns
ns
VCC = 4.5 V; VEE = −4.5 V
E, Sn to Vos; RL = 1 kΩ; see Figure 14
VCC = 4.5 V; VEE = 0 V
[4]
toff
turn-off time
-
-
-
-
75
57
ns
ns
VCC = 4.5 V; VEE = −4.5 V
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPHL and tPLH
.
[3] ton is the same as tPZH and tPZL
.
[4] toff is the same as tPHZ and tPLZ
.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ{(CL + Csw) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
N = number of inputs switching;
Σ{(CL + Csw) × VCC2 × fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
50 %
V
input
is
t
t
PLH
PHL
50 %
V
os
output
001aad555
Fig 13. Input (Vis) to output (Vos) propagation delays
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
14 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
V
I
V
M
E, Sn inputs
0 V
t
PZL
t
PLZ
50 %
V
output
output
os
os
10 %
t
t
PHZ
PZH
90 %
50 %
V
switch ON
switch OFF
switch ON
001aae330
For 74HC4052: VM = 0.5 × VCC
.
For 74HCT4052: VM = 1.3 V.
Fig 14. Turn-on and turn-off times
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
0 V
t
W
V
V
V
CC
is
CC
V
V
os
I
S1
R
L
PULSE
GENERATOR
open
DUT
R
C
L
T
GND
V
EE
001aae382
Definitions for test circuit; see Table 11:
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
S1 = Test selection switch.
Fig 15. Test circuit for measuring AC performance
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
15 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
Table 11. Test data
Test
Input
VI
Load
CL
S1 position
Vis
tr, tf
RL
at fmax
< 2 ns
< 2 ns
< 2 ns
other[1]
6 ns
[2]
[2]
[2]
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
pulse
VCC
50 pF
50 pF
50 pF
1 kΩ
1 kΩ
1 kΩ
open
VEE
6 ns
VEE
6 ns
VCC
[1] tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor.
[2] VI values:
a) For 74HC4052: VI = VCC
b) For 74HCT4052: VI = 3 V
12. Additional dynamic characteristics
Table 12. Additional dynamic characteristics
Recommended conditions and typical values; GND = 0 V; Tamb = 25 °C; CL = 50 pF.
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nYn or nZ, whichever is assigned as an output.
Symbol
Parameter
Conditions
Min Typ Max Unit
dsin
sine-wave distortion
fi = 1 kHz; RL = 10 kΩ; see Figure 16
Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = −2.25 V
Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = −4.5 V
fi = 10 kHz; RL = 10 kΩ; see Figure 16
Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = −2.25 V
Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = −4.5 V
RL = 600 Ω; fi = 1 MHz; see Figure 17
VCC = 2.25 V; VEE = −2.25 V
-
-
0.04
0.02
-
-
%
%
-
-
0.12
0.06
-
-
%
%
αiso
isolation (OFF-state)
crosstalk
[1]
[1]
-
-
−50
−50
-
-
dB
dB
VCC = 4.5 V; VEE = −4.5 V
Xtalk
between two switches/multiplexers;
RL = 600 Ω; fi = 1 MHz; see Figure 18
[1]
[1]
VCC = 2.25 V; VEE = −2.25 V
VCC = 4.5 V; VEE = −4.5 V
-
-
−60
−60
-
-
dB
dB
Vct
crosstalk voltage
peak-to-peak value; between control and any
switch; RL = 600 Ω; fi = 1 MHz; E or Sn square
wave between VCC and GND; tr = tf = 6 ns;
see Figure 19
VCC = 4.5 V; VEE = 0 V
VCC = 4.5 V; VEE = −4.5 V
RL = 50 Ω; see Figure 20
VCC = 2.25 V; VEE = −2.25 V
VCC = 4.5 V; VEE = −4.5 V
-
-
110
220
-
-
mV
mV
f(−3dB)
−3 dB frequency response
[2]
[2]
-
-
170
180
-
-
MHz
MHz
[1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω).
[2] Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 Ω).
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
16 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
V
CC
Sn
10 μF
nYn/nZ
nZ/nYn
V
is
V
os
V
EE
GND
R
C
L
dB
L
001aah829
Fig 16. Test circuit for measuring sine-wave distortion
V
CC
Sn
0.1 μF
nYn/nZ
nZ/nYn
GND
V
is
V
os
V
EE
R
C
L
dB
L
001aah871
VCC = 4.5 V; GND = 0 V; VEE = −4.5 V; RL = 50 Ω; RS = 1 kΩ.
a. Test circuit
001aae332
0
α
iso
(dB)
−20
−40
−60
−80
−100
2
3
4
5
6
10
10
10
10
10
10
f (kHz)
i
b. Isolation (OFF-state) as a function of frequency
Fig 17. Test circuit for measuring isolation (OFF-state)
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
17 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
V
CC
Sn
0.1 μF
R
L
nYn/nZ
nZ/nYn
GND
V
is
V
EE
R
C
L
L
V
CC
Sn
nYn/nZ
nZ/nYn
GND
V
os
V
EE
R
R
C
L
dB
L
L
001aah873
Fig 18. Test circuits for measuring crosstalk between any two switches/multiplexers
2R
2R
L
L
L
V
CC
Sn, E
nYn
V
ct
nZ
GND
G
V
EE
2R
2R
oscilloscope
L
001aah913
Fig 19. Test circuit for measuring crosstalk between control input and any switch
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
18 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
V
CC
Sn
10 μF
nYn/nZ
nZ/nYn
V
is
V
os
V
EE
GND
R
C
L
dB
L
001aah829
VCC = 4.5 V; GND = 0 V; VEE = −4.5 V; RL = 50 Ω; RS = 1 kΩ.
a. Test circuit
001aad551
5
V
os
(dB)
3
1
−1
−3
−5
2
3
4
5
6
10
10
10
10
10
10
f (kHz)
b. Typical frequency response
Fig 20. Test circuit for frequency response
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
19 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 21. Package outline SOT109-1 (SO16)
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
20 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 22. Package outline SOT338-1 (SSOP16)
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
21 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 23. Package outline SOT38-4 (DIP16)
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
22 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 24. Package outline SOT403-1 (TSSOP16)
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
23 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
y
D
D
E
L
v
w
y
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 25. Package outline SOT763-1 (DHVQFN16)
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
24 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
14. Abbreviations
Table 13. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
15. Revision history
Table 14. Revision history
Document ID
Release date
20100111
Data sheet status
Change notice
Supersedes
74HC_HCT4052_6
Modifications:
Product data sheet
-
74HC_HCT4052_5
• Added type number 74HCT4052PW (TSSOP16 / SOT403-1 package).
74HC_HCT4052_5
74HC_HCT4052_4
74HC_HCT4052_3
20080505
20041111
20030516
Product data sheet
Product specification
Product specification
-
-
-
-
-
74HC_HCT4052_4
74HC_HCT4052_3
74HC_HCT4052_CNV_2
-
74HC_HCT4052_CNV_2 19901201
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
25 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT4052_6
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 11 January 2010
26 of 27
74HC4052; 74HCT4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 12
Additional dynamic characteristics . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 26
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 January 2010
Document identifier: 74HC_HCT4052_6
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