74HCT259D,653 [NXP]
74HC(T)259 - 8-bit addressable latch SOP 16-Pin;
| 型号： | 74HCT259D,653 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)259 - 8-bit addressable latch SOP 16-Pin 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总21页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC259; 74HCT259
8-bit addressable latch
Rev. 04 — 25 February 2009
Product data sheet
1. General description
The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7-A.
The 74HC259; 74HCT259 are high-speed 8-bit addressable latches designed for general
purpose storage applications in digital systems. They are multifunctional devices capable
of storing single-line data in eight addressable latches and providing a 3-to-8 decoder and
multiplexer function with active HIGH outputs (Q0 to Q7). They also incorporates an active
LOW common reset (MR) for resetting all latches as well as an active LOW enable input
(LE).
The 74HC259; 74HCT259 has four modes of operation:
• Addressable latch mode, in this mode data on the data line (D) is written into the
addressed latch. The addressed latch will follow the data input with all non-addressed
latches remaining in their previous states.
• Memory mode, in this mode all latches remain in their previous states and are
unaffected by the data or address inputs.
• Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows
the state of the data input (D) with all other outputs in the LOW state.
• Reset mode, in this mode all outputs are LOW and unaffected by the address inputs
(A0 to A2) and data input (D).
When operating the 74HC259; 74HCT259 as an address latch, changing more than one
address bit could impose a transient wrong address. Therefore, this should only be done
while in the Memory mode.
2. Features
I Combined demultiplexer and 8-bit latch
I Serial-to-parallel capability
I Output from each storage bit available
I Random (addressable) data entry
I Easily expandable
I Common reset input
I Useful as a 3-to-8 active HIGH decoder
I Input levels:
N For 74HC259: CMOS level
N For 74HCT259: TTL level
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC259N
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HCT259N
74HC259D
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SOT338-1
SOT403-1
74HCT259D
74HC259DB
74HCT259DB
74HC259PW
74HCT259PW
74HC259BQ
74HCT259BQ
SSOP16
TSSOP16
plastic shrink small outline package; 16 leads; body
width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
4. Functional diagram
13
Z9
15
G8
14
G10
9,10D
1
DX
4
C10
8R
14
LE
0
1
2
3
0
2
5
6
4
5
0
7
1
2
3
4
5
6
7
Q0
G
13
D
Q1
Q2
Q3
Q4
Q5
Q6
Q7
6
7
7
9
1
2
3
9
A0
A1
A2
10
11
12
10
11
12
MR
15 mna573
mna572
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
2 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
Q0
Q1
Q2
Q3
Q4
Q5
4
5
A0
A1
A2
1
2
3
6
1-of-8
DECODER
7
8 LATCHES
9
14 LE
10
15
13
Q6 11
Q7 12
MR
D
mna571
Fig 3. Functional diagram
5. Pinning information
5.1 Pinning
74HC259
74HCT259
terminal 1
index area
74HC259
74HCT259
2
3
4
5
6
7
15
14
13
12
11
10
A1
MR
LE
D
A2
Q0
Q1
Q2
Q3
1
2
3
4
5
6
7
8
16
V
A0
A1
CC
15
14
13
12
11
10
9
MR
LE
D
A2
Q7
Q6
Q5
Q0
(1)
GND
Q1
Q7
Q6
Q5
Q4
Q2
Q3
001aaj445
GND
Transparent top view
001aaj444
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 4. Pin configuration (DIP16, SO16, SSOP16 and
TSSOP16)
Fig 5. Pin configuration (DHVQFN16)
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
3 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
A0, A1, A2
1, 2, 3
address input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output
GND
D
8
ground (0 V)
data input
13
14
15
16
LE
latch enable input (active LOW)
conditional reset input (active LOW)
supply voltage
MR
VCC
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
Output
MR LE
D
X
d
d
d
d
d
d
d
d
X
d
d
d
d
d
d
d
d
A0 A1 A2 Q0
Q1
Q2
L
Q3
L
Q4
L
Q5
L
Q6
L
Q7
L
Reset (clear)
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
L
X
L
X
L
L
L
Demultiplexer
(active HIGH 8-channel)
decoder (when D = H)
L
Q = d L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
q0
Q = d L
L
L
L
L
L
L
H
H
L
L
L
Q = d L
L
L
L
L
L
H
L
L
L
L
Q = d L
L
L
L
L
H
H
H
H
X
L
L
L
L
Q = d L
L
L
L
H
L
L
L
L
L
L
Q = d L
L
L
H
H
X
L
L
L
L
L
L
Q = d L
L
H
X
L
L
L
L
L
L
L
Q = d
Memory (no action)
Addressable latch
H
H
H
H
H
H
H
H
H
q1
q2
q2
q3
q3
q3
q4
q4
q4
q4
q5
q5
q5
q5
q5
q6
q6
q6
q6
q6
q6
q7
q7
q7
q7
q7
q7
q7
Q = d q1
H
L
L
L
q0
q0
q0
q0
q0
q0
q0
Q = d q2
H
H
L
L
q1
q1
q1
q1
q1
q1
Q = d q3
H
L
L
q2
q2
q2
q2
q2
Q = d q4
H
H
H
H
q3
q3
q3
q3
Q = d q5
H
L
L
q4
q4
q4
Q = d q6
H
H
q5
q5
Q = d q7
q6 Q = d
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
4 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
Table 4.
Operating mode select table[1]
LE
L
MR
H
Mode
Addressable latch mode
Memory mode
Demultiplexer mode
Reset mode
H
L
H
L
H
L
[1] H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7.0
±20
±20
±25
+70
-
Unit
V
VCC
IIK
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to VCC + 0.5 V
-
mA
mA
mA
mA
mA
°C
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−70
−65
storage temperature
total power dissipation
+150
Tamb = −40 °C to +125 °C
DIP16 package
[2]
[3]
[4]
[5]
-
-
-
-
750
500
500
500
mW
mW
mW
mW
SO16 package
(T)SSOP16 package
DHVQFN16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70 °C.
[3] Ptot derates linearly with 8 mW/K above 70 °C.
[4] Ptot derates linearly with 5.5 mW/K above 60 °C.
[5] Ptot derates linearly with 4.5 mW/K above 60 °C.
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
5 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
8. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC259
74HCT259
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
V
VO
output voltage
0
-
0
-
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
−40
-
−40
-
°C
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
9. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HC259
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15 2.4
3.15
3.15
VCC = 6.0 V
4.2
3.2
0.8
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = −4.0 mA; VCC = 4.5 V 3.98 4.32
IO = −5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND;
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
±1
V
V
II
input leakage
current
-
±0.1
µA
V
CC = 6.0 V
ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
-
8.0
-
80
-
160
µA
V
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
6 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
CI
input
-
3.5
-
-
-
-
-
pF
capacitance
74HCT259
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = −4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND;
-
-
-
0
0.1
-
-
-
0.1
0.33
±1
-
-
-
0.1
0.4
±1
V
0.15 0.26
V
II
input leakage
current
-
±0.1
µA
V
CC = 5.5 V
ICC
∆ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
8.0
-
80
-
160
µA
V
additional
VI = VCC − 2.1 V; IO = 0 A;
supply current other inputs at VCC or GND;
V
CC = 4.5 V to 5.5 V
pin An, LE
pin D
-
-
-
-
150 540
120 432
-
-
-
-
675
540
338
-
-
-
-
-
735
588
368
-
µA
µA
µA
pF
pin MR
75
270
-
CI
input
3.5
capacitance
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
7 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
10. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter
Conditions
25 °C
Min Typ[1] Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
74HC259
[2]
[2]
[2]
tpd
propagation
delay
D to Qn; see Figure 6
VCC = 2.0 V
-
-
-
-
58
21
18
17
185
37
-
-
-
-
-
230
46
-
-
-
-
-
280
56
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
31
39
48
An to Qn; see Figure 7
VCC = 2.0 V
-
-
-
-
58
21
17
17
185
37
-
-
-
-
-
230
46
-
-
-
-
-
280
56
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
31
39
48
LE to Qn; see Figure 8
VCC = 2.0 V
-
-
-
-
55
20
17
16
170
34
-
-
-
-
-
215
43
-
-
-
-
-
255
51
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
29
37
43
tPHL
HIGH to LOW MR to Qn; see Figure 9
propagation
delay
VCC = 2.0 V
-
-
-
-
50
18
15
14
155
31
-
-
-
-
-
195
39
-
-
-
-
-
235
47
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
26
33
40
[3]
tt
transition time see Figure 8
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
119
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
pulse width
LE HIGH or LOW;
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
70
14
12
17
6
-
-
-
90
18
15
-
-
-
105
21
-
-
-
ns
ns
ns
VCC = 6.0 V
5
18
MR LOW; see Figure 9
VCC = 2.0 V
70
14
12
17
6
-
-
-
90
18
15
-
-
-
105
21
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
18
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
8 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter
Conditions
25 °C
Min Typ[1] Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
tsu
set-up time
hold time
D, An to LE; see Figure 10
and Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
19
7
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
6
17
20
th
D to LE; see Figure 10
and Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
−19
−6
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
−5
An to LE; see Figure 10
and Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
2
2
2
-
−11
−4
-
-
-
-
2
2
2
-
-
-
-
-
2
2
2
-
-
-
-
-
ns
ns
ns
pF
−3
[4]
CPD
power
fi = 1 MHz;
19
dissipation
capacitance
VI = GND to VCC
74HCT259
[2]
[2]
[2]
tpd
propagation
delay
D to Qn; see Figure 6
VCC = 4.5 V
-
-
23
20
39
-
-
-
49
-
-
-
59
-
ns
ns
VCC = 5.0 V; CL = 15 pF
An to Qn; see Figure 7
VCC = 4.5 V
-
-
25
20
41
-
51
-
62
-
ns
ns
VCC = 5.0 V; CL = 15 pF
LE to Qn; see Figure 8
VCC = 4.5 V
-
-
-
-
22
20
38
-
-
-
48
-
-
-
57
-
ns
ns
VCC = 5.0 V; CL = 15 pF
tPHL
HIGH to LOW MR to Qn; see Figure 9
propagation
delay
VCC = 4.5 V
-
-
23
20
39
-
-
-
49
-
-
-
59
-
ns
ns
VCC = 5.0 V; CL = 15 pF
[3]
tt
transition time see Figure 8
VCC = 4.5 V
-
7
15
-
19
-
22
ns
tW
pulse width
LE HIGH or LOW;
see Figure 8
VCC = 4.5 V
19
18
11
10
-
-
24
23
-
-
29
27
-
-
ns
ns
MR LOW; see Figure 9
VCC = 4.5 V
tsu
set-up time
D, An to LE; see Figure 10
and Figure 11
VCC = 4.5 V
17
10
-
21
-
26
-
ns
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
9 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter
Conditions
25 °C
Min Typ[1] Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
th
hold time
D to LE; see Figure 10
and Figure 11
VCC = 4.5 V
0
−8
-
0
-
0
-
ns
An to LE; see Figure 10
and Figure 11
VCC = 4.5 V
0
-
−4
-
-
0
-
-
-
0
-
-
-
ns
[4]
CPD
power
fi = 1 MHz;
19
pF
dissipation
capacitance
VI = GND to VCC − 1.5 V
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
[3] tt is the same as tTHL and tTLH
.
.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
V
CC
D input
V
M
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aah123
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Data input to output propagation delays
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
10 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
V
CC
V
An input
M
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aah122
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Address input to output propagation delays
V
CC
D input
GND
V
CC
V
M
LE input
GND
t
W
t
t
PLH
PHL
V
OH
V
Y
V
Qn output
M
V
X
V
OL
t
t
THL
TLH
001aaj446
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Enable input to output propagation delays and pulse width
V
CC
MR input
V
M
GND
t
W
t
PHL
V
OH
V
Qn output
M
V
OL
001aah124
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Master reset input to output propagation delays
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
11 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
V
CC
LE input
V
M
GND
t
t
su
su
t
t
h
h
V
CC
V
D input
M
GND
V
OH
V
Qn output
Q = D
Q = D
M
V
OL
001aah125
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. Data input to latch enable input set-up and hold times
V
CC
An input
LE input
V
ADDRESS STABLE
M
GND
t
t
h
su
V
CC
V
M
GND
001aah126
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. Address input to latch enable input set-up and hold times
Table 9.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC259
0.5VCC
1.3 V
0.5VCC
1.3 V
0.1VCC
0.1VCC
0.9VCC
0.9VCC
74HCT259
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
12 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 12. Load circuit for measuring switching times
Table 10. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC259
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT259
open
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
13 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
12. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 13. Package outline SOT38-4 (DIP16)
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
14 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 14. Package outline SOT109-1 (SO16)
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
15 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 15. Package outline SOT338-1 (SSOP16)
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
16 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 16. Package outline SOT403-1 (TSSOP16)
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
17 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 17. Package outline SOT763-1 (DHVQFN16)
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
18 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
13. Abbreviations
Table 11. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 12. Revision history
Document ID
74HC_HCT259_4
Modifications:
Release date
20090225
Data sheet status
Change notice
Supersedes
Product data sheet
-
74HC_HCT259_3
• Added type number 74HC259N and 74HCT259N (DIP16 package)
• Added type number 74HC259DB and 74HCT259DB (SSOP16 package)
74HC_HCT259_3
20090108
Product data sheet
-
74HC_HCT259_CNV_2
74HC_HCT259_CNV_2 19970828
Product specification
-
-
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
19 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
20 of 21
74HC259; 74HCT259
NXP Semiconductors
8-bit addressable latch
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 February 2009
Document identifier: 74HC_HCT259_4
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