74AHC2G00DP-G [NXP]
2-input NAND gate - Description: Dual 2-Input NAND Gate ; Logic switching levels: CMOS ; Number of pins: 8 ; Output drive capability: +/- 8.0 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.5 @5V ns; Voltage: 2.0-5.5 V;
| 型号： | 74AHC2G00DP-G |
| 厂家： | 
NXP |
| 描述： | 2-input NAND gate - Description: Dual 2-Input NAND Gate ; Logic switching levels: CMOS ; Number of pins: 8 ; Output drive capability: +/- 8.0 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.5 @5V ns; Voltage: 2.0-5.5 V 栅 |
| 文件： | 总17页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AHC2G00; 74AHCT2G00
2-input NAND gate
Product specification
2004 Jan 21
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
FEATURES
DESCRIPTION
• Symmetrical output impedance
• High noise immunity
The 74AHC2G/AHCT2G00 is a high-speed Si-gate CMOS
device.
The 74AHC2G/AHCT2G00 provides the 2-input NAND
gate function.
• ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 500 V.
• Low power dissipation
• Balanced propagation delays
• SOT505-2 and SOT765-1 package
• Specified from −40 to +85 °C and −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
AHC2G
3.5
AHCT2G
3.6
tPHL/tPLH propagation delay nA and nB to nY
CL = 15 pF; VCC = 5 V
ns
pF
pF
CI
input capacitance
1.5
17
1.5
18
CPD
power dissipation capacitance per
gate
CL = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2004 Jan 21
2
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nY
nA
nB
L
L
L
H
L
H
H
H
L
H
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
PACKAGE MATERIAL
TEMPERATURE
RANGE
PINS
CODE
MARKING
74AHC2G00DP
74AHCT2G00DP
74AHC2G00DC
74AHCT2G00DC
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
8
8
8
8
TSSOP8
TSSOP8
VSSOP8
VSSOP8
plastic
plastic
plastic
plastic
SOT505-2
SOT505-2
SOT765-1
SOT765-1
A00
C00
A00
C00
PINNING
PIN
SYMBOL
DESCRIPTION
1
2
3
4
5
6
7
8
1A
1B
2Y
data input
data input
data output
ground (0 V)
data input
GND
2A
2B
data input
1Y
data output
supply voltage
VCC
2004 Jan 21
3
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
handbook, halfpage
1A
1B
1
2
3
4
8
7
6
5
V
CC
handbook, halfpage
1
2
1A
1B
1Y
2Y
7
3
1Y
2B
2A
00
5
6
2A
2B
2Y
GND
MNA712
MNA711
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1
handbook, halfpage
&
&
7
3
2
handbook, halfpage
B
A
Y
5
6
MNA099
MNA713
Fig.3 IEC logic symbol.
Fig.4 Logic diagram.
2004 Jan 21
4
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
RECOMMENDED OPERATING CONDITIONS
74AHC2G00
MIN. TYP. MAX. MIN.
2.0
74AHCT2G00
SYMBOL
PARAMETER
CONDITIONS
UNIT
TYP. MAX.
VCC
VI
supply voltage
input voltage
output voltage
5.0
−
5.5
5.5
VCC
4.5
0
5.0
−
5.5
5.5
VCC
V
0
V
V
VO
0
−
0
−
Tamb
operating ambient see DC and AC
−40
+25
+125 −40
+25
+125 °C
temperature
characteristics per device
tr, tf
input rise and fall VCC = 3.3 ± 0.3 V
−
−
−
−
100
20
−
−
−
−
−
ns/V
ns/V
times
VCC = 5 ± 0.5 V
20
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
VI
−0.5
−0.5
−
+7.0
+7.0
−20
±20
±25
±75
V
input voltage
V
IIK
input diode current
output diode current
output source or sink current
VI < −0.5 V
mA
mA
mA
mA
IOK
IO
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−0.5 V < VO < VCC + 0.5 V
−
−
ICC, IGND VCC or GND current
−
Tstg
PD
storage temperature
power dissipation
−65
−
+150 °C
250 mW
Tamb = −40 to +125 °C
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2004 Jan 21
5
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
DC CHARACTERISTICS
Type 74AHC2G00
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
OTHER
VCC (V)
Tamb = 25 °C
VIH
HIGH-level input
voltage
2.0
3.0
5.5
2.0
3.0
5.5
1.5
−
−
−
−
−
−
−
V
V
V
V
V
V
2.1
3.85
−
−
−
VIL
LOW-level input
voltage
0.5
0.9
1.65
−
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −50 µA
IO = −50 µA
IO = −50 µA
2.0
3.0
4.5
3.0
4.5
1.9
2.0
3.0
4.5
−
−
−
−
−
−
V
V
V
V
V
2.9
4.4
IO = −4.0 mA
IO = −8.0 mA
VI = VIH or VIL
IO = 50 µA
2.58
3.94
−
VOL
LOW-level output
voltage
2.0
3.0
4.5
3.0
4.5
5.5
−
−
−
−
−
−
0
0
0
−
−
−
0.1
V
IO = 50 µA
0.1
V
IO = 50 µA
0.1
V
IO = 4.0 mA
IO = 8.0 mA
VI = VCC or GND
0.36
0.36
0.1
V
V
ILI
input leakage
current
µA
ICC
CI
quiescent supply
current
VI = VCC or GND; IO = 0
5.5
−
−
−
10
10
µA
input capacitance
−
1.5
pF
2004 Jan 21
6
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
CONDITIONS
OTHER
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input
2.0
3.0
5.5
2.0
3.0
5.5
1.5
−
−
−
−
−
−
−
V
V
V
V
V
V
voltage
2.1
3.85
−
−
−
VIL
LOW-level input
voltage
0.5
0.9
1.65
−
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −50 µA
IO = −50 µA
IO = −50 µA
2.0
3.0
4.5
3.0
4.5
1.9
2.9
4.4
2.48
3.8
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
IO = −4.0 mA
IO = −8.0 mA
VI = VIH or VIL
IO = 50 µA
VOL
LOW-level output
voltage
2.0
3.0
4.5
3.0
4.5
5.5
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
IO = 50 µA
0.1
V
IO = 50 µA
0.1
V
IO = 4.0 mA
IO = 8.0 mA
VI = VCC or GND
0.44
0.44
1.0
V
V
ILI
input leakage
current
µA
ICC
CI
quiescent supply
current
VI = VCC or GND; IO = 0
5.5
−
−
−
−
10
10
µA
input capacitance
−
pF
2004 Jan 21
7
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
CONDITIONS
OTHER
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
VCC (V)
Tamb = −40 to +125 °C
VIH HIGH-level input
2.0
3.0
5.5
2.0
3.0
5.5
1.5
−
−
−
−
−
−
−
V
V
V
V
V
V
voltage
2.1
3.85
−
−
−
VIL
LOW-level input
voltage
0.5
0.9
1.65
−
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −50 µA
IO = −50 µA
IO = −50 µA
2.0
3.0
4.5
3.0
4.5
1.9
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
2.9
4.4
IO = −4.0 mA
IO = −8.0 mA
VI = VIH or VIL
IO = 50 µA
2.40
3.70
VOL
LOW-level output
voltage
2.0
3.0
4.5
3.0
4.5
5.5
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
IO = 50 µA
0.1
V
IO = 50 µA
0.1
V
IO = 4.0 mA
IO = 8.0 mA
VI = VCC or GND
0.55
0.55
2.0
V
V
ILI
input leakage
current
µA
ICC
CI
quiescent supply
current
VI = VCC or GND; IO = 0
5.5
−
−
−
−
40
10
µA
input capacitance
−
pF
2004 Jan 21
8
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
Type 74AHCT2G00
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP. MAX. UNIT
OTHER
VCC (V)
Tamb = 25 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
4.5 to 5.5
4.5 to 5.5
2.0
−
−
−
V
V
−
0.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −50 µA
4.5
4.5
4.4
4.5
−
−
V
V
IO = −8.0 mA
3.94
−
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 50 µA
4.5
4.5
5.5
5.5
5.5
−
−
−
−
−
0
−
−
−
−
0.1
V
IO = 8.0 mA
0.36
0.1
V
ILI
input leakage current
VI = VIH or VIL
VI = VCC or GND; IO = 0
µA
µA
mA
ICC
∆ICC
quiescent supply current
1.0
additional quiescent supply VI = 3.4 V; other inputs at
1.35
current per input pin
VCC or GND; IO = 0
CI
input capacitance
−
1.5
10
pF
Tamb = −40 to +85 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
4.5 to 5.5
4.5 to 5.5
2.0
−
−
−
V
V
−
0.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −50 µA
4.5
4.5
4.4
3.8
−
−
−
−
V
V
IO = −8.0 mA
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 50 µA
4.5
4.5
5.5
5.5
5.5
−
−
−
−
−
−
−
−
−
−
0.1
0.44
1.0
10
V
IO = 8.0 mA
V
ILI
input leakage current
VI = VIH or VIL
VI = VCC or GND; IO = 0
µA
µA
mA
ICC
∆ICC
quiescent supply current
additional quiescent supply VI = 3.4 V; other inputs at
1.5
current per input pin
VCC or GND; IO = 0
CI
input capacitance
−
−
−
10
pF
2004 Jan 21
9
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
CONDITIONS
OTHER
SYMBOL
PARAMETER
MIN.
TYP. MAX. UNIT
VCC (V)
Tamb = −40 to +125 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
4.5 to 5.5
4.5 to 5.5
2.0
−
−
−
V
V
−
0.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −50 µA
4.5
4.5
4.4
−
−
−
−
V
V
IO = −8.0 mA
VI = VIH or VIL
IO = 50 µA
3.70
VOL
LOW-level output voltage
4.5
4.5
5.5
5.5
5.5
−
−
−
−
−
−
−
−
−
−
0.1
0.55
2.0
40
V
IO = 8.0 mA
V
ILI
input leakage current
VI = VIH or VIL
VI = VCC or GND; IO = 0
µA
µA
mA
ICC
∆ICC
quiescent supply current
additional quiescent supply VI = 3.4 V; other inputs at
1.5
current per input pin
VCC or GND; IO = 0
CI
input capacitance
−
−
−
10
pF
2004 Jan 21
10
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
AC CHARACTERISTICS
Type 74AHC2G00
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
WAVEFORMS CL (pF)
SYMBOL
PARAMETER
MIN. TYP. MAX. UNIT
VCC (V)
T
amb = 25 °C
tPHL/tPLH propagation delay
input nA and nB to output nY
see Figs 5 and 6 15
50
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
−
−
−
−
4.5(1) 7.9
3.5(2) 5.5
6.5(1) 11.4 ns
ns
ns
4.9(2) 7.5
ns
Tamb = −40 to +85 °C
tPHL/tPLH propagation delay
input nA and nB to output nY
see Figs 5 and 6 15
50
3.0 to 3.6 1.0
4.5 to 5.5 1.0
3.0 to 3.6 1.0
4.5 to 5.5 1.0
−
−
−
−
9.5
6.5
ns
ns
13.0 ns
8.5 ns
Tamb = −40 to +125 °C
tPHL/tPLH
propagation delay
input nA and nB to output nY
see Figs 5 and 6 15
50
3.0 to 3.6 1.0
4.5 to 5.5 1.0
3.0 to 3.6 1.0
4.5 to 5.5 1.0
−
−
−
−
10.5 ns
7.0 ns
14.5 ns
9.5 ns
Notes
1. Typical values are measured at VCC = 3.3 V.
2. Typical values are measured at VCC = 5.0 V.
2004 Jan 21
11
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
Type 74AHCT2G00
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
WAVEFORMS CL (pF)
SYMBOL
PARAMETER
MIN. TYP. MAX. UNIT
VCC (V)
T
amb = 25 °C
tPHL/tPLH propagation delay
input nA and nB to output nY
Tamb = −40 to +85 °C
see Figs 5 and 6 15
50
4.5 to 5.5 1.0
4.5 to 5.5 1.0
3.6(1) 6.2
5.0(1) 7.9
ns
ns
tPHL/tPLH
propagation delay
input nA and nB to output nY
see Figs 5 and 6 15
50
4.5 to 5.5 1.0
4.5 to 5.5 1.0
−
−
7.1
9.0
ns
ns
Tamb = −40 to +125 °C
tPHL/tPLH
propagation delay
input nA and nB to output nY
see Figs 5 and 6 15
50
4.5 to 5.5 1.0
4.5 to 5.5 1.0
−
−
8.0
ns
10.0 ns
Note
1. Typical values are measured at VCC = 5.0 V.
2004 Jan 21
12
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
AC WAVEFORMS
handbook, halfpage
nA, nB input
V
t
M
t
PHL
PLH
nY output
V
M
MNA213
VM
VM
FAMILY
INPUT OUTPUT
50% VCC 50% VCC
1.5 V 50% VCC
AHC2G00
AHCT2G00
Fig.5 The inputs (nA and nB) to output (nY) propagation delays.
V
handbook, halfpage
CC
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
L
T
MNA101
VI INPUT
REQUIREMENTS
FAMILY
AHC2G00
GND to VCC
AHCT2G00
GND to 3.0 V
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance (See “AC characteristics” for the value).
RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator.
Fig.6 Load circuitry for switching times.
13
2004 Jan 21
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
PACKAGE OUTLINES
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
2004 Jan 21
14
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
2004 Jan 21
15
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Jan 21
16
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R44/01/pp17
Date of release: 2004 Jan 21
Document order number: 9397 750 12474
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