74ABT5074N [NXP]
Synchronizing dual D-type flip-flop with metastable immune characteristics; 同步双D型触发器具有亚稳态的免疫特性
| 型号： | 74ABT5074N |
| 厂家： | 
NXP |
| 描述： | Synchronizing dual D-type flip-flop with metastable immune characteristics |
| 文件： | 总7页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop
with metastable immune characteristics
74ABT5074
FEATURES
PIN CONFIGURATION
• Metastable immune characteristics
RD0
D0
1
2
3
4
5
14
V
CC
• Pin compatible with 74F74 and 74F5074
13 RD1
12 D1
• Typical f
= 200MHz
MAX
CP0
SD0
Q0
• Output skew guaranteed less than 2.0ns
11 CP1
10 SD1
• High source current (I = 15mA) ideal for clock driver
OH
applications
Q0
6
7
9
8
Q1
Q1
• Output capability: +20mA/–15mA
• Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
GND
SA00001
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
PIN DESCRIPTION
PIN NUMBER
2, 12
SYMBOL
NAME AND FUNCTION
Data inputs
DESCRIPTION
D0, D1
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
3, 11
CP0, CP1 Clock inputs (active rising edge)
SD0, SD1 Set inputs (active-Low)
4, 10
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. Data must be stable
just one setup time prior to the low-to-high transition of the clock for
guaranteed propagation delays.
1, 13
RD0, RD1 Reset inputs (active-Low)
Data outputs (active-Low),
non-inverting
5, 9
6, 8
Q0, Q1
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive-going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
Data outputs (active-Low),
inverting
Q0, Q1
7
GND
Ground (0V)
The 74ABT5074 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the
74ABT5074 are:
14
V
CC
Positive supply voltage
7
τ
94ps and T 1.3 × 10 sec
o
where τ represents a function of the rate at which a latch in a
metastable state resolves that condition and T represents a
0
function of the measurement of the propensity of a latch to enter a
metastable state.
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
2.8
2.4
PLH
PHL
C = 50pF; V = 5V
ns
L
CC
CPn to Qn or Qn
Input capacitance
Total supply current
C
V = 0V or V
I CC
3
2
pF
IN
I
Outputs disabled; V =5.5V
µA
CC
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40°C to +85°C
ORDER CODE
74ABT5074N
74ABT5074D
74ABT5074DB
74ABT5074PW
DRAWING NUMBER
SOT27-1
14-pin plastic DIP
14-pin plastic SOL
–40°C to +85°C
SOT108-1
14-pin plastic shrink small outline SSOP Type II
14-pin plastic thin shrink small outline (TSSOP) Type I
–40°C to +85°C
SOT337-1
–40°C to +85°C
SOT402-1
1
December 15, 1994
853-1775 14470
Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop
with metastable immune characteristics
74ABT5074
LOGIC SYMBOL
IEC/IEEE SYMBOL
2
12
4
3
2
1
S
5
6
D0 D1
3
4
CP0
SD0
RD0
CP1
SD1
RD1
C1
1D
R
1
11
10
13
10
11
12
13
S
9
8
C2
2D
Q0 Q0 Q1 Q1
R
5
6
9
8
V
= Pin 14
CC
GND = Pin 7
SA00002
SA00003
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MODE
4, 10
SD
SD
L
RD
H
L
CP
X
X
X
↑
D
X
X
X
h
l
Q
H
Q
L
Asynchronous set
Asynchronous reset
Undetermined*
Load ”1”
5, 9
1, 13
RD
Q
Q
H
L
L
H
L
L
H
6, 8
3, 11
CP
H
H
H
H
H
H
L
↑
L
H
Load ”0”
2, 12
D
H
↑
X
NC
NC
Hold
NOTES:
H = High voltage level
V
= Pin 14
CC
GND = Pin 7
h
=
High voltage level one setup time prior to low-to-high clock
transition
SF00048
L
l
=
=
Low voltage level
Low voltage level one setup time prior to low-to-high clock
transition
NC= No change from the previous setup
X
↑
↑
*
=
=
=
=
Don’t care
Low-to-high clock transition
Not low-to-high clock transition
This setup is unstable and will change when either set or
reset return to the high level
2
December 15, 1994
Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop
with metastable immune characteristics
74ABT5074
After determining the T and τ of the flop, calculating the mean time
METASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term ‘metastable immune’ to
describe characteristics of some of the products in its family. By
running two independent signal generators (see Figure 1) at nearly
the same frequency (in this case 10MHz clock and 10.02MHz data)
the device-under-test can often be driven into a metastable state. If
the Q output is then used to trigger a digital scope set to infinite
persistence the Q output will build a waveform. An experiment was
run by continuously operating the devices in the region where
metastability will occur.
0
between failures (MTBF) is simple. Suppose a designer wants to
use the 74ABT5074 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74ABT5074 7 nanoseconds after the clock
edge. He simply plugs his number into the following equation:
τ
(t’/ )
MTBF = e
/ T *f *f
O C I
In this formula, f is the frequency of the clock, f is the average
C
I
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ > h, h being the normal propagation delay). In
this situation the f will be twice the data frequency of 20 MHz
I
because input events consist of both of low and high transitions.
15
2
Multiplying f by f gives an answer of 10 Hz . From Figure 2 it is
SIGNAL
GENERATOR
I
C
TRIGGER
DIGITAL
D
Q
10
clear that the MTBF is greater than 10 seconds. Using the above
formula the actual MTBF is 1.69 × 10 seconds or about 535 years.
10
SCOPE
SIGNAL
GENERATOR
Q
INPUT
CP
SA00004
Figure 1. Test Setup
E6
E8
E10
E12
E14 E15 = fc*fi
E13
E12
10,000 YEARS
100 YEARS
ONE YEAR
ONE WEEK
E11
E10
E9
MTBF
(SECONDS)
E8
E7
E6
E5
4
5
6
7
8
t’ (NANOSECONDS)
τ
(t’/ )
7
V
CC
= 5V, T
= 25°C, τ =94ps, To = 1.3x10 sec MTBF = e
/T *f *f
O C I
amb
SA00005
Figure 2. Mean Time Between Failures (MTBF) versus t’
3
December 15, 1994
Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop
with metastable immune characteristics
74ABT5074
TYPICAL VALUES FOR τ AND T AT VARIOUS V S AND TEMPERATURES
0
CC
T
amb
= –40°C
T
amb
= 25°C
T = 85°C
amb
V
CC
τ
T
0
τ
T
τ
T
0
0
6
6
9
5.5V
5.0V
4.5V
84ps
84ps
89ps
1.0 × 10 sec
93ps
94ps
103ps
3.8 × 10 sec
89ps
106ps
115ps
1.5 × 10 sec
8
7
6
2.7 × 10 sec
1.3 × 10 sec
2.2 × 10 sec
9
7
6
1.0 × 10 sec
2.1 × 10 sec
4.4 × 10 sec
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
CC
I
IK
DC supply voltage
V
mA
V
DC input diode current
V < 0
I
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
Output in Off or High state
Output in Low state
–0.5 to +5.5
40
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
0
MAX
V
CC
DC supply voltage
5.5
V
V
V
I
Input voltage
V
CC
V
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
2.0
V
IH
V
0.8
–15
20
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
Input transition rise or fall rate
0
10
T
amb
Operating free-air temperature range
–40
+85
4
December 15, 1994
Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop
with metastable immune characteristics
74ABT5074
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25°C
T
amb
= –40°C to +85°C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
V
Input clamp voltage
V
V
= 4.5V; I = –18mA
–0.9
–1.2
–1.2
V
V
IK
CC
IK
= 4.5V; I = –15mA;
CC
OH
V
OH
High-level output voltage
2.5
2.9
2.5
V = V or V
I
IL
IH
V
= 4.5V; I = 20mA;
OL
CC
V
OL
Low-level output voltage
0.35
0.5
0.5
V
V = V or V
I
IL
IH
I
Input leakage current
V
V
V
V
V
= 5.5V; V = GND or 5.5V
±0.01
±5.0
–75
2
±1.0
±100
–180
50
±1.0
±100
–180
50
µA
µA
mA
µA
I
CC
CC
CC
CC
CC
I
I
Power-off leakage current
= 0.0V; V or V v 4.5V
OFF
O
I
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–50
O
I
Quiescent supply current
Additional supply current
= 5.5V; V = GND or V
I CC
CC
= 5.5V; one input at 3.4V,
∆I
CC
0.25
500
500
µA
2
per input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
T
V
= +25°C
= +5.0V
T
V
= –40 to +85°C
= +5.0V ±0.5V
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
1
1
180
250
150
ns
ns
max
t
t
Propagation delay
CPn to Qn or Qn
1.0
1.0
2.8
2.4
3.9
3.5
1.0
1.0
4.5
3.7
PLH
PHL
t
t
Propagation delay
SDn, RDn to Qn or Qn
1.0
1.0
3.5
3.1
4.6
4.2
1.0
1.0
5.5
4.7
PLH
PHL
2
4
ns
ns
1, 2
Output skew
t
1.5
2.0
sk(o)
CPn to Qn to Qn
NOTES:
1. | t actual - t actual | for any output compared to any other output where N and M are either LH or HL.
PN
PM
2. Skew times are valid only under same test conditions (temperature, V , loading, etc.).
CC
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
T
V
= +25°C
= +5.0V
T
V
= –40 to +85°C
= +5.0V ±0.5V
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
MIN
TYP
MIN
t (H)
t (L)
s
Setup time, High or Low
Dn to CPn
2.5
2.5
1.5
1.5
2.5
2.5
s
1
1
ns
ns
t (H)
Hold time, High or Low
Dn to CPn
0
0
–1.4
–1.4
0
0
h
t (L)
h
t
t
(H)
(L)
CPn pulse width,
high or low
1.5
2.4
0.6
1.8
1.5
2.9
w
w
1
2
3
ns
ns
ns
t
(L)
SDn or RDn pulse width, low
2.0
2.4
1.3
1.3
2.2
2.8
w
Recovery time
SDn or RDn to CPn
t
rec
5
December 15, 1994
Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop
with metastable immune characteristics
74ABT5074
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
The shaded areas indicate when the input is permitted to change for the predictable output performance.
Dn
V
V
V
V
M
M
M
M
V
V
M
SDn
RDn
M
t (L)
s
t (L)
h
t (H)
s
t (H)
h
f
MAX
t
w
(L)
t (L)
w
t
w
(H)
t
w
(L)
V
V
M
M
CPn
V
V
V
M
M
M
t
t
t
PLH
PHL
t
t
t
PLH
PHL
Qn
Qn
V
V
V
V
M
M
M
M
Qn
Qn
V
V
V
M
M
M
PLH
t
PHL
PLH
t
PHL
V
M
SA00008
SA00009
Waveform 1. Propagation Delay for Data to Output,
Data Setup Time and Hold Time, and Clock Width
Waveform 2. Propagation Delay for Set and Reset to Output,
Set and Reset Pulse Width
SDn or RDn
Qn, Qn
Qn, Qn
V
V
M
M
t
t
(0)
REC
SK
CPn
V
V
M
M
SA00010
SA00011
Waveform 3. Recovery Time for Set or Reset to Output
Waveform 4. Output Skew
6
December 15, 1994
Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop
with metastable immune characteristics
74ABT5074
TEST CIRCUIT AND WAVEFORM
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
R
L
C
L
R
T
=
=
=
Load resistor;
see AC CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
Input Pulse Definition
INPUT PULSE REQUIREMENTS
FAMILY
rep. rate
t
t
t
F
amplitude
w
R
of
OUT
2.5ns 2.5ns
74F
3.0V
1MHz
500ns
SA00058
7
December 15, 1994
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