PS4530 [PERICOM]
Precision 8-Ch, 2-Ch, Latched Analog Multiplexers/Switches; 高精度8通道， 2通道，锁存模拟多路复用器/开关
| 型号： | PS4530 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Precision 8-Ch, 2-Ch, Latched Analog Multiplexers/Switches |
| 文件： | 总16页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PS4530/PS4531/PS4532
Precision 8-Ch, 2-Ch, Latched
Analog Multiplexers/Switches
Features
Description
• Low On-Resistance (60 Ohm typ.) Minimizes Distortion
PS4530/PS4531/PS4532 are low voltage CMOS analog ICs config-
ured as an 8-channel multiplexer (mux) (PS4530), two 4-channel
muxes (PS4531), and three single-pole/double-throw switches
(PS4532). These devices are pin compatible with the industry
standard 74H4351/74HC4352/74HC4353. All devices have two
complementary switch-enable inputs and address latching.
and Error Voltages
• Single-Supply Operation (+2.0V to 12.0V)
• Dual-Supply Operation (± 2.0V to ± 6.0V)
• Improved Second Sources for MAX4530/MAX4531/MAX4532
• 75 Ohm On-Resistance with ±5V supplies
• 150 Ohm On-Resistance with ±5V supply
• TTL/CMOS Logic Compatible
• Fast Switching Speed, t and t
• Break-Before-Make action eliminates momentary crosstalk
• Rail-to-RailAnalog Signal Range
The PS4530/PS4531/PS4532 operate from a single supply of +2V to
+12V, or from dual supplies of ±2V to ±6V. On-resistance (150Ohm
max.) is matched between switches to 8Ohm max. Each switch can
= 150ns & 120ns at ±4.5V
ON
OFF
handle rail-to-rail analog signals. Off-leakage current is only 1nA
o
at T = +25°C and 50nAat T = +85 C.
A
A
All digital inputs have 0.8V and 2.4V logic thresholds, ensuring
both TTL-logic and CMOS-logic compatibility when using ±5V or
a single +5V supply.
• Low Power Consumption, <1µW
• Narrow SOIC, and SSOPPackages Minimize BoardArea
Applications
• Data Acquisition Systems
• Audio Switching and Routing
• Test Equipment
• PBX, PABX
• Telecommunication Systems
• Battery-Powered Systems
Functional Block Diagrams and Pin Configurations
Top View
PS4531
Top View
PS4532
Top View
PS4530
V+
V+
V+
20
19
20
19
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
20
19
NO0B
NO1B
N.C.
NOB
NCB
NO1
NO3
N.C.
COM
NO7
NO5
EN1
NO1A
COMB
NO2
18 NO2A
17
18 COMC
18 NO4
17
N.C.
COMB
NO3B
NO2B
EN1
NOA
COMA
NCA
17
16
15
14
13
12
COMA
NOC
NCC
ADDC
N.C.
NO0
16 NO0A
15 NO3A
16 NO6
15 ADDC
EN1
N.C.
14
N.C.
14
Logic
Logic
Logic
13
13
EN2
V–
EN2
V–
EN2
N.C.
ADDB
ADDB
ADDA
ADDB
12
12
ADDA
ADDA
GND 10
GND 10
GND 10
11 LE
11 LE
11 LE
PS4531
PS4532
PI5A4530
NARROW DIP/WIDE SO
NARROW DIP/WIDE SO
NARROW DIP/WIDE SO
PS8591D
11/17/04
1
PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
TruthTable
ADDRESS BITS
ON SWITCHES
LE
EN2 EN1
ADDC*
ADDB
ADDA
PS4530
PS431
PS4532
Last address
0
X
X
1
0
0
X
1
X
X
X
X
X
X
X
X
X
Last address
Last address
All switches open
All switches open
All switches open
All switches open
All switches open
All switches open
X
COMA-NCA,
COMB-NCB,
COMC-NCC
COMA-NO0A,
COMB-NO0B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
COM-NO0
COM-NO1
COM-NO2
COM-NO3
COM-NO4
COM-NO5
COM-NO6
COM-NO7
COMA-NOA,
COMB-NCB,
COMC-NCC
COMA-NO1A,
COMB-NO1B
COMA-NCA,
COMB-NOB,
COMC-NCC
COMA-NO2A,
COMB-NO2B
COMA-NOA,
COMB-NOB,
COMC-NCC
COMA-NO3A,
COMB-NO3B
COMA-NCA,
COMB-NCB,
COMC-NOC
COMA-NO0A,
COMB-NO0B
COMA-NOA,
COMB-NCB,
COMC-NOC
COMA-NO1A,
COMB-NO1B
COMA-NCA,
COMB-NOB,
COMC-NOC
COMA-NO2A,
COMB-NO2B
COMA-NOA,
COMB-NOB,
COMC-NOC
COMA-NO3A,
COMB-NO3B
X = Don’t Care *ADDC not present of PS4531.
Note:
NO_ and COM_ pins are identical and interchangeable. Either may be considered an input or an output;
signals pass equally well in either direction. LE is independent of EN1 and EN2.
PS8591D
11/17/04
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PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Voltages Referenced to V–
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
Thisisastressratingonlyandfunctionaloperationofthe
device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
V+ ................................................................................................. –0.3Vto+13V
Voltage into Any Terminal(1)
or ±20mA (whichever occurs first) .......................................–0.3Vto(V++0.3V)
Continuous Current into Any Terminal ................................................... ±20mA
PeakCurrent, NO, NC, orCOM_
(pulsed at 1ms, 10% duty cycle .............................................................. ±40mA
ESDperMethod3015.7 ........................................................................... >2000V
Continuous Power Dissipation (TA = +70°C)
SO(derate10.00mW/°Cabove+70°C) .................................................. 800mW
SSOP(derate8.00mW/°Cabove+70°C) ............................................... 640mW
Operating Temperature Ranges
PS453_C_P ................................................................................... 0°Cto+70°C
PS453_E_P ............................................................................... –40°Cto+85°C
Storage Temperature Range ..................................................... –65°Cto+150°C
Lead Temperture (soldering, 10s ............................................................... +30°C
Note:
Voltages exceeding V+ or V– on any signal terminal are clampled by internal diodes.
Limit forward-diode current to maximum currant rating.
PS8591D
11/17/04
3
PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
ElectricalSpecifications-DualSupplies
(V+ = +5V ±10%, V– = –5V ±10%, GND = 0V, VADD_H = VEN_H = VLE = 2.4V, VADD_L = VEN_L = 0.8V, TA = TMIN to TMAX
unless otherwise noted)
,
Parameter
Symbol
Conditions
Min(2) Typ(2) Max(2) Units
Switch
VCOM, VNO,
VNC_
Analog Signal Range
Note(3)
V–
V+
35
45
V
TA = +25°C
20
INO = 2mA, VCOM = ±3.5V,
V+ = 4.5V, V– = –4.5V
Channel On Resistance
RON
TA = TMIN to TMAX
TA = +25°C
6
8
8
10
6
On-Resistance Matching
Between Channals(4)
INO = 2mA, VCOM = ±3.5V,
V+ = 4.5V, V– = –4.5V
Ohm
∆RON
TA = TMIN to TMAX
TA = +25°C
INO = 2mA,
On -Resistance Flatnesss(5)
NO-Off Leakage Current(6)
RFLAT(ON) VCOM = –3V,0V, +3V;
V+ = 5V; V– = –5V
TA = TMIN to TMAX
TA = +25°C
8
–80
–100
–80
0.01
0.01
0.01
80
VNO = ±4.5V, VCOM = ±4.5V,
INO(OFF)
V+ = 5.5V, V– = –5.5V
TA = TMIN to TMAX
TA = +25°C
100
80
VCOM = ±4.5V, VNO ±4.5V,
V+ = 5.5V, V– = –5.5V
PS4530
TA = TMIN to TMAX
TA = +25°C
–100
–80
100
80
COM-Off Leakage
Current(6)
ICOM(OFF)
VCOM = ±4.5V, VNO ±4.5V,
V+ = 5.5V, V– = –5.5V
PS4531,
PS4532
nΑ
TA = TMIN to TMAX
–100
100
TA = +25°C
–80
–100
–80
0.01
0.01
80
100
80
PS4530
VCOM = ±4.5V,
TA = TMIN to TMAX
TA = +25°C
COM-On Leakage
Current(6)
ICOM(ON) V+ = 5.5V,
V– = –5.5V
PS4531,
PS4532
TA = TMIN to TMAX
–100
100
PS8591D
11/17/04
4
PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
ElectricalSpecifications-DualSupplies(continued)
(V+ = +5V ±10%, V– = –5V ±10%, GND = 0V, VADD_H = VEN_H = VLE = 2.4V, VADD_L = VEN_L = 0.8V, TA = TMIN to TMAX
,
unless otherwise noted)
Parameter
Symbol
Conditions
Min(2) Typ(2) Max(2) Units
Digital Logic Input
VADD_H, VEN_H,
VLE
Logic High Threshold
Logic Low Threshold
TA = TMIN to TMAX
TA = TMIN to TMAX
2.4
V
V
ADD_H, VEN_H,
0.8
VLE
Input Current with
Input Voltage High
IADD_H, IEN_H,
ILE
VADD_H = 2.4V, VADD_L = 0.8V
0.01
–0.1
0.1
µΑ
Input Current with
Input Voltage Low
IADD_L, IEN_L,
ILE
VADD_H = 2.4V, VADD_L = 0.8V
Supply
Power Supply Range
V+, V–
I+
±2.0
–1
±6
1
V
TA = +25°C
0.001
0.001
VEN = VADD_ = VLE = 0V/V+, V+
= 5.5V, V– = –5.5V
Positive Supply Current
Negative Supply Current
TA = TMIN to TMAX
TA = +25°C
–10
–1
10
1
VEN = VADD_ = VLE = 0V/V+, V+
= 5.5V, V– = –5.5V
I–
TA = TMIN to TMAX
–10
10
TA = +25°C
–1
0.01
60
1
VEN = VADD_ = VLE = 0V/V+, V+
= 5.5V, V– = –5.5V
IGND Supply Current
Dynamic
IGND
TA = TMIN to TMAX
–10
10
TA = +25°C
150
250
Transition Time
tTRANS
tBBM
Figure 1
Figure 3
Figure 2
TA = TMIN to TMAX
TA = +25°C
Break-Before-Make Interval
Enable Turn-On Time
4
10
10
TA = +25°C
150
250
100
150
tON(EN)
TA = TMIN to TMAX
TA = +25°C
40
Enable Turn-Off Time
tOFF(EN)
Figure 2
Figure 4
Figure 6
Figure 5
TA = TMIN to TMAX
TA = +25°C
ns
50
60
0
Setup Time, Channel
Select to Latch Enable
tS
TA = TMIN to TMAX
TA = +25°C
Hold Time,Latch Enable
to Channel Select
tH
TA = TMIN to TMAX
TA = +25°C
0
60
70
Pulse Width
Latch Enable
tMPW
TA = TMIN to TMAX
Charge Injection(3)
Off Isolation(7)
Q
1.5
5
pC
dB
VEN2 = 0V, RL = 1kOhm
f = 1 MHz
VISO
–65
TA = +25°C
VEN1 = 0V, REN2 = 2.4V,
f = 1 MHz, VGEN = 1Vp-p,
RL = 1kOhm
Crosstalk Between Channels
VCT
–92
PS8591D
11/17/04
5
PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
ElectricalSpecifications-DualSupplies(continued)
(V+ = +5V ±10%, V– = –5V ±10%, GND = 0V, VADD_H = VEN_H = VLE = 2.4V, VADD_L = VEN_L = 0.8V, TA = TMIN to TMAX
unless otherwise noted)
,
Parameter
Symbol
Conditions
Min(2) Typ(2) Max(2) Units
Distortion, THD
0.025
Logic Input
Capacitance
CIN
f = 1 MHz
3
NO-Off Capacitance
CNO(OFF) f = 1 MHz, VEN = VCOM = 0V
3
PS4530
15
TA = +25°C
f = 1 MHz,
pF
COM-Off Capacitance
CCOM(OFF)
PS4531
PS4532
PS4530
PS4531
PS4532
9
VEN2 = VCOM = 0V
6
26
20
17
f = 1 MHz,
COM-On Capacitance
CCOM(ON)
VEN1 = VCOM = 0V
VEN2 = 2.4V
ElectricalCharacteristics-Single5VSupply
(V+ = +5V ±10%, V– = –0V, GND = 0V, VADD_H = VEN_H = VLE = 2.4V, VADD_L = VEN_L = 0.8V, TA = TMIN to TMAX
unless otherwise noted)
,
Parameter
Symbol
Conditions
Min(2) Typ(2) Max(2) Units
Switch
Analog Signal Range
VCOM , VNO Note(3)
0
V+
65
75
V
TA = +25°C
25
1
INO = 1mA, VCOM = 3.5V
V+ = 4.5V
On-Resistance
RON
TA = TMIN to TMAX
TA = +25°C
On-Resistance
Matching Between
Channels (3,4)
8
INO = 1mA, VCOM = 3.5V
V+ = 4.5V
Ohm
∆RON
RFLAT
TA = TMIN to TMAX
12
INO = 1mA, VCOM = 3V,2/V,1V,
V+ = 4.5V
On-Resistance Flatness
TA = +25°C
4
TA = +25°C
–80
–100
–80
80
100
80
VNO = 4.5V, VCOM = 4.5V, 1V,
V+ = 4.5V
NO-Off Leakage
Current (8)
INO(OFF)
TA = TMIN to TMAX
TA = +25°C
PS4530
VCOM = 4.5V, 1V;
VNO = 1V, 4.5V;
V+ = 5.5V
TA = TMIN to TMAX
TA = +25°C
–100
–80
100
80
COM-Off Leakage
Current (8)
ICOM(OFF)
PS453,
PS4532
nA
TA = TMIN to TMAX
TA = +25°C
–100
–80
100
80
PS4530
TA = TMIN to TMAX
TA = +25°C
–100
–80
100
80
COM-On Leakage
Current (8)
ICOM(ON)
PS4531,
PS4532
TA = TMIN to TMAX
–100
100
PS8591D
11/17/04
6
PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
ElectricalCharacteristics-Single5VSupply
(V+ = +5V ±10%, V– = –0V, GND = 0V, VADD_H = VEN_H = VLE = 2.4V, VADD_L = VEN_L = 0.8V, TA = TMIN to TMAX, unless otherwise noted)
Parameter
Symbol
Conditions
Min(2) Typ(2) Max(2) Units
Digital Logic Input
VADD_H,
Logic-High Threshold
Logic-Low Threshold
2.4
VEN_H, VLE
TA = TMIN to TMAX
V
VADD_L,
0.8
VEN_L, VLE
Input Current with
Input Voltage High
IADD_H,
IEN_H, ILE
VH = 2.4V, VL = 0.8V
–0.1
0.1
µΑ
Input Current with
Input Voltage Low
IADD_L,
IEN_L, ILE
Supply
Positive-Supply Range
2.0
–1.0
–10
–1.0
–10
–1.0
–10
12
1.0
10
V
TA = +25°C
Positive-Supply Current
Negative-Supply Current
I+
I–
TA = TMIN to TMAX
TA = +25°C
1.0
10
VEN_ = VADD = VLE = 0V, V+;
V+ = 5.5V; V– = 0V
µΑ
TA = TMIN to TMAX
TA = +25°C
1.0
10
IGND Supply Current
Dynamic
IGND
TA = TMIN to TMAX
TA = +25°C
90
200
250
Transition Time
tTRANS
tBBM
Figure 1, VNO =3V
Figure 3 (3)
TA = TMIN to TMAX
TA = +25°C
Break-Before-Make Interval
Enable Turn-On Time(3)
10
20
TA = +25°C
100
200
250
100
125
tON(EN)
Figure 2
TA = TMIN to TMAX
TA = +25°C
40
Enable Turn-Off Time(3)
tOFF(EN)
Figure 3
TA = TMIN to TMAX
TA = +25°C
ns
50
60
0
Set-Up Time, Channel
Select to Latch Enable
tS
TA = TMIN to TMAX
TA = +25°C
Hold Time, Latch Enable
to Channel Select
tH
Figure 7
TA = TMIN to TMAX
TA = +25°C
0
60
70
Pulse Width, Latch Enable
Charge Injection(3)
tMPW
Q
TA = TMIN to TMAX
TA = +25°C
Figure 7, CL = 1nF, VNO = 0V
1.5
5
pC
PS8591D
11/17/04
7
PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
ElectricalCharacteristics-Single3VSupply
(V+ = +2.7V to 3.6V, V– = –0V, GND = 0V, VADD_H = VEN_H = VLE = 2.4V, VADD_L = VEN_L = 0.5V, TA = TMIN to TMAX, unless otherwise noted)
Parameter
Symbol
Conditions
Min(2) Typ(2) Max(2) Units
Switch
Analog Signal Rnage
VANALOG
RON
Note 3
0
V+
185
250
V
TA = +25°C
75
INO = 1mA, VCOM = 1.5V
V+ = 2.7V
On-Resistance
Ohm
TA = TMIN to TMAX
Dynamic
Figure 1, VIN = 2.4V
Transistion Time(3)
tTRANS
tON(EN)
tOFF(EN)
tS
150
150
60
350
350
150
VNO1 = 1.5V, VNO8 = 0V
Figure 3, VINH = 2.4V
VINL = 0V, VNO1 = 1.5V
Enable Turn-On Time(3)
Enable Turn-Off Time(3)
Figure 3, VINH = 2.4V
VINL = 0V, VNO1 = 1.5V
TA = +25°C
ns
Set-Up Time, Channel
Select to Latch Enable
100
Note 3
Hold Time, Latch Enable
to Channel Select
tH
0
Pulse Width, Latch Enable
tMPW
120
Notes:
2. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum,
is used in this data sheet.
3. Guaranteed by design
4. ∆RΟΝ = RΟΝ (max) - RΟΝ (min)
5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured over the specified
analog ranges, i.e., VNO = 3V to 0V and 0V to –3V.
6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at TA = +25ºC.
7. Worst-case isolation is on channel 4 because of its proximity to the COM pin.
Off isolation = 20log VCOM/VNO, VCOM = output, VNO = input to off switch
8. Leakage testing at single supply is guaranteed by testing with dual supplies.
PS8591D
11/17/04
8
PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
Applications Information
Power-Supply Considerations
Overview
The PS4530/PS4531/PS4532 construction is typical of most CMOS V+ reaches +12V, the threshold is about 3.1V – above the TTL
analog Switches. They have three supply pins: V+, V, and GND. V+ guaranteed, high-level minimum of 2.8V, but still compatible with
and V- drive the the internal CMOS switches and set the limits of CMOS outputs.
the analog voltage on any switch. Reverse ESD-protection diodes
are internally connected between each analog-signal pin and both
V+ and V-. One of these diodes conducts if any signal exceeds V+
or V-. During normal operation, these and other reverse-biased
ESD diodes leak, forming the only current drawn from V+ or V–.
Virtually all of the analog leakage current comes from the ESD
diodes. Although the ESD diodes on a given signal pine are iden-
tical and therefore fairly well balanced, they are reverse biased
differently. Each is biased by either V+ or V- and the analog signal.
This means their leakages vary as the signal varies. The difference
in the two diode leakages to the V+ and V– pins constitutes the
analog-signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the other
switch terminal. For this reason, both sides of a given switch can
show leakage currents of either the same or opposite polarity.
Bipolar Supplies
The PS4530/PS4531/PS4532 operate with bipolar supplies between
±2.0V and ±6V. The V+ and V- supplies need not be symmetrical,
but their sum cannot exceed the +13V absolute maximum rating.
Single Supply
The PS4530/PS4531/PS4532 operate from a single supply between
+2V and 12V when V- is connected to GND. All of the bipolar
precautions must be observed. At room temperature, they actually
work with a single supply at, near, or below +1.7V, although as
supply voltage decreases, switch on-resistance and switching times
become very high.
High-Frequency Performance
In 50Ohm systerns, signal response is reasonably flat up to 50MHz
(see Typical Operating Characteristics). Above 20MHz, the on
response has several minor peaks that are highly layout depen-
dent. The problem is not in turning the switch on, but in turning it
off. The off-state switch acts lilke a capacitor and passes higher
frequencies with less attenuation. At 10MHz, off isolation is about
–65dB in 50Ohm systems, becoming worse (approximately 21dB
per decade) as frequency increases. Higher circuit impedances
also make off isolation worse. Adjacent channel attenuation is
about 3dB above that of a bare IC socket, and is due entirely to
capacitive coupling.
The signal paths and GND are not connected.
V+ and GND power the internal logic and logic-level translators,
and set both the input and output logic limits. The logic level
translators convert the logic levels into switched V+ and V- sig-
nals to drive the analog signals’ gates. This drive signal is the only
connection between the logic supplies and signals and the analog
supplies. V+ and V- have ESD-protection diodes to GND.
The logic-level thresholds are TTL/CMOS compatible when
V+ = +5V. As V+ rises, the threshold increases slightly, so when
PS8591D
11/17/04
9
PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
TestCircuits/TimingDiagrams
V+
V+
50%
V
ADD_
LE V+
ADDC
0V
+3V
–3V
NO0
NO1-NO6
ADDB
V
NO0
ADDA
50Ohm
90%
PI5A4530
NO7
0V
V+
EN2
EN1
V
V
COM
OUT
OUT
90%
GND
V-
V
35pF
NO7
300Ohm
V–
t
t
trans
trans
V+
V+
0V
VADD_
50%
LE V+
V
ADDA
ADDB
ADD_
+3V
–3V
NO0
NO1_-NO2_
V
NO0
0V
50Ohm
90%
PI5A4531 NO3_
V+
EN2
EN1
V
COM
OUT
V
OUT
GND
V-
90%
35pF
V
NO3
300Ohm
V–
t
t
trans
trans
V+
VADD_
V+
0V
LE V+
ADD_
50%
V
+3V
–3V
NO_
NC_
ADD_
50Ohm
V
NC_
PI5A4532
90%
V+
EN2
EN1
V
OUT
COM
0V
V
GND
V-
OUT
35pF
90%
300Ohm
V
NO_
V–
t
t
trans
trans
Figure 1.Address Transition Time
PS8591D
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PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
TestCircuits/TimingDiagrams(continued)
V+
V+
50%
V
EN1
LE V+
ADDC
0V
+3V
NO0
ADDB
ADDA
V
NO1-NO7
NO0
90%
PS4530
VEN1
V
V
COM
V–
OUT
OUT
EN1
EN2
V+
300
Ohm
35pF
90%
GND
50Ohm
0V
t
t
ON
V–
OFF
V+
V+
50%
LE V+
V
V
ADDA
ADDB
EN1
+3V
NO0_
0V
NO1_NO2_NO3_
V
NO0
90%
PS4531
VEN
V
COM_
OUT
EN1
EN2
OUT
V+
300
Ohm
35pF
GND
V–
V–
90%
50Ohm
0V
t
t
ON
OFF
V+
V+
0V
50%
LE V+
V
EN1
NO0_
ADD_
V
NO0
NC_
+3V
90%
PS4532
VEN1
V
COM_
OUT
V
EN1
EN2
OUT
V+
300
Ohm
35pF
GND
V–
90%
50Ohm
0V
V–
t
t
ON
OFF
V– = 0V for Single-Supply Operation.
Repeat Test for Each Section
Repeat Test for EN2, with Pulse Inverted and EN1 Connected to GND.
Figure 2. Enable Switching Time
PS8591D
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PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
V+
VADD_
LE V+
ADDC
ADDB
ADDA
NO1-NO7
COM
+3V
50
Ohm
V
OUT
PS4530
V+
EN1
EN2
300
Ohm
35pF
GND
V–
V–
V+
t
t
= <20ns
= <20ns
F
R
V+
0V
V
50%
VADD_
ADD_
LE V+
ADDA
ADDB
NO0_-NO3_
COM
+3V
V
50
NO_
Ohm
90%
V
OUT
PS4531
V
OUT
V+
EN2
EN1
300
Ohm
35pF
GND
V–
V–
0V
t
BBM
V+
VADD_
LE V+
ADD_
NO_-NO3_
COM
50
Ohm
+3V
V
OUT
PS4532
V+
EN2
EN1
300
Ohm
35pF
GND
V–
V–
V– = 0V for Single-Supply Operation.
Repeat Test for Each Section
Figure 3. Break-Before-Make Interval
PS8591D
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PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
V+
LE V+
ADDC
ADDB
ADDA
V+
NO_
VNO =0V
Channel
Select
V
EN1
0V
V
∆V
VEN1
OUT
OUT
COM
VOUT
EN1
EN2
CL = 1000pF
V+
GND
V–
50Ohm
∆V
is the measured voltage resulting from charge-transfer
OUT
V–
error Q when the channel turns off.
Q = ∆V x CL
OUT
V– = 0V for single-supply operation.
Repeat test for each section.
Figure 4. Charge Injection
V+
NETWORK
ANALYZER
LE V+
ADDC
Channel
Select
VOUT
VIN
OFF ISOLATION = 20log
ON LOSS = 20log
ADDB
NO_
ADDA
VIN
50Ohm
50Ohm
VOUT
VIN
MEASUREMENT
REF
VOUT
VOUT
VIN
COM_
EN2
CROSSTALK = 20log
V+
50
Ohm
50
Ohm
EN1
GND
V–
V–
Measurements are standardized against short at socket terminals.
Off isolation is measured between COM_ and OFF NO_ terminal on each switch.
On loss is measured between COM_ and ON terminal on each switch.
Crosstalk (PS4531/PS4532) is measured from one channel (A,B,C) to all other channels.
Signal direction through switch is reversed; worst values are recorded.
Figure 5. Off Isolation, On Loss, and Crosstalk
V+
LE V+
ADDC
Channel
Select
NO_
NO_
ADDB
ADDA
1MHz
CAPACITANCE
ANALYZER
V+
EN2
EN1
COM
GND
V–
V–
Figure 6. NO/COM Capacitance
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PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
V+
VADD_
EN2 V+
ADDC
ADDB
ADDA
NO1-NO7
+3V
50
Ohm
PI5A4530
V
COM
OUT
VLE
LE
300
Ohm
35pF
EN1
GND
V–
50
Ohm
t
MPW
3V
0V
V–
V
LE
50%
t
t
t
H
S
H
V+
3V
V
50%
ADD_
0V
VADD_
EN2 V+
ADDA
ADDB
t
,t
ON OFF
NO1_NO2_NO3_
+3V
3V
50
Ohm
90%
NO0_
V
OUT
PI5A4531
V
OUT
0V
COM_
VLE
LE
300
Ohm
35pF
EN1
GND
V–
50
Ohm
V–
V+
VADD_
EN2 V+
ADD_
NO_
NC_
50Ohm
+3V
PI5A4532
V
OUT
COM_
V–
VLE
LE
EN1
300
Ohm
35pF
GND
50
Ohm
V–
V– = 0V for Single-Supply Operation.
Repeat Test for Each Section
Figure 7. Setup and Hold Times, Minimum LE Width
PS8591D
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PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
Packaging Mechanical: 20-pin SOIC (S)
20
7.40
7.60
.2914
.2992
0.254
0.737
.010
.029
x 45˚
1
.496
.511
12.60
12.99
.0091
.0125
0.23
0.32
0-8˚
0.41
1.27
.016
.050
.020 0.508
.030 0.762
REF
2.35
2.65
.0926
.1043
.394
.419
10.00
10.65
SEATING
PLANE
0.10
0.30
.0040
.0118
.050
BSC
1.27
.013
.020
X.XX
DENOTES CONTROLLING
0.33
0.51
X.XX
DIMENSIONS IN MILLIMETERS
Packaging Mechanical: 20-pin SSOP (H)
20
5.00
5.60
.197
.220
1
0.09
0.25
.004
.009
.272
.295
6.90
7.50
.022
.037
0.55
0.95
.078
2.00
Max
.291
.322
7.40
8.20
SEATING
PLANE
.002
0.050
Min
.0098
Max.
0.25
.0256
BSC
0.65
DENOTES DIMENSIONS
IN MILLIMETERS
X.XX
X.XX
PS8591D
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PS4530/PS4531/PS4532
Precision8-Ch, 2-Ch,LatchedAnalogMultiplexers/Switches
Ordering Information
Ordering Code
PS4530CWP
PS4530CAP
Packaging Code
Package Type
20-pin SOIC
20-pin SSOP
20-pin SOIC
20-pin SSOP
20-pin SOIC
20-pin SSOP
20-pin SOIC
20-pin SSOP
20-pin SOIC
S
H
S
PS4530EWP
PS4530EAP
H
S
PS4531CWP
PS4531CAP
H
S
PS4531EWP
PS4531EAP
H
S
PS4532EWP
Notes:
1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/mechanicals.php
PericomSemiconductorCorporation
2380BeringDrive • SanJose,CA95131•1-800-435-2336 • Fax(408)435-1100• http://www.pericom.com
PS8591D
11/17/04
16
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