PI74FCT377TSX [PERICOM]

D Flip-Flop, FCT Series, 8-Func, 1-Bit, True Output, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOIC-20;
PI74FCT377TSX
型号: PI74FCT377TSX
厂家: PERICOM SEMICONDUCTOR CORPORATION    PERICOM SEMICONDUCTOR CORPORATION
描述:

D Flip-Flop, FCT Series, 8-Func, 1-Bit, True Output, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOIC-20

触发器 时钟
文件: 总3页 (文件大小:41K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
PI74FCT377T  
Fast CMOS Octal D Flip-Flop  
with Clock Enable  
Product Description:  
PericomSemiconductor’sPI74FCTseriesoflogiccircuitsarepro-  
ducedintheCompany’sadvanced 0.6/0.8micron CMOStechnology,  
achieving industry leading speed grades.  
ProductFeatures:  
• ThePI74FCT377TispincompatiblewithbipolarFAST™  
Series at a higher speed and lower power  
consumption  
• TTL input and output levels  
• OctalDflip-flopswithClockEnable  
• Extremelylowstaticpower  
• Hysteresis on all inputs  
• Industrial operating temperature range: –40°C to +85°C  
• Packagesavailable:  
The PI74FCT377T is an 8-bit wide octal designed with eight edge-  
triggered D-type flip-flops with individual D inputs and O outputs.  
When Clock Enable (CE) is LOW, the common buffered Clock  
(CP)loadsallflip-flopssimultaneously. Theregisterisfullyedge-  
triggered. D input state, one setup time before the LOW-to-HIGH  
clock transition, is transferred to the corresponding flip-flop’s O  
output. The CE input must be stable only one setup time prior to  
the LOW-to-HIGH transition for predictable operation.  
– 20-pin173milwideplasticTSSOP(L)  
– 20-pin300milwideplasticDIP(P)  
– 20-pin150milwideplasticQSOP(Q)  
– 20-pin150milwideplasticTQSOP(R)  
– 20-pin300milwideplasticSOIC(S)  
Logic Block Diagram  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
CE  
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
CP  
CP  
CP  
CP  
CP  
CP  
CP  
CP  
CP  
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
Truth Table(1)  
Product Pin Configuration  
Product Pin Description  
Inputs  
Outputs  
ON  
Pin Name  
CE  
Description  
CE  
1
2
3
4
5
6
7
8
9
10  
20 Vcc  
Mode  
CP  
CE  
l
DN  
h
Clock Enable (Active LOW)  
Clock Pulse Input  
Data Inputs  
O0  
D0  
D1  
O1  
O2  
D2  
D3  
O3  
19  
18  
17  
16  
15  
14  
13  
12  
11  
O7  
Load "1"  
Load "0"  
Hold  
H
CP  
20-PIN  
L20  
P20  
Q20  
R20  
S20  
D7  
l
l
L
D0-D7  
O0-O7  
GND  
VCC  
D6  
h
X
X
NC  
NC  
O
O
6
5
Data Outputs  
Ground  
(Do Nothing)  
H
H
D
D
5
4
Power  
1. H = HIGH Voltage Level  
h = HIGH Voltage Level one setup time  
prior to the LOW-to-HIGH Clock  
Transition  
O
4
GND  
CP  
L = LOW Voltage Level  
l = LOW Voltage Level one setup time  
prior to the LOW-to-HIGH Clock  
Transition  
X = Don't Care  
NC = No Change  
= LOW-to-HIGH Clock Transition  
PS2017A 03/11/96  
1
PI74FCT377T  
OCTAL D FLIP-FLOP with CLOCK ENABLE  
Maximum Ratings  
(Above which the useful life may be impaired. For user guidelines, not tested.)  
Note:  
StorageTemperature .................................................................... –65°Cto+150°C  
Ambient Temperature with Power Applied .....................................-40°Cto+85°C  
Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. –0.5Vto+7.0V  
Supply Voltage to Ground Potential (Outputs & D/O Only) ........... –0.5Vto+7.0V  
DC Input Voltage ............................................................................ –0.5Vto+7.0V  
DC Output Current ..................................................................................... 120mA  
Power Dissipation ..........................................................................................0.5W  
Stresses greater than those listed under  
MAXIMUM RATINGS may cause permanent  
damage to the device. This is a stress rating  
only and functional operation of the device at  
these or any other conditions above those  
indicated in the operational sections of this  
specification is not implied. Exposure to  
absolute maximum rating conditions for  
extended periods may affect reliability.  
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5V ± 5%)  
Parameters Description  
TestConditions(1) Min. Typ(2) Max. Units  
Output HIGH Voltage VCC = Min., VIN = VIH or VIL  
VOH  
VOL  
VIH  
VIL  
IIH  
IOH = –15.0 mA  
IOL = 64 mA  
2.4  
3.0  
0.3  
V
V
Output LOW Current  
Input HIGH Voltage  
Input LOW Voltage  
Input HIGH Current  
Input LOW Current  
VCC = Min., VIN = VIH or VIL  
0.55  
Guaranteed Logic HIGH Level  
Guaranteed Logic LOW Level  
VCC = Max.  
2.0  
V
0.8  
1
V
VIN =VCC  
µA  
µA  
V
IIL  
VCC = Max.  
VIN =GND  
–1  
VIK  
IOS  
Clamp Diode Voltage VCC = Min., IIN = –18 mA  
–0.7  
–120  
–1.2  
Short Circuit Current  
Power Down Disable  
Input Hysteresis  
VCC =Max.(3),VOUT =GND  
–60  
mA  
µA  
mV  
IOFF  
VH  
VCC =GND,VOUT =4.5V  
100  
200  
Capacitance (TA = 25°C, f = 1 MHz)  
Parameters(4)  
Description  
Test Conditions  
VIN = 0V  
Typ  
Max.  
Units  
pF  
CIN  
Input Capacitance  
Output Capacitance  
6
8
10  
12  
COUT  
VOUT = 0V  
pF  
Notes:  
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.  
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.  
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.  
4. This parameter is determined by device characterization but is not production tested.  
PS2017A 03/11/96  
2
PI74FCT377T  
OCTAL D FLIP-FLOP with CLOCK ENABLE  
Power Supply Characteristics  
Parameters Description  
Test Conditions(1)  
Min. Typ(2) Max. Units  
ICC  
Quiescent Power  
Supply Current  
VCC = Max.  
VCC = Max.  
VIN = GND  
or VCC  
0.1  
500  
µA  
ICC  
ICCD  
Supply Current per  
Input @ TTL HIGH  
VIN = 3.4V(3)  
0.5  
2.0  
mA  
Supply Current per  
Input per MHz(4)  
VCC = Max., Outputs Open  
CE = GND  
VIN = VCC  
VIN = GND  
0.15  
0.25  
mA/  
MHz  
One Input Toggling  
50% Duty Cycle  
IC  
Total Power Supply  
Current(6)  
VCC = Max., Outputs Open  
fCP = 10 MHZ, 50% Duty Cycle  
CE = GND  
50% Duty Cycle  
One Bit toggling at fI = 5 MHZ  
VIN = VCC  
VIN = GND  
VIN = 3.4V  
VIN = GND  
1.57  
3.5(5)  
mA  
2.0  
3.8  
5.5(5)  
7.3(5)  
VCC = Max., Outputs Open  
fCP = 10 MHZ, 50% Duty Cycle  
CE = GND  
VIN = VCC  
VIN = GND  
VIN = 3.4V  
Eight Bits toggling at fI = 2.5 MHZ VIN = GND  
6.0  
16.3(5)  
50% Duty Cycle  
Notes:  
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.  
2. Typical values are at Vcc = 5.0V, +25°C ambient.  
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.  
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.  
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.  
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC  
IC = ICC + ICC DHNT + ICCD (fCP/2 + fINI)  
ICC = Quiescent Current  
ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)  
DH = Duty Cycle for TTL Inputs High  
NT = Number of TTL Inputs at DH  
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)  
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)  
fI = Input Frequency  
NI = Number of Inputs at fI (All currents are in milliamps and all frequencies are in megahertz.)  
Switching Characteristics over Operating Range  
377T  
Com.  
377AT  
Com.  
377CT  
Com.  
377DT  
Com.  
Parameters  
Description  
Conditions(1)  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
t
t
t
PLH  
PHL  
SU  
PropagationDelay  
C
L
L
= 50 pF  
2.0  
13.0  
2.0  
7.2  
2.0  
5.2  
2.0  
4.5  
ns  
ns  
ns  
ns  
ns  
ns  
CP to O  
N
R
= 500  
Setup Time, HIGH or LOW  
Dn to CP  
2.5  
2.0  
4.0  
1.5  
7.0  
2.0  
1.5  
3.5  
1.5  
6.0  
2.0  
1.5  
3.5  
1.5  
6.0  
2.0  
1.5  
2.0  
1.5  
3.0  
t
t
t
H
Hold Time, HIGH or LOW  
Dn to CP  
SU  
H
Setup Time HIGH or LOW  
CE to CP  
Hold Time HIGH or LOW  
CE to CP  
Clock Pulse Width(3)  
tW  
HIGH or LOW  
Notes:  
1. See test circuit and wave forms.  
2. Minimum limits are guaranteed but not tested on Propagation Delays.  
3. This parameter guaranteed but not production tested.  
PS2017A 03/11/96  
3

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