PI74FCT162H373CTVX [PERICOM]
暂无描述;型号: | PI74FCT162H373CTVX |
厂家: | PERICOM SEMICONDUCTOR CORPORATION |
描述: | 暂无描述 锁存器 |
文件: | 总7页 (文件大小:70K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PI74FCT16373T
PI74FCT162373T
PI74FCT162H373T
Fast CMOS 16-Bit
Transparent Latches
ProductFeatures:
CommonFeatures:
Product Description:
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-
duced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
• PI74FCT16373T,PI74FCT162373T,andPI74FCT162H373Tare
high-speed,
low power devices with high current drive.
• Vcc=5V±10%
• Hysteresis on all inputs
• Packagesavailable:
–48-pin240milwideplasticTSSOP(A)
–48-pin300milwideplasticSSOP(V)
PI74FCT16373TFeatures:
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit "live insertion"
ThePI74FCT16373T,PI74FCT162373T,andPI74FCT162H373T
are 16-bit transparent latches designed with 3-state outputs and are
intended for bus oriented applications. The Output Enable and
Latch Enable controls are organized to operate as two 8-bit latches
orone16-bitlatch. WhenLatchEnable(LE)isHIGH,theflip-flops
appear transparent to the data. The data that meets the set-up time
when LE is LOW is latched. When OE is HIGH, the bus output is
in the high impedance state.
• Typical VOLP (Output Ground Bounce) < 1.0V
atVCC =5V,TA =25°C
PI74FCT162373TFeatures:
The PI74FCT16373T output buffers are designed with a Power-
Off disable allowing “live insertion” of boards when used as
backplane drivers.
• Balanced output drivers: ±24 mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V
atVCC =5V,TA =25°C
The PI74FCT162373T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
PI74FCT162H373TFeatures:
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull-up resistors
The PI74FCT162H373T has “Bus Hold” which retains the input’s
last state whenever the input goes to high-impedance preventing
“floating”inputsandeliminatingtheneedforpull-up/downresistors.
Logic Block Diagram
1OE
1LE
2OE
2LE
1D0
2D0
D
C
D
C
1O0
2O0
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
PS2033A 03/11/96
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PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
Product Pin Description
Truth Table
Inputs(1)
Outputs(1)
PinName
xOE
Description
XDX
H
XOE
L
xLE
H
xOx
H
Output Enable Inputs (Active LOW)
xLE
Latch Enable Inputs (Active HIGH)
Inputs(1)
L
L
H
L
xDx
X
H
X
Z
xOx
3-State Outputs
Ground
GND
VCC
Note: 1. H = High Voltage Level, X = Don’t Care, L = Low
Voltage Level, Z = High Impedance
Power
Note: 1. For the PI74FCT162H373T, these pins have “Bus
Hold.” All other pins are standard, outputs, or I/Os.
Product Pin Configuration
1
OE
1
1
1
LE
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
O
0
1
D
0
1
2
1
O
D
3
GND
GND
4
1
O
O
2
3
1
D
2
3
5
1
1D
6
V
CC
VCC
7
1
O
O
4
5
1D
4
8
1
1D
5
9
GND
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-PIN
V48
A48
1
1
2
2
O
O
O
O
6
7
0
1
1D
1D
2D
2D
6
7
0
1
GND
GND
2
O
O
2
3
2
D
2
3
2
2D
V
CC
VCC
2
O
O
4
5
2D
4
2
2D
5
GND
GND
2
O
O
6
7
2
2
2
D
6
7
2
D
2OE
LE
PS2033A 03/11/96
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PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
MaximumRatings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
StorageTemperature .................................................................... –65°Cto+150°C
Ambient Temperature with Power Applied ....................................–40°Cto+85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. –0.5Vto+7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ........... –0.5Vto+7.0V
DC Input Voltage ............................................................................ –0.5Vto+7.0V
DC Output Current ..................................................................................... 120mA
Power Dissipation ..........................................................................................1.0W
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5.0V ± 10%)
Parameters Description
TestConditions(1)
Min.
Typ(2)
Max.
Units
VIH
VIL
IIH
InputHIGHVoltage
GuaranteedLogicHIGHLevel
GuaranteedLogicLOWLevel
Standard Input, VCC = Max.
StandardI/O,VCC =Max.
Bus Hold Input(4), VCC = Max.
BusHoldI/O(4), VCC = Max.
Standard Input, VCC = Min.
Standard I/O, VCC = Min.
2.0
V
V
Input LOW Voltage
InputHIGHCurrent
InputHIGHCurrent
InputHIGHCurrent
InputHIGHCurrent
Input LOW Current
Input LOW Current
Input LOW Current
Input LOW Current
Bus Hold
Sustain Current
HighImpedance
Output Current
ClampDiodeVoltage
ShortCircuitCurrent
Output Drive Current
Input Hysteresis
0.8
1
1
±100
±100
–1
–1
±100
±100
VIN =VCC
VIN =VCC
VIN =VCC
VIN =VCC
VIN =GND
VIN =GND
VIN = GND
VIN = GND
VIN =2.0V
VIN=0.8V
VOUT =2.7V
VOUT =0.5V
µA
µA
µA
µA
µA
µA
µA
µA
µA
IIH
IIH
IIH
IIL
IIL
IIL
Bus Hold Input(4), VCC = Min.
Bus Hold I/O(4), VCC = Min.
Bus Hold Input(4), VCC = Min.
IIL
IBHH
IBHL
IOZH
IOZL
VIK
IOS
IO
–50
+50
(5)
(5)
VCC =Max.
VCC =Max.
VCC = Min., IIN =–18mA
VCC =Max.(3),VOUT = GND
VCC =Max.(3),VOUT =2.5V
1
–1
–1.2
–200
–180
µA
µA
V
mA
mA
mV
–0.7
–140
–80
–50
VH
100
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. This specification does not apply to bi-directional functionalities with Bus Hold.
PS2033A 03/11/96
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PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
PI74FCT16373T Output Drive Characteristics (Over the Operating Range)
Parameters Description
TestConditions(1)
Min.
Typ(2)
Max.
Units
VOH
OutputHIGHVoltage
VCC =Min.,VIN =VIH orVIL
IOH = –3.0 mA
IOH =–15.0mA
IOH = –32.0 mA
IOL = 64 mA
2.5
2.4
2.0
3.5
3.5
3.0
0.2
—
V
VOL
IOFF
Output LOW Voltage
PowerDownDisable
VCC = Min., VIN = VIH or VIL
VCC =0V,VIN orVOUT ≤4.5V
0.55
±100
V
µA
—
PI74FCT162373T/162H373TOutputDriveCharacteristics(OvertheOperatingRange)
Parameters Description
TestConditions(1)
Min.
Typ(2)
Max.
Units
VOH
VOL
IODL
IODH
OutputHIGHVoltage
VCC =Min.,VIN =VIH orVIL
VCC =Min.,VIN =VIH orVIL
IOH =–24.0mA
IOL = 24 mA
2.4
3.3
0.3
115
–115
V
V
mA
mA
Output LOW Voltage
Output LOW Current
OutputHIGHCurrent
0.55
150
–150
VCC =5V,VIN =VIH OR VIL,VOUT =1.5V(3)
VCC =5V,VIN =VIH OR VIL,VOUT =1.5V(3)
60
–60
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(4)
Description
Test Conditions
Typ
Max.
Units
CIN
Input Capacitance
Output Capacitance
VIN = 0V
4.5
5.5
6
8
pF
pF
COUT
VOUT = 0V
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
PS2033A 03/11/96
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PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
Power Supply Characteristics
Parameters Description
Test Conditions(1)
Min. Typ(2) Max. Units
ICC
Quiescent Power
Supply Current
VCC = Max.
VIN = GND or VCC
0.1
0.5
60
500
µA
∆ICC
ICCD
Supply Current per
Input @ TTL HIGH
VCC = Max.
VIN = 3.4V(3)
1.5
mA
Supply Current per
Input per MHz(4)
VCC = Max.,
Outputs Open
VIN = VCC
VIN = GND
100
µA/
MHz
XOE = GND, XLE = VCC
One Bit Toggling
50% Duty Cycle
IC
Total Power Supply
Current(6)
VCC = Max.,
Outputs Open
VIN = VCC
VIN = GND
0.6
1.5(5)
mA
fI = 10 MHZ
50% Duty Cycle
XOE = GND, XLE = VCC
One Bit Toggling
VIN = 3.4V
VIN = GND
0.9
2.4
2.3(5)
4.5(5)
VCC = Max.,
VIN = VCC
Outputs Open
VIN = GND
fI = 2.5 MHZ
50% Duty Cycle
XOE = GND, XLE = VCC
16 Bits Toggling
VIN = 3.4V
VIN = GND
6.4
16.5(5)
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
PS2033A 03/11/96
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PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
PI74FCT16373T Switching Characteristics over Operating Range
16373T
Com.
16373AT
Com.
16373CT
Com.
16373DT
Com.
16373ET
Com.
Parameters
Description
Conditions(1)
Min Max Min Max Min Max Min Max Min Max Unit
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
SU
PropagationDelay
xDxtoxOx
C
L
L
= 50 pF
1.5
8.0
1.5
5.2
8.5
6.5
5.5
—
1.5
2.0
1.5
1.5
2.0
1.5
5.0
—
4.2
5.5
5.5
5.0
—
1.5
1.5
1.5
1.5
1.5
1.0
3.0
—
3.8
4.0
4.8
4.0
—
1.5
1.5
1.5
1.5
1.0
1.0
3.0
—
3.4
3.7
4.4
4.0
—
ns
ns
ns
ns
ns
ns
ns
ns
R
=500Ω
PropagationDelay
xLE to xOx
2.0 13.0 2.0
1.5 12.0 1.5
Output Enable Time
xOE to xOx
OutputDisableTime(3)
1.5
2.0
1.5
6.0
—
7.5
—
—
—
0.5
1.5
2.0
1.5
5.0
—
xOEtoxOx
Setup Time HIGH
or LOW,
Hold Time HIGH
or LOW, to X
XD
X
to
X
LE
LE
tH
—
—
—
—
XD
X
tW
xLE Pulse Width
HIGH(3)
OutputSkew(4)
—
—
—
—
t
SK(o)
0.5
0.5
0.5
0.5
PI74FCT162373T Switching Characteristics over Operating Range
162373T
Com.
162373AT 162373CT 162373DT 162373ET
Com. Com. Com. Com.
Parameters
Description
Conditions(1)
Min Max Min Max Min Max Min Max Min Max Unit
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
SU
PropagationDelay
xDxtoxOx
C
L
L
= 50 pF
1.5
8.0
1.5
5.2
8.5
6.5
5.5
—
1.5
2.0
1.5
1.5
2.0
1.5
5.0
—
4.2
5.5
5.5
5.0
—
1.5
1.5
1.5
1.5
1.5
1.0
3.0
—
3.8
4.0
4.8
4.0
—
1.5
1.5
1.5
1.5
1.0
1.0
3.0
—
3.4
3.7
4.4
4.0
—
ns
ns
ns
ns
ns
ns
ns
ns
R
=500Ω
PropagationDelay
xLE to xOx
2.0 13.0 2.0
1.5 12.0 1.5
Output Enable Time
xOE to xOx
OutputDisableTime(3)
1.5
2.0
1.5
6.0
—
7.5
—
—
—
0.5
1.5
2.0
1.5
5.0
—
xOEtoxOx
Setup Time HIGH
or LOW,
Hold Time HIGH
or LOW, to X
XD
X
to
X
LE
LE
tH
—
—
—
—
XD
X
tW
xLE Pulse Width
HIGH(3)
OutputSkew(4)
—
—
—
—
t
SK(o)
0.5
0.5
0.5
0.5
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
PS2033A 03/11/96
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PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
PI74FCT162H373T Switching Characteristics over Operating Range
162H373T 162H373AT 162H373CT 162H373DT 162H373ET
Com. Com. Com. Com. Com.
Min Max Min Max Min Max Min Max Min Max Unit
Parameters
Description
Conditions(1)
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
SU
PropagationDelay
xDx to xOx
C
R
L
L
= 50 pF
1.5
8.0
1.5
5.2
8.5
6.5
5.5
—
1.5
2.0
1.5
1.5
2.0
1.5
5.0
—
4.2
5.5
5.5
5.0
—
1.5
1.5
1.5
1.5
1.5
1.0
3.0
—
3.8
4.0
4.8
4.0
—
1.5
1.5
1.5
1.5
1.0
1.0
3.0
—
3.4
3.7
4.4
4.0
—
ns
ns
ns
ns
ns
ns
ns
ns
= 500Ω
Propagation Delay
xLE to xOx
2.0 13.0 2.0
1.5 12.0 1.5
Output Enable Time
xOE to xOx
Output Disable Time(3)
1.5
2.0
1.5
6.0
—
7.5
—
—
—
0.5
1.5
2.0
1.5
5.0
—
xOE to xOx
Setup Time HIGH
or LOW,
Hold Time HIGH
or LOW, to X
X
D
X
to
X
LE
t
t
t
H
—
—
—
—
X
D
X
LE
W
xLE Pulse Width
HIGH(3)
Output Skew(4)
—
—
—
—
SK(o)
0.5
0.5
0.5
0.5
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS2033A 03/11/96
7
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