PI6C3Q991-5IJ [PERICOM]
3.3V Programmable Skew PLL Clock Driver; 3.3V的可编程偏移PLL时钟驱动器
| 型号： | PI6C3Q991-5IJ |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V Programmable Skew PLL Clock Driver |
| 文件： | 总10页 (文件大小：546K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock
Features
Description
PI6C3Q99X family provides following products:
PI6C3Q991:32-pinPLCCversion
PI6C3Q993:28-pinQSOPversion
Inputs are 5V I/O Tolerant
4 pairs of programmable skew outputs
Low skew: 200ps same pair; 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
ThePI6C3Q99Xfamilyisahighfanout3.3VPLL-basedclockdriver
intended for high performance computing and data-communica-
tions applications. A key feature of the programmable skew is the
abilityofoutputstoleadorlagtheREFinputsignal.ThePI6C3Q991
has 8 programmable skew outputs in 4 banks of 2, while the
PI6C3Q993 has 6 programmable skew outputs and 2 zero skew
outputs.Skewiscontrolledby3-levelinputsignalsthatmaybehard-
wiredtoappropriateHIGH-MID-LOWlevels.
Synchronous output enable
Output frequency: 3.75 MHz to 85 MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
3-level inputs for skew and PLL range control
PLL bypass for DC testing
When the GND/sOE pin is held low, all the outputs are synchro-
nously enabled. However, if GND/sOE is held high, all the outputs
except3Q0and3Q1aresynchronouslydisabled.Furthermore,when
the V
/PE is held high, all the outputs are synchronized with the
CCQ
positive edge of the REF clock input. When V
/PE is held low,
CCQ
alltheoutputsaresynchronizedwiththenegativeedgeof REF.Both
devices have LVTTL outputs with 12mA balanced drive outputs.
Externalfeedback,internalloopfilter
12mA balanced drive outputs
LowJitter:<200pspeak-to-peak
Industrial temperature range
Pin-to-pincompatiblewithIDTQS5V991andQS5V993
Availablein32-pinPLCCand28-pinQSOP
PinConfigurations
PI6C3Q991
PI6C3Q993
1
REF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
TEST
2F1
2
V
CCQ
FS
3
4
3
2
1 32 31 30
29
4
3F0
3F1
/PE
2F0
3F1
4F0
4F1
/PE
5
6
7
8
9
2F0
GND/sOE
1F1
5
GND/sOE
1F1
28
27
26
25
24
23
22
21
6
V
CCQ
V
28-Pin
Q
7
1F0
V
CCN
1F0
CCQ
V
32-Pin
8
4Q1
4Q0
GND
3Q1
3Q0
V
CCN
V
CCN
4Q1
4Q0
GND
GND
J
CCN
9
1Q0
1Q1
GND
GND
2Q0
2Q1
10
11
12
13
1Q0
1Q1
GND
GND
10
11
12
13
14
V
14 15 16 17 18 19 20
CCN
FB
PS8449A
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PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver SuperClock
Logic Block Diagrams
PI6C3Q993
PI6C3Q991
GND/sOE
GND/sOE
Skew
1Q0
Skew
1Q0
1Q1
Select
Select
1Q1
3
3
3
3
1F1:0
2F1:0
3F1:0
1F1:0
2F1:0
3F1:0
4F1:0
V
/PE
CCQ
V
/PE
CCQ
Skew
Skew
2Q0
2Q1
2Q0
2Q1
Select
Select
3
3
3
3
REF
FB
REF
FB
PLL
PLL
Skew
Select
Skew
Select
3Q0
3Q1
3Q0
3Q1
3
3
3
3
3
3
FS
FS
Skew
Select
4Q0
4Q1
4Q0
4Q1
3
3
PinDescriptions
Pin Name
REF
Type
Functional Description
IN
IN
Reference Clock input
Feedback Input
FB
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections
(see table 3) remain in effect. Set LOW for normal operation.
TEST(1)
IN
IN
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0
or 3Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and
GND/sOE is HIGH, the nF [1:0] pins act as output disable controls for individual banks when nF [1:0] = LL.
Set GND/sOE LOW for normal operation.
GND/sOE(1)
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock.
VCCQ/PE
nF [1:0]
FS
IN
3-level inputs for selecting 1 of 9 skew taps or frequency range.
Selects appropriate oscillator circuit based on anticipated frequency range. See table 2
4 output banks of 2 outputs, with programmable skew. On the PI6C3Q993 4Q1:0 are fixed zero skew outputs.
Power supply for output buffers
IN
nQ [1:0]
VCCN
VCCQ
GND
OUT
PWR
PWR
PWR
Power supply for phase locked loop and other internal circuitry
Ground
Note:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] =LL functioning as an output disable control for
individual output banks. Skew selections (see Table 3) remain in effect unless nF[1:0] = LL.
PS8449A
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock
ExternalFeedback
ProgrammableSkew
Byprovidingexternalfeedback,thePI6C3Q99Xfamilygivesusers
flexibilitywithregardtoskewadjustment.TheFBsignaliscompared
with the input REF signal at the phase detector in order to drive the
VCO.PhasedifferencescausetheVCOofthePLLtoadjustupwards
or downwards accordingly. An internal loop filter moderates the
response of the VCO to the phase detector. The loop filter transfer
function has been chosen to provide minimal jitter (or frequency
variation) while still providing accurate responses to input fre-
quency changes.
Output skew with respect to the REF input is adjustable to compen-
sate for PCB trace delays, backplane propagation delays or to
accommodaterequirementsforspecialtimingrelationshipsbetween
clocked components. Skew is selectable as a multiple of a time unit
t which is of the order of a nanosecond (see Table 2). There are 9
U
skew configurations available for each output pair. These configu-
rations are choosen by the nF1:0 control pins. In order to minimize
the number of control pins, 3-level inputs (HIGH-MID-LOW) are
used,theyareintendedforbutnotrestrictedtohard-wiring.Undriven
3-level inputs default to the MID level. Where programmable skew
isnotarequirement,thecontrolpinscanbeleftopenforthezeroskew
default setting. The Skew Selection Table (Table 3) shows how to
select specific skew taps by using the nF1:0 control pins.
Table2. PLLProgrammableSkewRangeandResolutionTable
FS = LOW
1/(44xF
FS = MID
1/(26xF
FS = HIGH
1/(16xF )
NOM
Comments
Timing unit calculation (t )
)
)
U
NOM
NOM
(1,2)
VCO frequency range (F
)
15 to 35 MHz 25 to 60 MHz 40 to 85 MHz
NOM
±9.09ns
±49°
±14%
±9.23ns
±83°
±23%
±9.38ns
±135°
±37%
(3)
Skew adjustment range Max.
adjustment
ns Phase degrees
% of cycle time
Example 1, F
Example 2, F
Example 3, F
Example 4, F
Example 5, F
Example 6, F
= 15 MHz
= 25 MHz
= 30 MHz
= 40 MHz
= 50 MHz
= 80 MHz
t = 1.52ns
U
NOM
NOM
NOM
NOM
NOM
NOM
t = 0.91ns
U
t = 1.54ns
U
t = 0.76ns
U
t = 1.28ns
U
t = 0.96ns
U
t = 1.56ns
U
t = 0.77ns
U
t = 1.25ns
U
t = 0.78ns
U
Notes:
1. The device may be operated outside recommended frequency ranges without damage, but functional
operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the
PLL to operate in its sweet spot where jitter is lowest.
2. TheleveltobesetonFSisdeterminedbythenominaloperatingfrequencyoftheVCOandTimeUnitGenerator.
The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their
undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the
output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO
frequencywhenthepartisconfiguredforafrequencymultiplicationbyusingadividedoutputastheFBinput.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used
for feedback, then adjustment range will be greater. For example if a 4t skewed output is used for feedback,
U
all other outputs will be skewed 4t in addition to whatever skew value is programmed for those outputs.
U
Max adjustment range applies to output pairs 3 and 4 where ±6 t skew adjustment is possible and at the
U
lowest F
value.
NOM
PS8449A
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PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver SuperClock
Table 3. Skew Selection Table for Output Pairs
(1)
nF1:0
Skew (Pair #1, #2)
Skew (Pair #3)
Skew (Pair #4)
(2)
LL
4t
Divide by 2
Divide by 2
U
LM
LH
3t
6t
6t
U
U
U
2t
4t
4t
U
U
U
ML
MM
MH
HL
1t
2t
2t
U
U
U
Notes:
1.Programmableskewonpair#4isnotapplicable
forthePI6C993.
2.LLdisablesoutputsifTEST = MIDandGND/
sOE = HIGH.
3.Whenpair#4issettoHH(inverted),GND/sOE
disablespair#4HIGHwhenV
Zero skew
+1t
Zero skew
+2t
Zero skew
+2t
U
U
U
+2t
+4t
+4t
U
U
U
HM
HH
+3t
+6t
+6t
U
U
U
/PE=HIGH,
CCQ
GND/sOEdisablespair#4LOWwhenV
PE=LOW
/
CCQ
(3)
+4t
Divide by 4
Inverted
U
Table 4. Absolute Maximum Ratings
StressesabovethoselistedunderAbsoluteMaximumRatings
maycausepermanentdamagetothedevice.Theseratingsare
stress specifications only and functional operation of the
device at these or any other conditions above those listed in
the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Supply Voltage to ground ........................................................0.5Vto7.0V
DCinputVoltageV .................................................................... 0.5VtoV +0.5V
CC
I
MaximumPowerDissipationatT =85°C,PLCC .........................0.80watts
A
QSOP .......................0.66watts
TSTGStoragetemperature ....................................................65°Cto150°C
Table 5. Recommended Operating Range
PI6C3Q99X
PI6C399X-2
PI6C3Q99X-5
(Commercial)
Symbol
Description
Units
(Industrial)
Min. Max. Min. Max.
Power Supply
Voltage
VCC
TA
3.0
3.6
85
3.0
0
3.6
70
V
Ambient Operating
Temperature
40
°C
PS8449A
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock
Table 6. DC Characteristics Over Operating Range
Symbol
Parameter
Test Condition
Min.
Max.
Units
Guaranteed Logic HIGH
(REF, FB inputs only)
V
IH
Input HIGH Voltage
2.0
Guaranteed Logic LOW
(REF, FB inputs only)
V
Input LOW Voltage
0.8
IL
V
(1)
V
IHH
Input HIGH Voltage
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
0.6
CC
(1)
V
IMM
Input MID Voltage
Input LOW Voltage
V
CC
/2 0.3
V
/2 +0.3
CC
(1)
V
ILL
0.6
5
Input Leakage Current (REF,
FB inputs only)
V
= V or GND,
IN CC
I
IN
V
CC
= Max.
V
= V
HIGH Level
MID Level
LOW Level
200
50
200
IN
CC
3-Level Input DC Current
(TEST, FS, nF1:0)
I
3
V
= V /2
IN
CC
V
IN
= GND
µA
V
Input Pull-Up Current
I
V
= Max., V = GND
100
100
PU
CC
IN
(V
/PE)
CCQ
Input Pull-Down Current
(GND/sOE)
I
PD
V
= Max., V = V
CC IN CC
V
OH
Output HIGH Voltage
Output LOW Voltage
V
CC
= Min., I
OH =
12mA
12mA
2.2
V
OL
V
= Min., I
OL =
0.55
CC
Note:
1.TheseinputsarenormallywiredtoV ,GND,orunconnected.Internalterminationresistorsbiasunconnectedinputs
CC
to V /2. If these inputs are switched, the function and timing of the outputs may glitched, and the PLL may require
CC
an additional t
time before all datasheet limits are achieved.
LOCK
Table7.PowerSupplyCharacteristics
Symbol
Parameter
Test Condition
Typ. Max. Units
V
CC = Max., TEST = Mid., REF = LOW,
ICCQ
Quiescent Power Supply Current
Power Supply Current per Input HIGH(1)
8.0
15
mA
GND/sOE = LOW, All outputs unloaded
∆ICC
ICCD
IC
VCC = Max., VIN = 3.0V
1.0
55
29
42
76
30
90
µA
Dynamic Power Supply Current per Output(1) VCC = Max., CL = 0pF
µA/MHz
Total Power Supply Current(1)
Total Power Supply Current(1)
Total Power Supply Current(1)
VCC = 3.3V, FREF = 20 MHz, CL = 160pF(2)
IC
VCC = 3.3V, FREF = 33 MHz, CL = 160pF(2)
VCC = 3.3V, FREF = 66 MHz, CL = 160pF(2)
mA
IC
Notes:
1. Guaranteed by characterization but not production tested.
2. For 8 outputs each loaded with 20pF.
PS8449A
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PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver SuperClock
Table8. Capacitance (T = 25°C, f = 1 MHz, V =0V)
A
IN
QSOP
PLCC
Units
Typ.
Max.
Typ.
Max.
C
4
6
5
7
pF
IN
VCC
150Ω
150Ω
Output
20pF
tORISE
tOFALL
≤1ns
≤1ns
3.0V
2.0V
Vth=1.5V
0.8V
2.0V
0.8V
tPWH
tPWL
0V
LVTTL Input Test Waveform
LVTTL Output Waveform
AC Test Loads and Waveforms
PS8449A
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock
Table9.SwitchingCharacteristicsOverOperatingRange
PI6C3Q991-2
PI6C3Q993-2
PI6C3Q991-5
PI6C3Q993-5
PI6C3Q991
PI6C3Q993
Description
Units
Symbol
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
F
VCO frequency range
REF pulse width HIGH
see Table 2
see Table 2
see Table 2
NOM
(11)
(11)
t
3.0
3.0
3.0
3.0
3.0
3.0
RPWH
ns
t
REF pulse width LOW
RPWL
t
Programmable skew time unit
see Table 3
see Table 3
0.1
see Table 3
U
(1,2,3)
t
Zero output matched-pair skew (xQ0, xQ1)
0.05 0.20
0.1 0.25
0.25 0.50
0.30 1.2
0.25
0.5
0.7
1.2
0.7
1.0
1.25
0.5
1.2
2.5
3.0
1.8
1.8
0.5
40
0.1
0.3
0.6
1.0
0.7
1.2
0.25
0.75
1.0
1.5
1.2
1.7
1.65
0.7
1.2
3.0
3.5
2.5
2.5
0.5
40
SKEWPR
(1,4)
t
Zero output skew (all outputs) C = 0pF
0.25
0.6
SKEW0
L
(1,5)
t
Output skew (rise-rise, fall-fall, same class outputs)
Output skew (rise-fall, nominal-inverted, divided-divided)
SKEW1
(1,5)
(1,5)
t
0.5
SKEW2
(1,5)
t
Output skew (rise-rise, fall-fall, different class outputs)
Output skew (rise-fall, nominal-divided, divided-inverted)
0.25 0.50
0.50 0.90
0.75
0.5
SKEW3
t
0.5
SKEW4
(1,2,6)
t
Device-to-device skew
ns
DEV
(1,8)
t
PD
REF input to FB propagation delay
0.25
1.2
0
0
0.25
1.2
2.0
2.5
1.8
1.8
0.5
25
0.5
1.2
0
0
0.7
1.2
0
0
(1)
t
Output duty cycle varation from 50%
ODCV
(1,9)
t
Output HIGH time deviation from 50%
PWH
(1,10)
t
Output LOW time deviation from 50%
PWL
(1)
t
Output rise time
0.15
0.15
1.0
1.0
0.15
0.15
1.0
1.0
0.15
0.15
1.5
1.5
ORISE
(1)
t
Output fall time
OFALL
(1,7)
t
PLL lock time
ms
ps
LOCK
RMS
(1)
t
JR
Cycle-to-cycle output jitter
Peak-to-peak
200
200
200
Notes:
1. AlltimingtolerancesapplyforFNOM≥25MHz. Guaranteedbydesignandcharacterization, notsubjectto100%
production testing.
2. Skewisthetimebetweentheearliest andthelatest output transitionamongall outputsforwhichthesamet delay
U
has been selected when all are loaded with the specified load.
3. t
4. t
is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t .
U
SKEWPR
is the skew between outputs when they are selected for 0t .
SKEW0
U
5. Thereare3classesofoutputs:Nominal(multipleoft delay),Inverted(4Q0and4Q1onlywith4F0=4F1=HIGH),
U
andDivided(3Qxand4QxonlyinDivide-by-2orDivide-by-4mode).
6. t DEV is the output-to-output skew between any two devices operating under the same conditions (V , ambient
CC
temperature,airflow,etc.)
7. t
is the time that is required before synchronization is achieved. This specification is valid only after V is
CC
LOCK
stable and within normal operating limits. This parameter is measured from the application of a new signal or
frequency at REF or FB until t is within specified limits.
PD
8. t is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
PD
9. Measured at 2.0V.
10.Measuredat0.8V.
11.RefertoTable12formoredetail.
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PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver SuperClock
Table12.InputTimingRequirements
Symbol
tR, tF
tPWC
DH
Description
Maximum input rise and fall times, 0.8V to 2.0V
Input clock pulse, HIGH or LOW
Input duty cycle
Min.
Max. Units
10
ns/V
ns
3
10
90
%
Notes:
1. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by D is
H
less than t
limit, t
limit applies.
PWC
PWC
t
t
REF
RPWL
t
RPWH
REF
t
PD
t
t
ODCV
ODCV
FB
Q
t
JR
t
SKEWPR
t
SKEWPR
t
SKEW0, 1
t
SKEW0, 1
Other Q
t
t
SKEW2
SKEW2
Inverted Q
t
t
SKEW3,4
t
t
SKEW3,4
SKEW3,4
SKEW2,4
REF Divided by 2
REF Divided by 4
t
SKEW1,3,4
ACTimingDiagram
Notes:
VCCQ/PE: TheACtimingdiagramaboveappliestoVCCQ/PE=VCC. ForVCCQ/PE=GND, thenegativeedgeofFBalignswiththenegativeedgeofREF,
divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with 20pF and terminated with 75Ohm to VCC/2.
tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0
tDEV
tODCV
tLOCK
:
The skew between outputs when they are selected for 0t U.
:
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
:
:
tPWH is measured at 2.0V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2.0V.
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock
32-PinPLCCPackageDiagram
28-PinQSOPPackageDiagram
28
0.150
0.157
3.81
3.99
.015 x 45˚
1
0.178
0.254
.007
.010
.386 9.804
.394 10.009
0.41 .016
1.27 .050
.228
.244
5.79
6.19
.033
REF
0.84
1.35 .053
1.75 .069
SEATING
PLANE
0.101
0.254
.004
.010
.008
.012
.025
BSC
0.635
0.203
0.305
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
PS8449A
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PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver SuperClock
OrderingInformation
Ordering Code
PI6C3Q991J
Package Code
Package Type
32-Pin PLCC
32-Pin PLCC
32-Pin PLCC
32-Pin PLCC
32-Pin PLCC
28-Pin QSOP
28-Pin QSOP
28-Pin QSOP
28-Pin QSOP
28-Pin QSOP
Operating Range
J32
J32
PI6C3Q991-2J
PI6C3Q991-5J
PI6C3Q991-IJ
PI6C3Q991-5IJ
PI6C3Q993Q
Commercial
J32
J32
Industrial
Commercial
Industrial
J32
Q28
Q28
Q28
Q28
Q28
PI6C3Q993-2Q
PI6C3Q993-5Q
PI6C3Q993-IQ
PI6C3Q993-5IQ
PericomSemiconductorCorporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8449A
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相关型号：
SI9130DB
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