PI6C39911-2 [PERICOM]
Clock IC | 250ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz ; 时钟IC | 250PS精度。 3.3V 。 LVTTL 。 3.75至110 MHz的
| 型号： | PI6C39911-2 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Clock IC | 250ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz
|
| 文件： | 总11页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C39911
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer - SuperClock®
Features
Description
• All output pair skew <100ps typical (250 Max.)
• 12.5 MHz to 133 MHz output operation
The PI6C39911 offers selectable control over system clock func-
tions. These multiple-output clock drivers provide the system
integrator with functions necessary to optimize the timing
• 3.125 MHz to 133 MHz input operation (input as low as 3.125
of high-performance computer systems. Eight individual drivers,
arranged as four pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as low as 50-Ohms
whiledeliveringminimalandspecifiedoutputskewsandfull-swing
logiclevels.
MHzfor4xoperation,or6.25MHzfor2xoperation)
• User-selectable output functions
— Selectable skew to 18ns
— Inverted and non-inverted
— Operation at ½ and ¼ input frequency
— Operation at 2X and 4X input frequency
• Zero input-to-output delay
• 50% duty-cycle outputs
• Inputs are 5V Tolerant
• LVTTLoutputsdrive50-Ohmterminatedlines
• Operates from a single 3.3V supply
• Low operating current
• 32-pinPLCCpackage
• Jitter < 200ps peak-to-peak (< 25ps RMS)
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
foradditionalflexibilityindesigningcomplexclocksystems.When
combinedwiththeinternalPLL,thesedividefunctionsallowdistri-
butionofalow-frequencyclockthatcanbemultipliedbytwoorfour
attheclockdestination.This feature allows flexibility and simpli-
fies system timing distribution design for complex high-speed
systems.
PinConfiguration
LogicBlockDiagram
Test
Phase
Freq.
DET
VCO and
Time Unit
Generator
FB
Filter
REF
FS
4
3
2
1
32 31 30
5
29
28
27
26
25
24
23
22
21
3F1
4F0
4F1
2F0
GND
1F1
1F0
6
7
4Q0
4Q1
4F0
4F1
32 Pin
J
8
V
CCQ
Select Inputs
(three level)
9
V
V
CCN
4Q1
CCN
Skew
10
11
12
13
1Q0
1Q1
GND
GND
3Q0
3Q1
3F0
3F1
4Q0
Select
GND
GND
2Q0
2Q1
2F0
2F1
14 15 16 17 18 19 20
Matrix
1Q0
1Q1
1F0
1F1
PS8497E
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PI6C39911
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
PinDescriptions
Signal
I/O
Description
Name
REF
I
I
Reference frequency input supplies the frequency and timing against which all functional variation is measured.
PLL feedback input (typically connected to one of the eight outputs)
Three-level frequency range select. see Table 1.
FB
FS
I
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
I
Three-level function select inputs for output pair 1 (1Q0, 1Q1). see Table 2.
Three-level function select inputs for output pair 2 (2Q0, 2Q1). see Table 2.
Three-level function select inputs for output pair 3 (3Q0, 3Q1). see Table 2.
Three-level function select inputs for output pair 4 (4Q0, 4Q1). see Table 2.
Three-level select. See test mode section under the block diagram descriptions
Output pair 1. see Table 2
I
I
I
I
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
O
O
O
O
Output pair 2. see Table 2
Output pair 3. see Table 2
Output pair 4. see Table 2
V
PWR Power supply for output drivers
PWR Power supply for internal circuitry
PWR Ground
CCN
V
CCQ
GND
(1)
(1)
Table2.ProgrammableSkewConfigurations
Function Selects Output Functions
Table1.FrequencyRangeSelectandt Calculation
U
1
tU
=
Approximate
Freq. (MHz) at
which tU = 1.0ns
FNOM (MHz)
fNOM × N
FS(1,2)
1F1, 2F1,
1F0, 2F0,
3F0, 4F0
LOW
MID
HIGH
LOW
MID
1Q0, 1Q1,
2Q0, 2Q1
3Q0, 3Q1 4Q0, 4Q1
3F1, 4F1
LOW
LOW
LOW
MID
where N=
Min.
12.5
25
Max.
30
–4t
–3t
–2t
–1t
Divide by 2 Divide by 2
U
U
U
U
LOW
MID
44
26
16
22.7
38.5
62.5
–6t
–4t
–2t
–6t
–4t
–2t
U
U
U
U
U
U
50
HIGH
40
133
MID
0t
U
0t
U
0t
U
MID
HIGH
LOW
MID
+1t
+2t
+3t
+4t
+2t
+4t
+6t
+2t
+4t
+6t
U
U
U
U
U
U
U
U
U
U
HIGH
HIGH
HIGH
HIGH
Divide by 4 Inverted
Notes:
1. For all three-state inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open
CC
connection. Internal termination circuitry holds an unconnected input to V /2.
CC
NOM
2.TheleveltobesetonFSisdeterminedbythe“normal”operatingfrequency(f
)andTimeUnitGenerator(seeLogicBlockDiagram).
Nominal frequency (f
) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table
NOM
2). The frequency appearing at the REF and FB inputs will be f
when the output connected to FB is undivided. The frequency
NOM
oftheREFandFBinputswillbef
as the FB input.
/2orf
/4whenthepartisconfiguredforafrequencymultiplicationbyusingadividedoutput
NOM
NOM
PS8497E
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PI6C39911
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
Test Mode
MaximumRatings
TheTESTinputisathree-levelinput. Innormalsystemoperation,
thispinisconnectedtoground, allowingthePI6C39911 tooperate
as explained briefly above (for testing purposes, any of the three
levelinputscanhavearemovablejumpertoground,orbetiedLOW
through a 100 Ohm resistor. This will allow an external tester to
change the state of these pins.)
IftheTESTinputisforcedtoitsMIDorHIGHstate,thedevicewill
operatewithitsinternalphaselockedloopdisconnected,andinput
levels supplied to REF will directly control all outputs. Relative
output to output functions are the same as in normal mode.
Storage Temperature ..................................... –65°Cto+150°C
AmbientTemperaturewith
Power Applied ............................................... –55°Cto+125°C
Supply Voltage to Ground Potential ................ –0.5Vto+5.0V
DC Input Voltage .............................................. –0.5Vto+5.0V
Output Current into Outputs (LOW) .............................. 64mA
StaticDischargeVoltage ............................................... >2001V
(perMIL-STD-883,Method3015)
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
selectinputs(xF0andxF1)andthewaveformcharacteristicsofthe
REFinput.
Latch-UpCurrent .........................................................>200mA
(2,3)
MaximumPowerDissipationatT =85°C
.............. 0.80watts
A
OperatingRange
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
V
CC
3.3V ±10%
3.3V ±10%
–40°C to +85°C
FB Input
REF Input
1Fx
3Fx
4Fx
2Fx
(N/A)
LL
LM
LH
–6tU
–4tU
–3tU
–2tU
–1tU
0tU
LM (N/A)
LH ML
ML (N/A)
MM MM
MH
HL
(N/A) +1tU
MH +2tU
(N/A) +3tU
HM
HH
HL
+4tU
+6tU
(N/A)
HM
(N/A) LL/HH Divided
(N/A) HH Invert
(3)
Figure1.TypicalOutputswithFBConnectedtoaZero-SkewOutput
Note:
3. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID)
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PI6C39911
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
Capacitance(6)
Parameter
Description
Test Conditions
T = 25°C, f = 1MHz, V = 3.3V
Max.
Units
C
Input Capacitance
10
pF
IN
A
CC
ElectricalCharacteristics(OvertheOperatingRange)
Parameter
Description
Test Conditions
Min.
Max.
Units
VOH
Output HIGH Voltage
Output LOW Voltage
VCC = Min., IOH = –18mA
VCC = Min., IOL = 35mA
2.4
VOL
0.45
VCC
Input HIGH Voltage
VIH
VIL
2.0
(REF and FB inputs only)
Input LOW Voltage
(REF and FB inputs only)
–0.5
0.8
V
Three-Level Input HIGH Voltage
VIHH
VIMM
VILL
IIH
Min. ≤ VCC ≤ Max.
0.87 VCC VCC
(Test, FS, xFn)(4)
Three-Level Input MID Voltage
(Test, FS, xFn)(4)
Min. ≤ VCC ≤ Max.
0.47 VCC 0.53 VCC
Three-Level Input LOW Voltage
Min. ≤ VCC ≤ Max.
0.0
0.13 VCC
20
(Test, FS, xFn)(4)
Input HIGH Leakage Current
(REF and FB inputs only)
VCC = Max., VIN = Max.
VCC = Max., VIN = 0.4V
Input LOW Leakage Current
(REF and FB inputs only)
IIL
–20
µA
IIHH
IIMM
IILL
IOS
Input HIGH Current (Test, FS, xFn)
Input MID Current (Test, FS, xFn)
Input LOW Current (Test, FS, xFn)
Short Circuit Current(5)
VIN = VCC
200
50
VIN = VCC/2
–50
VIN = GND
–200
VCC = Max., VOUT = GND (25°C only)
–200
95
Com'l
Operating Current Used by Internal
Circuitry
VCCN = VCCQ = Max.,
All Input Selects Open
ICCQ
ICCN
mA
Mil/Ind
100
VCCN = VCCQ = Max., IOUT = 0mA
All Input Selects Open, fMAX
Output Buffer Current per Output Pair
Power Dissipation per Output Pair
19
VCCN = VCCQ = Max., IOUT = 0mA
All Input Selects Open, fMAX
PD
104
mW
Notes:
4. These inputs are normally wired to V , GND, or left unconnected (actual threshold voltages vary as a percentage of V ).
CC
CC
Internal termination resistors hold unconnected inputs at V /2. If these inputs are switched, the function and timing of the
CC
outputs may glitch and the PLL may require an additional t
time before all data sheet limits are achieved.
LOCK
5. PI6C39911 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
Roomtemperatureonly.
6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
7. Test measurement levels for the PI6C39911 are 1.5V to 1.5V. Test conditions assume signal transition times of 2ns or less and output
loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
8. Guaranteed by statistical correlation.
PS8497E
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PI6C39911
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
(2,7)
Switching Characteristics(OvertheOperatingRange)
PI6C39911-2
PI6C39911-5
PI6C39911
Unit-
s
Parameter
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
FS = LOW(1,2)
FS = MID(1,2)
FS = HIGH(1,2)
12.5
25
30
50
12.5
25
30
50
12.5
25
30
Operating
Clock
(1,2)
fNOM
50 MHz
133
Frequency
40
133
40
133
40
in MHz
tRPWH
tRPWL
tU
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
3.0
3.0
3.0
3.0
3.0
3.0
ns
See Table 1
See Table 1
See Table 1
0.1 0.25
0.3 0.75
Zero Output Matched
tSKEWPR
tSKEW0
tSKEW1
0.1 0.25
0.20 0.25
0.1
0.25
0.6
0.25
0.5
-Pair Skew (XQ0, XQ1)(9,10)
Zero Output Skew (All Outputs)(9,11)
Output Skew (Rise-Rise, Fall-Fall,
0.4
0.6
0.4
0.5
0.5
0.8
0.5
0.7
0.6
1.0
0.7
1.2
1.0
1.5
1.2
Same Class Outputs)(9,13)
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)(9,13)
tSKEW2
tSKEW3
tSKEW4
0.5
0.5
0.5
1.0
0.7
Output Skew (Rise-Rise, Fall-Fall,
Different Class Outputs)(9,13)
ns
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)(9,13)
0.8
1.0
1.0
1.7
(8,14)
tDEV
tPD
tODCV
tPWH
Device-to-Device Skew
1.25
1.65
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation (15)
Output HIGH Time Deviation from 50%(16)
Output LOW Time Deviation from 50%(16)
Output Rise Time(16,17)
–0.3 0.0 +0.3 –0.5
–1.0 0.0 +1.0 –1.0
0.0
0.0
+0.5 –0.7 0.0 +0.7
+1.0 –1.2 0.0 +1.2
2.5
3.0
1.5
1.5
0.5
25
2.5
3.0
1.5
1.5
0.5
25
3.0
3.5
1.5
1.5
0.5
25
tPWL
tORISE
tOFALL
tLOCK
0.15 1.0
0.15 1.0
0.15
0.15
1.0
1.0
0.15 1.0
0.15 1.0
Output Fall Time(16,17)
PLL Lock Time(18)
ms
ps
RMS(8)
Cycle-to-cycle
Output Jitter
tJR
Peak-to-peak(8)
200
200
200
Notes:
9. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t delay has been
U
selected when all are loaded with 30pF and terminated with 50 ohms to V /2.
CC
10. t
11. t
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t .
U
SKEWPR
is defined as the skew between outputs when they are selected for 0t . Other outputs are divided or inverted but not shifted.
SKEW0
U
12. C = 0pF. For C = 30pF, t
= 0.35ns.
L
L
SKEW0
13. Therearethreeclassesofoutputs:Nominal(multipleoft delay),Inverted(4Q0and4Q1onlywith4F0=4F1=HIGH),andDivided(3Qx
U
and4QxonlyinDivide-by-2orDivide-by-4mode).
14. t
15. t
istheoutput-to-outputskewbetweenanytwodevicesoperatingunderthesameconditions(V ambienttemperature, airflow, etc.)
CC
DEV
ODCV
isthedeviationoftheoutputfroma50%dutycycle.Outputpulsewidthvariationsareincludedint
andt
specifications.
SKEW2
SKEW4
16. Specified with outputs loaded with 30pF for the PI6C39911 devices. Devices are terminated through 50 Ohm to V /2. t
is measured
CC
PWH
at 2.0V. t
is measured at 0.8V.
PWL
and t
17. t
measured between 0.8V and 2.0V.
ORISE
LOCK
OFALL
18. t
is the time that is required before synchronization is achieved. This specification is valid only after V is stable and within normal
CC
operatinglimits.ThisparameterismeasuredfromtheapplicationofanewsignalorfrequencyatREForFBuntilt iswithinspecifiedlimits.
PD
PS8497E
09/13/02
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PI6C39911
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
AC Test Loads and Waveforms
TTL AC Test Load
TTL Input Test Waveform
V
CC
≤1ns
≤1ns
R1
3.0V
2.0V
Vth =1.5V
0.8V
C
L
R2
0V
R1=100
R2=100
C =30pF (Includes fixture and probe capacitance)
L
ACTimingDiagrams
t
t
REF
RPWL
t
RPWH
REF
t
PD
t
t
ODCV
ODCV
FB
Q
t
JR
t
SKEWPR
t
SKEWPR
t
SKEW0, 1
t
SKEW0, 1
Other Q
t
t
SKEW2
SKEW2
Inverted Q
t
t
SKEW3,4
t
t
SKEW3,4
SKEW3,4
REF Divided by 2
t
SKEW1,3,4
SKEW2,4
REF Divided by 4
PS8497E
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PI6C39911
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
OperationalModeDescriptions
REF
FB
LOAD
System Clock
REF
FS
L1
Z
Z
0
0
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
LOAD
L2
L3
L4
Z
Z
0
0
LENGTH: L1 = L2 = L3 = L4
Figure2.Zero-Skewand/orZero-DelayClockDriver
Figure2showstheSUPERCLOCKconfiguredasazero-skewclock
buffer.InthismodethePI6C39911canbeusedasthebasisforalow-
skew clock distribution tree. When all of the function select inputs
(xF0, xF1) are left open, the outputs are aligned and may each drive
aterminatedtransmissionlinetoanindependentload.TheFBinput
can be tied to any output in this configuration and the operating
frequency range is selected with the FS pin. The low-skew specifi-
cation,coupledwiththeabilitytodriveterminatedtransmissionlines
(withimpedancesaslowas50ohms),allowsefficientprintedcircuit
board design.
REF
FB
LOAD
LOAD
System Clock
REF
FS
L1
L2
Z
Z
0
0
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
L3
L4
LOAD
LOAD
Z
Z
0
0
LENGTH: L1 = L2, L3 < L2 by 6", L4 > L2 by 6"
Figure3.ProgrammableSkewClockDriver
PS8497E
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PI6C39911
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
Figure 3 shows a configuration to equalize skew between metal Figure4showsanexampleoftheinvertfunctionoftheSuperClock.
tracesofdifferentlengths.Inadditiontolowskewbetweenoutputs, In this example the 4Q0 output used as the FB input is programmed
the SuperClock can be programmed to stagger the timing of its forinvert(4F0=4F1=HIGH)whiletheotherthreepairsofoutputs
outputs. The four groups of output pairs can each be programmed areprogrammedforzeroskew.When4F0and4F1aretiedHIGH,4Q0
to different output timing. Skew timing can be adjusted over a wide and 4Q1 become inverted zero phase outputs. The PLL aligns the
range in small increments with the appropriate strapping of the rising edge of the FB input with the rising edge of the REF. This
functionselectpins. Inthisconfigurationthe4Q0outputisfedback causesthe1Q,2Q,and3Qoutputstobecomethe“inverted”outputs
to FB and configured for zero skew.
with respect to the REF input. By selecting which output is connect
to FB, it is possible to have 2 inverted and 6 non-inverted outputs
or 6 inverted and 2 non-inverted outputs. The correct configuration
would be determined by the need for more (or fewer) inverted
outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate
for varying trace delays independent of inver-sion on 4Q.
The other three pairs of outputs are programmed to yield different
skewsrelativetothefeedback.Byadvancingtheclocksignalonthe
longertracesorretardingtheclocksignalonshortertraces,allloads
can receive the clock pulse at the same time.
In this illustration the FB input is connected to an output with 0ns
skew(xF1,xF0=MID)selected.TheinternalPLLsynchronizesthe
FB and REF inputs and aligns their rising edges to insure that all
outputs have precise phase alignment.
Clock skews can be advanced by ±6 time units (t ) when using an
U
REF
output selected for zero skew as the feedback. A wider range of
delaysispossibleiftheoutputconnectedtoFBisalsoskewed.Since
FB
“ZeroSkew”,+t ,and–t aredefinedrelativetooutputgroups,and
20 MHz
REF
U
U
sincethePLLalignstherisingedgesofREFandFB, itispossibleto
FS
createwideroutputskewsbyproperselectionofthexFninputs. For
40 MHz
20 MHz
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
4Qx
examplea+10t betweenREFand3Qxcanbeachievedbyconnect-
U
ing 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 =
High.(SinceFBalignsat–4t and3Qxskewsto+6t ,atotalof+10
U
U
t skew is realized). Many other configurations can be realized by
U
80 MHz
skewing both the output used as the FB input and skewing the other
outputs.
REF
Figure5.FrequencyMultiplierwithSkewConnections
FB
REF
FS
Figure5illustratestheSuperClockconfiguredasaclockmultiplier.
The 3Q0 output is programmed to divide by four and is fed back to
FB. This causes the PLL to increase its frequency until the 3Q0 and
3Q1outputsarelockedat20MHzwhilethe1Qxand2Qxoutputsrun
at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by
two,whichresultsina40MHzwaveformattheseoutputs.Notethat
therisingedgesof4Qxand3Qxoutputsarealigned. The2Q0, 2Q1,
1Q0,and1Q1outputsrunat80MHzandareskewedbyprogramming
their select inputs accordingly. Note that the FS pin is wired for 80
MHz operation because that is the frequency of the fastest output.
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Figure4.InvertedOutputConnections
PS8497E
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PI6C39911
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
offerdivide-by-2anddivide-by-4timing.Aninvertedoutputallows
the system designer to clock different sub-systems on opposite
edges, without suffering from the pulse asymmetry typical of non-
ideal loading. This function allows the two subsystems to each be
clocked 180 degrees out of phase, but still to be aligned within the
skew specification.
REF
FB
20 MHz
REF
FS
10 MHz
The divided outputs offer a zero-delay divider for portions of the
system that need the clock to be divided by either two or four, and
still remain within a narrow skew of the “1X” clock. Without this
feature, an external divider would need to be add-ed, and the
propagation delay of the divider would add to the skew between the
different clock signals.
These divided outputs, coupled with the Phase Locked Loop, allow
the SuperClock to multiply the clock rate at the REF input by either
two or four. This mode will enable the designer to distribute a low-
frequency clock between various portions of the system, and then
locallymultiplytheclockratetoamoresuitablefrequency,whilestill
maintaining the low-skew characteristics of the clock driver. The
SuperClock can perform all of the functions described above at the
sametime.Itcanmultiplybytwoandfourordividebytwo(andfour)
at the same time that it is shifting its outputs over a wide range or
maintaining zero skew between selected outputs.
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
5 MHz
20 MHz
Figure6.FrequencyDividerConnections
Figure6demonstratestheSuperClock inaclockdividerapplication.
2Q0 is fed back to the FB input and programmed for zero skew.
3Qxisprogrammedtodividebyfour. 4Qxisprogrammedtodivide
by two. Note that the rising edges of the 4Qx and 3Qx outputs are
aligned. The 1Qx outputs are programmed to zero skew and are
aligned with the 2Qx outputs. In this example, the FS input is
groundedtoconfigurethedeviceinthe15to30MHzrangesincethe
highest frequency output is running at 20 MHz.
Figure 7 shows some of the functions that are selectable on the 3Qx
and 4Qx outputs. These include inverted outputs and outputs that
REF
FB
LOAD
27.5 MHz
REF
Distribution
Z
0
Clock
FS
110 MHz
Inverted
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
Z
0
27.5 MHz
LOAD
LOAD
110 MHz
Zero Skew
Z
0
110 MHz Skewed
–2.273ns (–4t )
Z
U
0
Figure7.Multi-FunctionClockDriver
PS8497E
09/13/02
9
PI6C39911
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
REF
LOAD
FB
System
Clock
Z
Z
0
0
REF
FS
L1
L2
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
L3
Z
0
L4
FB
Z
REF
FS
0
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
Figure8.Board-to-BoardClockDistribution
Figure8showsthePI6C39911 connectedinseriestoconstructazero delay clock tree. Cascaded clock buffers will accumulate low
skew clock distribution tree between boards. Delays of the down frequency jitter because of the non-ideal filtering characteristics of
streamclockbufferscanbeprogrammedtocompensateforthewire thePLLfilter.Itisrecommendedthatnotmorethantwoclockbuffers
length (i.e., select negative skew equal to the wire delay) necessary be connected in series.
to connect them to the master clock source, approximating a zero-
PS8497E
09/13/02
10
PI6C39911
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
PackagingMechanical:32-PinPLCC (J32)
OrderingInformation
Theta JA (in
Package
Name
still air)
(degrees
C/Watt)
Theta JC
Accuracy (ps)
Ordering Code
Package Type
Operating Range
(degrees C/Watt)
250
500
750
PI6C39911-2J
PI6C39911-5J
PI6C39911J
32-Pin Plastic
Leaded Chip
Carrier
J32
Commercial
52
23
PericomSemiconductorCorporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8497E
09/13/02
11
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