PI6C2510-133LX [PERICOM]

PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSOP-24;


型号：	PI6C2510-133LX
厂家：	PERICOM SEMICONDUCTOR CORPORATION
描述：	PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSOP-24 时钟驱动器
文件：	总5页 (文件大小：142K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PI6C2510-133

Low-Noise, Phase-Locked Loop

Clock Driver with 10 Clock Outputs

Features

Description

•

Operating Frequency up to 150 MHz

ThePI6C2510-133isa“quiet,”low-skew,low-jitter,phase-locked

loop (PLL) clock driver, distributing high-frequency clock signals

for SDRAM and server applications. By connecting the feedback

FB_OUT output to the feedback FB_IN input, the propagation

delayfromtheCLK_INinputtoanyclockoutputwillbenearlyzero.

This zero-delay feature allows the CLK_IN input clock to be

distributed, providing one clock input to one bank of ten outputs,

with an output enable.

•

Low-Noise Phase-Locked Loop Clock Distribution that

meets 133 MHz Registered DIMM Synchronous DRAM

modules for server/workstation/PC applications

Allows Clock Input to have Spread Spectrum modulation

for EMI reduction

•

Zero Input-to-Output delay: Distribute one Clock Input

to one Bank of Ten outputs, with an output enable.

Low jitter: Cycle-to-Cycle jitter ±75ps max.

On-chip series damping resistor at clock output drivers

for low noise and EMI reduction

•

ThisclockdriverisdesignedtomeetthePC133SDRAMRegistered

DIMM specification. For test purposes, the PLL can be bypassed

by strapping AV to ground.

•

Operates at 3.3V V

Packaging(Pb-free&Greenavailable):

-24-pinTSSOP(L)

BlockDiagram

PinConfiguration

AGND

CLK_IN

GND

Y[0:9]

GND

24-Pin

CLK_IN

FB_IN

AVcc

FB_OUT

PLL

FB_OUT

FB_IN

Functional Table

Inputs

Outputs

Y[0:9]

FB_OUT

CLK_IN

PS8383B

09/14/04

PI6C2510-133

Low-Noise, Phase-Locked Loop

Clock Driver with 10 Clock Outputs

Pin Functions

Pin Name Pin Number

Type

Description

CLK_IN

FB_IN

Reference Clock input. CLK_IN allows spread spectrum.

Feedback input. FB_IN provides the feedback signal to the internal PLL

Output bank enable. When G is LOW, outputs Y[0:9] are disabled to

a logic low state. When G is HIGH, all outputs Y[0:9] are enabled.

Feedback output. FB_OUT is dedicated for external feedback.

FB_OUT has an embedded series-damping resistor of the same

value as the clock outputs Y[0:9].

FB_OUT

Y[0:9]

AV_CC

AGND

V_CC

3,4,5,8,9,15

16,17,20,21

Clock outputs. These outputs provide low-skew copies of

CLK_IN_.Each output has an embedded series-damping resistor.

Analog power supply. AV_CCcan be also used to bypass the PLL for

test purposes. When AV_CCis strapped to ground, PLL is bypassed and

CLK_IN buffered directly to the device outputs.

Power

Ground

Power

Ground

Analog ground. AGND provides the ground reference for the analog circuitry.

2,10,14,22

6,7,18,19

Power supply

Ground

GND

PS8383B

09/14/04

PI6C2510-133

Low-Noise, Phase-Locked Loop

Clock Driver with 10 Clock Outputs

DC Specifications

Absolute maximum ratings over operating free-air temperature range.

Symbol

V_I

Parameter

Min.

Max.

Units

Input voltage range

Output voltage range

DC input voltage

_CC+ 0.5

V_O

-0.5

V_{I_}DC

+5.0

100

1.0

I_{O_}DC

DC output current

^oC

Power

T_STG

Maximum power dissipation at T_A= 55^oC in still air

Storage temperature

-65

150

Note: Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.

Parameter

Test Conditions

V_I= V_CCor GND; I_O= 0

V_I= V_CCor GND

V_CC

Min.

Typ.

Max.

Units

I_CC

C_I

3.6V

µA

3.3V

C_O

V_O=V_CCor GND

Recommended Operating Conditions

Symbol Parameter

Min.

Max.

Units

Supply voltage

3.0

2.0

3.6

High level input voltage

Low level input voltage

Input voltage

0.8

0.0

Operating free-air temperature

Electrical characteristics over recommended operating free-air temperature range

Pull Up/Down Currents of PI6C2510-133, V = 3.0V

Symbol

Parameter

Pull-up current

Condition

V_OUT= 2.4V

V_OUT= 2.0V

V_OUT= 0.8V

V_OUT= 0.55V

Min.

Max.

-13.6

-22

Units

I_OH

Pull-up current

Pull-down current

I_OL

PS8383B

09/14/04

PI6C2510-133

Low-Noise, Phase-Locked Loop

Clock Driver with 10 Clock Outputs

AC Specifications

Timing requirements over recommended ranges of supply voltage and operating free-air temperature.

Symbol

Parameter

Input clock frequency

Min.

Max.

150

Units

MHz

F_CLK

Input clock duty cycle

Stabilization Time after power up

Switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL=30pF

= 3.3V ±0.3V, 0-70°C

Parameter

From

Units

Min.

Typ.

Max.

tphase error, with and without

spread spectrum

CLK_IN↑ at 133 MHz

FB_IN↑

–150

+150

Jitter, cycle-to-cycle,

with and without spread

spectrum

Output or

Any Output or FB_OUT

FB_OUT in

–75

+75

in CLK at 133 MHz

CLK

n+1

Skew, at 133 MHz

Any Y or FB_OUT

150

Any Y or

FB_OUT

Duty cycle

1.0

1.1

tr, rise-time, 0.4V to 2.0V

tf, fall-time, 2.0V to 0.4V

Note: These switching parameters are guaranteed, but not production tested.

PS8383B

09/14/04

PI6C2510-133

Low-Noise, Phase-Locked Loop

Clock Driver with 10 Clock Outputs

PackagingMechanical:24-pinTSSOP(L)

.169

.177

4.3

4.5

0.09

0.20

.004

.008

.303

0.45 .018

0.75 .030

.311

7.7

7.9

.047

1.20

Max

.252

BSC

6.4

SEATING

PLANE

.002

.006

0.05

0.15

.007

.012

0.19

0.30

.0256

BSC

0.65

X.XX DENOTES CONTROLLING

X.XX DIMENSIONS IN MILLIMETERS

OrderingInformation

OrderingCode

PI6C2510-133L

PI6C2510-133LE

PackageCode

PackageType

24-pinTSSOP

Pb-free&Green,24-pinTSSOP

Notes:

1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/

PericomSemiconductorCorporation • 1-800-435-2336 • www.pericom.com

PS8383B

09/14/04

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