EP8076B-1 [PCA]
Active Delay Line, Programmable, 1-Func, 7-Tap, TTL, DIP-16;
| 型号： | EP8076B-1 |
| 厂家： | 
PCA ELECTRONICS INC. |
| 描述： | Active Delay Line, Programmable, 1-Func, 7-Tap, TTL, DIP-16 光电二极管 逻辑集成电路 延迟线 |
| 文件： | 总5页 (文件大小：34K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Pin DIP 3 Bit Programmable TTL Delay Lines
(Auto-Insertable)
OUTPUT DELAY TIME PROGRAMMING (nS)
DATA INPUT (CBA)
PART
NUMBER
MIN DELAY
±2 nS
MAX DELAY
nS
STEP
000
001
010
011
100
101
110
111
EP8076-1
EP8076-2
EP8076-3
EP8076-4
EP8076-5
EP8076-6
EP8076-7
EP8076-8
EP8076-9
EP8076-10
7
7
7
7
7
7
7
7
7
7
14
21
28
35
42
49
56
63
70
77
1 ± 0.5 nS
2 ± 0.5 nS
3 ± 0.6 nS
4 ± 0.8 nS
5 ± 1.0 nS
6 ± 1.0 nS
7 ± 1.0 nS
8 ± 1.0 nS
9 ± 1.0 nS
10 ± 1.0 nS
7
7
7
7
7
7
7
7
7
7
8
9
9
11
13
15
17
19
21
23
25
27
10
13
16
19
22
25
28
31
34
37
11
15
19
23
27
31
35
39
43
47
12
17
22
27
32
37
42
47
52
57
13
19
25
31
37
43
49
55
61
67
14
21
28
35
42
49
56
63
70
77
10
11
12
13
14
15
16
17
Max delay tolerances ±2 nS or ±5% whichever is greater
All delays measured at 1.5V level on leading edge, no load (enable = "0"), at 25°C, 5.0Vdc
DC Electrical Characteristics
Schematic
Parameter
Test Conditions
Min Max Unit
V
High-Level Output Voltage
Low-Level Output Voltage
Input Clamp Voltage
V
= min. V = max. I = max 2.7
OH
V
V
V
mA
mA
mA
OH
CC
IL
V
V
= min. V = min. I = max
0.5
-1.2
10
15
15
OL
CC IH OL
V
I
V
= min. I = II
IK
CC
I
K
High-Level Input Current
V
= max. V = 2.7V
IH
CC
IN
V
V
= max. V = 5.25V
IN
= max. V = 0.5V
CC
I
Low-Level Input Current
Short Circuit Output Current
IL
CC IN
I
V
= max. V
= 0.
-40
-100 mA
OS
CC
OUT
(One output at a time)
= max. V = OPEN
I
High-Level Supply Current
Low-Level Supply Current
Output Rise Time
Fanout High-Level Output
Fanout Low-Level Output
V
45
90
4
mA
mA
nS
CCH
CC
IN
= max. V = 0
I
T
V
CCL
CC
IN
Td £ 500 nS (0.75 to 2.4 Volts)
= max. V = 2.7V
RO
H
L
N
N
V
CC
20 TTL LOAD
10 TTL LOAD
OH
= max. V = 0.5V
V
CC
OL
Recommended
Operating Conditions
Package
Min Max Unit
V
Supply Voltage
4.75
2.0
5.25
V
V
V
mA
mA
mA
%
CC
V
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Current
High-Level Output Current
Low-Level Output Current
Pulse Width of Total Delay
Duty Cycle
IH
V
0.8
-18
-1.0
20
IL
IK
OH
I
I
I
OL
P
W
*
100
d*
20
%
T
A
Operating Free-Air Temperature
0
+70
°C
*These two values are inter-dependent.
Input Pulse Test Conditions
Unit
E
Pulse Input Voltage
3.2
150
2.0
1.0
5.0
Volts
%
nS
MHz
Volts
IN
P
Pulse Width % of Total Delay
Pulse Rise Time (0.75 - 2.4 Volts)
Pulse Repetition Rate @ Td £ 500 nS
Supply Voltage
W
T
RI
P
V
RR
CC
DSD8076 8/25/94
QAF-CSO1b Rev. B 8/25/94
Unless Otherwise Noted Dimensions in Inches
Tolerances:
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
Fractional = ± 1/32
E L E C T R O N I C S I N C .
.XX = ± .030
.XXX = ± .010
FAX: (818) 894-5791
16 Pin DIL 3 Bit Programmable TTL Delay Lines
OUTPUT DELAY TIME PROGRAMMING (nS)
DATA INPUT (CBA)
PART
NUMBER
MIN DELAY
±2 nS
MAX DELAY
nS
STEP
000
001
010
011
100
101
110
111
1 ± 0.5 nS
2 ± 0.5 nS
3 ± 0.6 nS
4 ± 0.8 nS
5 ± 1.0 nS
6 ± 1.0 nS
7 ± 1.0 nS
8 ± 1.0 nS
9 ± 1.0 nS
EP8076B-1
EP8076B-2
EP8076B-3
EP8076B-4
EP8076B-5
EP8076B-6
EP8076B-7
EP8076B-8
EP8076B-9
EP8076B-10
7
7
7
7
7
7
7
7
7
7
14
21
28
35
42
49
56
63
70
77
7
7
7
7
7
7
7
7
7
7
8
9
9
11
13
15
17
19
21
23
25
27
10
13
16
19
22
25
28
31
34
37
11
15
19
23
27
31
35
39
43
47
12
17
22
27
32
37
42
47
52
57
13
19
25
31
37
43
49
55
61
67
14
21
28
35
42
49
56
63
70
77
10
11
12
13
14
15
16
17
10 ± 1.0 nS
Max delay tolerances ±2 nS or ±5% whichever is greater
All delays measured at 1.5V level on leading edge, no load (enable = "0"), at 25°C, 5.0Vdc
DC Electrical Characteristics
Schematic
Parameter
Test Conditions
Min Max Unit
V
High-Level Output Voltage
Low-Level Output Voltage
Input Clamp Voltage
V
= min. V = max. I = max 2.7
IL OH
V
V
V
mA
mA
mA
mA
OH
CC
V
V
= min. V = min. I = max
0.5
-1.2
10
15
15
OL
CC IH OL
V
I
V
= min. I = II
IK
CC
I
K
High-Level Input Current
V
= max. V = 2.7V
IH
CC
IN
V
V
= max. V = 5.25V
IN
= max. V = 0.5V
CC
I
Low-Level Input Current
Short Circuit Output Current
IL
CC IN
I
V
= max. V
= 0.
-40
-100
OS
CC
OUT
(One output at a time)
= max. V = OPEN
I
High-Level Supply Current
Low-Level Supply Current
Output Rise Time
Fanout High-Level Output
Fanout Low-Level Output
V
45
90
4
mA
mA
nS
CCH
CC
IN
= max. V = 0
I
T
V
CC
CCL
IN
Td £ 500 nS (0.75 to 2.4 Volts)
= max. V = 2.7V
RO
H
L
N
N
V
20 TTL LOAD
10 TTL LOAD
CC
OH
= max. V = 0.5V
V
CC
OL
Recommended
Operating Conditions
Package
Min Max Unit
V
Supply Voltage
4.75
2.0
5.25
V
V
V
mA
mA
mA
%
CC
V
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Current
High-Level Output Current
Low-Level Output Current
Pulse Width of Total Delay
Duty Cycle
IH
V
0.8
-18
-1.0
20
IL
IK
OH
I
I
I
OL
P
W
*
100
d*
20
%
T
Operating Free-Air Temperature
0
+70
°C
A
*These two values are inter-dependent.
Input Pulse Test Conditions
Unit
E
Pulse Input Voltage
3.2
150
2.0
1.0
5.0
Volts
%
nS
MHz
Volts
IN
P
Pulse Width % of Total Delay
Pulse Rise Time (0.75 - 2.4 Volts)
Pulse Repetition Rate @ Td £ 500 nS
Supply Voltage
W
T
RI
P
V
RR
CC
16 Pin DIL 3 Bit Programmable TTL Delay Lines (Economical)
OUTPUT DELAY TIME PROGRAMMING (nS)
TOTAL
MIN DELAY
(INHERENT)
±2 nS
DATA INPUT (CBA)
PART
DELAY*
nS
NUMBER
STEP
000
001
010
011
100
101
110
111
1 ± 0.4 nS
2 ± 0.4 nS
3 ± 0.5 nS
4 ± 0.8 nS
5 ± 1.0 nS
6 ± 1.0 nS
7 ± 1.0 nS
8 ± 1.0 nS
9 ± 1.0 nS
EPA210-1
EPA210-2
EPA210-3
EPA210-4
EPA210-5
EPA210-6
EPA210-7
EPA210-8
EPA210-9
EPA210-10
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
9
9
11
13
15
17
19
21
23
25
27
10
13
16
19
22
25
28
31
34
37
11
15
19
23
27
31
35
39
43
47
12
17
22
27
32
37
42
47
52
57
13
19
25
31
37
43
49
55
61
67
14
21
28
35
42
49
56
63
70
77
14
21
28
35
42
49
56
63
70
10
11
12
13
14
15
16
17
10 ± 1.0 nS
Total delay tolerances ±2 nS or ±5% whichever is greater
All delays measured at 1.5V level on leading edge, no load (enable = "0"), at 25°C, 5.0Vdc.
DC Electrical Characteristics
Schematic
Parameter
Test Conditions
Min Max Unit
V
High-Level Output Voltage
Low-Level Output Voltage
Input Clamp Voltage
V
= min. V = max. I = max 2.7
IL OH
V
V
V
mA
mA
mA
mA
OH
CC
V
V
= min. V = min. I = max
0.5
-1.2
10
15
15
OL
CC IH OL
V
I
V
= min. I = II
K
IK
CC
I
High-Level Input Current
V
= max. V = 2.7V
IH
CC IN
V
= max. V = 5.25V
CC
IN
= max. V = 0.5V
I
Low-Level Input Current
Short Circuit Output Current
V
IL
CC
IN
= max. V
I
V
= 0.
-40
-100
OS
CC OUT
(One output at a time)
I
High-Level Supply Current
Low-Level Supply Current
Output Rise Time
Fanout High-Level Output
Fanout Low-Level Output
V
= max. V = OPEN
45
90
4
mA
mA
nS
CCH
CC
IN
= max. V = 0
I
T
V
CC
CCL
IN
Td £ 500 nS (0.75 to 2.4 Volts)
= max. V = 2.7V
RO
H
L
N
N
V
20 TTL LOAD
10 TTL LOAD
CC
OH
= max. V = 0.5V
V
CC
OL
Recommended
Operating Conditions
Package
Min Max Unit
V
Supply Voltage
4.75
2.0
5.25
V
V
V
mA
mA
mA
%
CC
V
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Current
High-Level Output Current
Low-Level Output Current
Pulse Width of Total Delay
Duty Cycle
IH
V
0.8
-18
-1.0
20
IL
IK
OH
I
I
I
OL
P
*
100
W
d*
20
%
T
A
Operating Free-Air Temperature
0
+70
°C
*These two values are inter-dependent.
Input Pulse Test Conditions
Unit
E
Pulse Input Voltage
3.2
150
2.0
1.0
5.0
Volts
%
nS
MHz
Volts
IN
P
Pulse Width % of Total Delay
Pulse Rise Time (0.75 - 2.4 Volts)
Pulse Repetition Rate @ Td £ 500 nS
Supply Voltage
W
T
RI
P
V
RR
CC
DSA210 8/25/94
QAF-CSO1b Rev. B 8/25/94
Unless Otherwise Noted Dimensions in Inches
Tolerances:
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
Fractional = ± 1/32
E L E C T R O N I C S I N C .
.XX = ± .030
.XXX = ± .010
FAX: (818) 894-5791
16 Pin DIP 3 Bit Programmable TTL Delay Lines
With I/O Completely Buffered
OUTPUT DELAY TIME PROGRAMMING (nS)
DELAY
per
MIN DELAY
TOTAL
DATA INPUT (CBA)
PART
(INHERENT)
±2 nS
DELAY*
nS
NUMBER
STEP **
000
001
010
011
100
101
110
111
EPA563-1
EPA563-2
EPA563-3
EPA563-4
EPA563-5
EPA563-6
EPA563-7
EPA563-8
EPA563-9
EPA563-10
14
14
14
14
14
14
14
14
14
14
7
14
14
14
14
14
14
14
14
14
14
15
16
17
18
19
20
21
22
23
24
16
18
20
22
24
26
28
30
32
34
17
20
23
26
29
32
35
38
41
44
18
22
26
30
34
38
42
46
50
54
19
24
29
34
39
44
49
54
59
64
20
26
32
38
44
50
56
62
68
74
21
28
35
42
49
56
63
70
77
84
1 ± 0.5 nS
2 ± 0.5 nS
3 ± 0.6 nS
4 ± 0.8 nS
5 ± 1.0 nS
6 ± 1.0 nS
7 ± 1.0 nS
8 ± 1.0 nS
9 ± 1.0 nS
14
21
28
35
42
49
56
63
70
10 ± 1.0 nS
Total delay tolerances ±2 nS or ±5% whichever is greater.
All delays measured at 1.5V level on leading edge, no load (enable = "0"), at 25° C / 5.0 Vdc.
*This valule does not include the inherent delay.
DC Electrical Characteristics
Schematic
Parameter
Test Conditions
Min Max Unit
V
High-Level Output Voltage
Low-Level Output Voltage
Input Clamp Voltage
V
= min. V = max. I = max 2.7
OH
V
V
V
µA
mA
mA
mA
OH
CC
IL
V
V
= min. V = min. I = max
0.5
-1.2
50
1.0
OL
CC IH OL
V
I
V
= min. I = II
K
IK
CC
I
High-Level Input Current
V
= max. V = 2.7V
IH
CC IN
V
= max. V = 5.25V
CC
IN
= max. V = 0.5V
I
Low-Level Input Current
Short Circuit Output Current
V
-2
IL
CC
IN
= max. V
I
V
= 0.
-40 -100
OS
CC OUT
(One output at a time)
130
150
4
20 TTL LOAD
10 TTL LOAD
I
High-Level Supply Current
Low-Level Supply Current
Output Rise Time
Fanout High-Level Output
Fanout Low-Level Output
V
= max. V = OPEN
mA
mA
nS
CCH
CC
IN
= max. V = 0
I
T
V
CC
CCL
IN
Td £ 500 nS (0.75 to 2.4 Volts)
= max. V = 2.7V
RO
H
L
N
N
V
CC
OH
= max. V = 0.5V
V
CC
OL
Recommended
Operating Conditions
Package
Min Max Unit
V
Supply Voltage
4.75
2.0
5.25
V
V
V
mA
mA
mA
%
CC
V
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Current
High-Level Output Current
Low-Level Output Current
Pulse Width of Total Delay
Duty Cycle
IH
V
0.8
-18
-1.0
20
IL
IK
OH
I
I
I
OL
P
W
*
100
d*
20
%
T
Operating Free-Air Temperature
0
+70
°C
A
*These two values are inter-dependent.
Input Pulse Test Conditions
Unit
E
Pulse Input Voltage
3.2
150
2.0
1.0
5.0
Volts
%
nS
MHz
Volts
IN
P
Pulse Width % of Total Delay
Pulse Rise Time (0.75 - 2.4 Volts)
Pulse Repetition Rate @ Td £ 500 nS
Supply Voltage
W
T
RI
P
V
RR
CC
DSA563 8/25/94
QAF-CSO1bb Rev. B 8/25/94
Unless Otherwise Noted Dimensions in Inches
Tolerances:
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
Fractional = ± 1/32
E L E C T R O N I C S I N C .
.XX = ± .030
.XXX = ± .010
FAX: (818) 894-5791
16 Pin DIP 3 Bit Programmable TTL Delay Lines
With I/O Completely Buffered
OUTPUT DELAY TIME PROGRAMMING (nS)
MIN DELAY
TOTAL
DELAY
per
DATA INPUT (CBA)
(INHERENT)
±2 nS
PART
DELAY*
nS
NUMBER
STEP **
000
001
010
011
100
101
110
111
EPA563-1A
EPA563-2A
EPA563-3A
EPA563-4A
EPA563-5A
EPA563-6A
EPA563-7A
EPA563-8A
EPA563-9A
EPA563-10A
1 ± 0.5 nS
2 ± 0.5 nS
3 ± 0.6 nS
4 ± 0.8 nS
5 ± 1.0 nS
6 ± 1.0 nS
7 ± 1.0 nS
8 ± 1.0 nS
9 ± 1.0 nS
14
14
14
14
14
14
14
14
14
14
7
14
14
14
14
14
14
14
14
14
14
15
16
17
18
19
20
21
22
23
24
16
18
20
22
24
26
28
30
32
34
17
20
23
26
29
32
35
38
41
44
18
22
26
30
34
38
42
46
50
54
19
24
29
34
39
44
49
54
59
64
20
26
32
38
44
50
56
62
68
74
21
28
35
42
49
56
63
70
77
84
14
21
28
35
42
49
56
63
70
10 ± 1.0 nS
Total delay tolerances ±2 nS or ±5% whichever is greater.
All delays measured at 1.5V level on leading edge, no load (enable = "0"), at 25° C / 5.0 Vdc.
*This valule does not include the inherent delay.
**Tolerance is from step to step.
DC Electrical Characteristics
Schematic
Parameter
Test Conditions
Min Max Unit
V
High-Level Output Voltage
Low-Level Output Voltage
Input Clamp Voltage
V
= min. V = max. I = max 2.7
OH
V
V
V
µA
mA
mA
mA
OH
CC
IL
V
V
= min. V = min. I = max
0.5
-1.2
50
1.0
OL
CC IH OL
V
I
V
= min. I = II
K
IK
CC
I
High-Level Input Current
V
= max. V = 2.7V
IH
CC IN
V
= max. V = 5.25V
CC
IN
= max. V = 0.5V
I
Low-Level Input Current
Short Circuit Output Current
V
-2
IL
CC
IN
= max. V
I
V
= 0.
-40 -100
OS
CC OUT
(One output at a time)
I
High-Level Supply Current
Low-Level Supply Current
Output Rise Time
Fanout High-Level Output
Fanout Low-Level Output
V
= max. V = OPEN
130
150
4
20 TTL LOAD
10 TTL LOAD
mA
mA
nS
CCH
CC
IN
= max. V = 0
I
T
V
CC
CCL
IN
Td £ 500 nS (0.75 to 2.4 Volts)
= max. V = 2.7V
RO
H
L
N
N
V
CC
OH
= max. V = 0.5V
V
CC
OL
Recommended
Operating Conditions
Package
Min Max Unit
V
Supply Voltage
4.75
2.0
5.25
V
V
V
mA
mA
mA
%
CC
V
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Current
High-Level Output Current
Low-Level Output Current
Pulse Width of Total Delay
Duty Cycle
IH
V
0.8
-18
-1.0
20
IL
IK
OH
I
I
I
OL
P
W
*
100
d*
20
%
T
A
Operating Free-Air Temperature
0
+70
°C
*These two values are inter-dependent.
Input Pulse Test Conditions
Unit
E
Pulse Input Voltage
3.2
55
2.0
9.09 MHz
5.0 Volts
Volts
%
nS
IN
P
Pulse Width % of Total Delay
Pulse Rise Time (0.75 - 2.4 Volts)
Pulse Repetition Rate @ Td £ 500 nS
Supply Voltage
W
T
RI
P
V
RR
CC
DSA563A 8/25/94
QAF-CSO1b Rev. B 8/25/94
Unless Otherwise Noted Dimensions in Inches
Tolerances:
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
Fractional = ± 1/32
E L E C T R O N I C S I N C .
.XX = ± .030
.XXX = ± .010
FAX: (818) 894-5791
相关型号：
©2020 ICPDF网 联系我们和版权申明