AN5829 [PANASONIC]
Sound multiplex decoder IC for the U.S. televisions; 伴音解码器IC为美国电视
| 型号： | AN5829 |
| 厂家： | 
PANASONIC |
| 描述： | Sound multiplex decoder IC for the U.S. televisions |
| 文件： | 总17页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICs for TV
AN5829S
Sound multiplex decoder IC for the U.S. televisions
■ Overview
Unit: mm
The AN5829S is a multiplex sound demodulation IC
dedicated to the U.S. television and incorporates a bi-
directional I2C interface (adjustment, mode SW), an AGC
circuit and external stereo input switches (2 systems).
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
■ Features
7
8
• Stereo demodulation, SAP demodulation, dbx noise re-
duction, AGC, external stereo input SW and I2C bus
interface are integrated in a single chip
• Bi-directional I2C bus makes it possible to monitor
9
10
11
12
MPX input level, separation adjustment (3 places), mode
changeover and receiving status.
0.3
• Eliminated external parts (multi-sound block: 21 pieces
→ 14 pieces
7.2±0.3
9.4±0.3
• Lower power dissipation (VCC = 5 V, ITOT = 18 mA)
SOP024-P-0375A
■ Applications
• Televisions and VCRs for the North American market
1
AN5829S
ICs for TV
■ Block Diagram
1
22
R out
21
L out
4
12
13
15
16
17
GND
7
VCC
2
ICs for TV
AN5829S
■ Pin Descriptions
Pin No.
Description
Pin No.
13
Description
SAP carrier detection
1
2
AGC timing
External input 1 L-ch
14
Composite input
Pilot signal detection
Stereo PLL filter
GND
3
External input 1 R-ch
75 µs filter offset cancel
dbx offset cancel
15
4
16
5
17
6
Wideband timing
18
SCL
7
VCC
19
SDA
8
Wideband level sensor input
Spectral filter
20
PE for ZAP
9
21
L-ch output
10
11
12
Spectral timing
22
R-ch output
Spectral level sensor input
SAP noise level detection
23
External input 2 R-ch.
External input 2 L-ch.
24
■ Absolute Maximum Ratings
Parameter
Symbol
VCC
ICC
Rating
Unit
V
Supply voltage
6.0
25
Supply current
mA
mW
°C
Power dissipation *2
PD
150
1
Operating ambient temperature *
Topr
Tstg
−20 to +75
−55 to +125
Storage temperature *1
°C
Note)
The use of this IC, which builds in dbx-TV noise reduction, requires a license agreement with THAT Corporation.
1: Except fot the operating ambient temperature and storage temperature, all ratings are for T = 25°C.
*
*
a
2: T = 75°C
a
■ Recommended Operating Range
Parameter
Supply voltage
Symbol
VCC
Range
Unit
4.5 to 5.5
V
3
AN5829S
ICs for TV
■ Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25°C
Input level (at 100% modulation) L+R: 75 mV[rms] (pre-emphasis off)
L−R: 150 mV[rms] (dbx noise reduction off)
Pilot: 15 mV[rms]
SAP: 45 mV[rms] (dbx noise reduction off)
Parameter
Total circuit current
Mono output level
Symbol
Conditions
Min
11
Typ Max
Unit
ICC
No signal
18
480
0
25
mA
V0(MON) f = 1 kHz, (mono) 100%mod
430
− 0.5
530 mV[rms]
Mono frequency characteristics-1 V1(MON) f = 300 Hz, (mono) 30%mod
Mono frequency characteristics-2 V2(MON) f = 8 kHz, (mono) 30%mod
0.5
dB
dB
−1.2 − 0.1 0.7
Mono distortion ratio
Mono noise level
THD(MON) f = 1 kHz, (mono) 100%mod
0.7
%
VN(MON) Input short-circuit, BPF (A curve)
−60
dBV
dB
(L), (R) output voltage difference VLR(MON) f = 1 kHz, (mono) 100%mod
− 0.5
380
0
480
0
0.5
Stereo output level
V0(ST)
f = 1 kHz, (L(R)-only) 100%mod
f = 300 Hz, (L(R)-only) 30%mod
f = 3 kHz, (L(R)-only) 30%mod
f = 8 kHz, (L(R)-only) 30%mod
580 mV[rms]
Stereo frequency characteristics-1 V1(ST)
Stereo frequency characteristics-2 V2(ST)
Stereo frequency characteristics-3 V3(ST)
− 0.7
−1
0.7
1
dB
dB
0
−2.5 − 0.5 1.5
dB
Stereo distortion ratio
Stereo noise level
THD(ST) f = 1 kHz, (L(R)-only) 100%mod
1
%
VN(ST)
f = 15.73 kHz, (fH), 15 mV[rms]
fH, 2 fH Trap+BPF
−60
dBV
Stereo discrimination level
VTH(ST) f = 15.73 kHz (fH)
4
8
13 mV[rms]
dB
680 mV[rms]
Stereo discrimination hysteresis VHY(ST) f = 15.73 kHz (fH)
0.5
370
−1
5
SAP output level
V0(SAP) f = 1 kHz, (SAP) 100%mod
500
0
SAP frequency characteristics-1 V1(SAP) f = 300 Hz, (SAP) 30%mod
SAP frequency characteristics-2 V2(SAP) f = 3 kHz, (SAP) 30%mod
1
1
dB
dB
−2.5 − 0.5
SAP distortion ratio
SAP noise level
THD(SAP) f = 1 kHz, (SAP) 100%
VN(SAP) f = 78.7 kHz, (5fH),V= 45 mV[rms], BPF
VTH(SAP) f = 78.7 kHz, (5fH)
1.5
−70
%
dBV
SAP discrimination level
11
26 mV[rms]
SAP discrimination hysteresis VHY(SAP) f = 78.7 kHz, (5fH)
0.5
5
dB
dB
SAP → Stereo crosstalk
CT1
(SAP)1 kHz, 100%mod
(Stereo) pilot-signal
−50
Stereo → SAP crosstalk
CT2
(Stereo) 1 kHz, 100%mod
(SAP) carrier-signal
−50
dB
SAP → Mono crosstalk
Mono → SAP crosstalk
CT3
CT4
(SAP) 1 kHz, 100%mod
−50
−56
dB
dB
(Mono) 1 kHz, 100%mod
(SAP) carrier-signal
AUX 1, AUX 2 to INT
crosstalk
CT5
CT6
CT7
f = 1 kHz, VIN = 500 mV[rms]
50
50
50
dB
dB
dB
INT, AUX 2 to AUX 1
crosstalk
INT: (mono) 1 kHz, 100%mod
EXT: f = 1 kHz, 500 mV[rms]
INT, AUX 1 to AUX 2
crosstalk
INT: (mono) 1 kHz, 100%mod
EXT: f = 1 kHz, 500 mV[rms]
4
ICs for TV
AN5829S
■ Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25°C (continued)
Parameter
Symbol
VAGC1
VAGC2
Conditions
Min
67
Typ Max
Unit
1
AGC gain 1*
f = 1 kHz, VIN(EXT) = 50 mV[rms]
f = 1 kHz, VIN(EXT) = 500 mV[rms]
100
270
140 mV[rms]
390 mV[rms]
1
AGC gain 2 *
180
I2 C interface
Sink current at ACK
IACK
Maximum pin 2 sink current at ACK
1
3.5
0
2
20
5.0
0.9
100
mA
V
SCL, SDA signal input high level VIHI
SCL, SDA signal input low level VILO
Input available maximum frequency fImax
V
kbit/s
Note) 1: 00H register: D7 = 0, D6 = 1
*
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
20
17
20
10
22
20
22
14
20
20
20
14
Typ Max
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Stereo separation (100%)-1
Stereo separation (100%)-2
Stereo separation (100%)-3
Stereo separation (100%)-4
Stereo separation (30%)-1
Stereo separation (30%)-2
Stereo separation (30%)-3
Stereo separation (30%)-4
Stereo separation (10%)-1
Stereo separation (10%)-2
Stereo separation (10%)-3
Stereo separation (10%)-4
I2 C interface
Sep100-1 f = 300 Hz, (L(R)-only) 100%mod
Sep100-2 f = 1 kHz, (L(R)-only) 100 %mod
Sep100-3 f = 3 kHz, (L(R)-only) 100%mod
Sep100-4 f = 8 kHz, (L(R)-only) 100%mod
Sep30-1 f = 300 Hz, (L(R)-only) 30%mod
Sep30-2 f = 1 kHz, (L(R)-only) 30%mod
Sep30-3 f = 3 kHz, (L(R)-only) 30%mod
Sep30-4 f = 8 kHz, (L(R)-only) 30%mod
Sep10-1 f = 300 Hz, (L(R)-only) 10%mod
Sep10-2 f = 1 kHz, (L(R)-only) 10%mod
Sep10-3 f = 3 kHz, (L(R)-only) 10%mod
Sep10-4 f = 8 kHz, (L(R)-only) 10%mod
35
28
35
18
35
35
35
22
35
35
30
22
Bus free before start
tBUF
tSU.STA
tHD.STA
tLO
4.0
4.0
4.0
4.0
4.0
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Start condition set-up time
Start condition hold time
Low period SCL, SDA
High period SCL
tHI
Rise time SCL, SDA
tr
1.0
Fall time SCL, SDA
tf
0.35
Data set-up time (write)
Data hold time (write)
Acknowledge set-up time
Acknowledge hold time
Stop condition set-up time
tSU.DAT
tHD.DAT
tSU.ACK
tHD.ACK
tSU.STO
0.25
0.3
3.5
0
4.0
5
AN5829S
ICs for TV
■ Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25°C (continued)
Start
condition
Stop
condition
Slave
address
Sub
address
Data
byte
ACK
ACK
ACK
SDA
SCL
tLO
tSU.STO
tBUF tSU.DAT
tHD.DAT
tSU.STA tHDSTA tr
tf
tHI
tLO
■ Terminal Equivalent Circuits
Pin No.
Equivalent circuit
Description
DC voltage (V)
1
AGC:
0.5 to 2.0
VCC
AGC level sensor pin
425 Ω 51 kΩ
500 Ω
1
GND
VCC
2
AUXIL:
2.2
External input1
L-ch input pin
2
20.7 kΩ
13.8 kΩ
2.2 V
GND
VCC
3
AUXIR:
2.2
External input 1
R-ch input pin
3
20.7 kΩ
13.8 kΩ
2.2 V
GND
6
ICs for TV
AN5829S
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
DC voltage (V)
4
OFCAN1:
2.2
2.2
2.2
VCC
75 µs filter output
Offset cancel pin
524 Ω
4
80 kΩ
80 kΩ
2.2 V
GND
VCC
5
OFCAN2:
dbx output
Offset cancel pin
524 Ω
5
80 kΩ
80 kΩ
2.2 V
GND
VCC
6
WBTIME:
Wide expander effective value detec-
tion
7.5 µΑ
recovery time set-up pin
6
29 Ω
29 Ω
15 µΑ
GND
VCC
7
8
VCC: VCC pin
VCC
2.2
WBDET:
RMS detection circuit input pin
of wide band expander
8
14.4 kΩ
2.2 V
GND
7
AN5829S
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
DC voltage (V)
9
SPEFIL:
2.2
VCC
Variable de-emphasis level adjusting
pin
230 Ω
18 kΩ
230 Ω
18 kΩ
9
2.2 V
GND
VCC
10
11
12
SPETIME:
0.2
RMS detection recovery time pin of
variable de-emphasis
7.5 µΑ
10
29 Ω
29 Ω
15 µΑ
GND
VCC
SPEDET:
2.2
RMS detection circuit input pin of
variable de-emphasis
11
3.2 kΩ
2.2 V
GND
NOISEDET:
VCC − 2 VBE
VCC
Noise detecting pin of SAP malfunc-
tion-prevention-circuit(Mute SAP de-
modulation at detecting noise.)
141 kΩ
12
GND
8
ICs for TV
AN5829S
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
DC voltage (V)
VCC − 2 VBE
13
SAPDET:
VCC
SAP signal carrier level detection pin
163 kΩ
13
14
15
GND
VCC
14
15
16
17
MPXIN:
2.2
Composite signal input pin
524 Ω
54.4 kΩ
2.2 V
GND
VCC
PILOTDET:
2.2VCC − 2 VBE
VCC − 2 VBE
0
Stereo pilot signal detection pin
136 kΩ
GND
VCC
PLL:
Stereo PLL low pass filter connection
pin
58 kΩ
16
GND
GND: GND pin
9
AN5829S
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
DC voltage (V)
18
SCL:
VCC
I2C bus clock input pin
51 kΩ
18
1.7 kΩ
GND
VCC
19
20
21
SDA:
I2C bus data input pin
2.2
51 kΩ
19
1.7 kΩ
GND
PE:
20
Current application input pin for ZAP
at final test
GND
VCC
L-OUT:
2.2
L-ch. line out output pin
520 Ω
430 Ω
21
850 Ω
2.2 V
GND
10
ICs for TV
AN5829S
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
DC voltage (V)
22
R OUT:
2.2
2.2
2.2
VCC
R-ch. line out output pin
520 Ω
22
850 Ω
430 Ω
2.2 V
GND
23
AUX2R:
External input 2
L-ch. input pin
VCC
23
20.7 kΩ
13.8 kΩ
2.2 V
GND
VCC
24
AUX2L:
External input 2
R-ch. input pin
24
20.7 kΩ
13.8 kΩ
2.2 V
GND
11
AN5829S
ICs for TV
■ Usage Notes
1. AGC set-up method
By turning on AGC, the AGC performs 0 dB at a small signal input, Boost at a medium signal and gain reduction
at a big signal. It can also control the I/O characteristics of AGC by I2C as shown below:
AGC characteristics
1 V
AGC = Off
"11"
"00"
AGC = On
"01"
100 mV
10 mV
1 mV
"10"
Data of sub
address 00H
D7 D6
1 mV
10 mV
100 mV
1 V
10 V
Input level (rms)
2. Guarantee of I2C operating temperature
I2C bus control operation at an operating ambient temperature is theoretially guranteed based on IC design by means
of the inspection using about 50% faster clock speed at the normal temperature (Ta = 25°C).
Namely it is a theoretical value based on IC design, therefore it is not guranteed at the shipping inspection because
the inspection under a high and low temperature is not conducted.
3. Electrostatic breakdown
Pay attention to the following levels:
Pin 6: 200 pF, 130 V
Pin 10: 200 pF, 150 V
Pin 22: 200 pF, 190 V
12
ICs for TV
AN5829S
■ Technical Information
[1] I2C bus
1. Receiving mode
SDA
SCL
Start
condition
Slave
address
Acknowledge
bit
Sub
address
Acknowledge
bit
Data Acknowledge Stop
bit
condition
1
0
1
1
0
1
1
0
0
0
0
0
0
0
1
0
1 0 0 0 0 0 0 0
B
6
0
2
8
0
Transmission message
As transfer messages, SCL and SDA are transfered synchronouslly and serially. SCL is a constant clock
frequency and SDA is address data for controlling a receiving side and is sent in parallel by synchronizing with
SCL. Data are in principle sent by 8-bit 3-octet (byte) and there exists an acknowledge bit per octet. The frame
structure is mentioned below:
1) Start condition
When SDA becomes from high to low at SCL = high, the receiver gets ready to receive.
2) Stop condition
When SDA becomes from low to high at SCL = high, the receiver stops receiving.
3) Slave address
Specified for each device. If any addresses of other devices are sent, receiving will be stopped.
4) Sub-address
Specified for each function.
5) Data
Data for controlling
6) Acknowledge bit
This is the bit that informs the master of data reception every octet. The master sends the high signal and
the receiver sends back the low signal as shown with the dotted line in the above figure, thus the master
acknowledges reception on the receiver side. If the low signal is not sent back, the reception will be stopped.
Except for the start and stop conditions, SDA does not change at SCL = high.
13
AN5829S
ICs for TV
■ Technical Information
[1] I2C bus (continued)
1. Receiving mode (continued)
<I2C of this IC>
1) Enhances adjustment-free mechanism of the TV set thanks to DAC control 3 and 9 switches
2) Auto-increment function
• Sub address 0 *: Auto-increment mode
(Data sequential transfer leads to the sequential change of sub address, so that the data is inputted.)
• Sub address 8 *: Data renewal mode
(With sequential data transfer, data are inputted in the same sub address.)
3) I2C bus protocol
• Slave address
• Format (normal)
S
Slave address W A Sub address
A
Data byte
A
P
Acknowledge bit
Write Mode: 0
Start
condition
Stop
condition
• Auto-increment mode/data renewal mode
Slave address W A Sub address
S
A
Data 1
A
Data 2
A
Data n
A P
4) As the initial state of DAC is not guaranteed, never fail to input the following data in a power on mode.
"06" register: "04"
"00" register: adjustment data
"01" register: adjustment data
"02" register: "00"
"05" register: adjustment data
2. Transmission mode (read mode)
I2C bus protocol
• Slave address: 10110111 (B7H)
• Format
S
Slave address
R
A
Data byte
A P
Read
Mode: 1
14
ICs for TV
AN5829S
■ Technical Information (continued)
[1] I2C bus (continued)
• Sub address byte and data byte format
Write mode (slave add.: 10110110)
Upper MSB
Sub
Data byte
D4 D3
Lower LSB
D0
address
D7
D6
D5
D2
D1
AGC adj.
Input level adjustment
"00"
AUXselect AUX SW
0: AUX1
1: AUX2
0: Off
1: On
High frequency separation adjustment
"01"
"02"
"05"
"06"
Adj.: 1 → On Mute: 1 → On
L:VGA out L: Mute
R:VCO fH R: Mute
FMONO: 1 → On
L: L+R
R: L+R
AGC
1 → On
St/SAP (L+R)/SAP
0 → SAP 0 → SAP
0
0
Low frequency separation adjustment
0
0
= Don't care
Read mode (slave add.: 10110111)
Upper MSB
Data byte
Lower LSB
D0
D7
D6
D5
D4
D3
D2
D1
Pilot det. SAP det.
1 → DET 1 → DET
= Don't care
15
AN5829S
ICs for TV
■ Technical Information (continued)
[2] Noise detecting operation in SAP receiving mode
L−R
filter
SW1
a
dbx
Decoder
Stereo
filter
b
SAP out
filter
MPX
in
Input
VCA
14
5fH BPF
I2C
Decoder
SAP det.
SAP
filter
SAP
det.
13
12
DC voltage
comparater
150 kHz BPF
Noise
filter
Noise
det.
Noise det.
SW2
75 µs
De-emph.
a
b
c
21
22
L out
R out
Matrix
a
b
c
dbx
Decoder
Pin 14 input "02" register Pin 12, pin 13
DC voltage
SW1
SW2
I2C SAP det. Pin 21, pin 22
Noise: Small
Noise: Large
"00"
"00"
V12 > V13
V12 < V13
b
a
c
a
3.5 V to 5 V
0 V to 0.9 V
SAP
L+R
16
ICs for TV
AN5829S
■ Application Circuit Example
4.7 µF
180 kΩ
1
4.7 µF
22
R out
4.7 µF
21
L out
2.2 µF
4
0.1 µF
12
0.1 µF
13
0.1 µF
15
0.047 µF
16
17
VCC
5 V
7
4.7 µF
17
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