PD353X [OSRAM]
Lead (Pb) Free Product - RoHS Compliant;
| 型号： | PD353X |
| 厂家： | 
OSRAM GMBH |
| 描述： | Lead (Pb) Free Product - RoHS Compliant |
| 文件： | 总14页 (文件大小：937K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-Character 5 x 7 Dot Matrix
Alphanumeric Programmable DisplayTM with Built-in CMOS Control Functions
Lead (Pb) Free Product - RoHS Compliant
PD243X, PD353X, PD443X
PD353X
PD443X
PD243X
DESCRIPTION
FEATURES
•
Four Dot Matrix Characters in High Efficiency Red,
Red, and Bright Green
These Programmable Displays are four digit display sys-
tem modules. The characters are
- PD2435/6/7, 5.08 mm (0.200") High
- PD3535/6/7, 6.86 mm (0.270") High
- PD4435/6/7, 11.43 mm (0.45") High
Built-in Memory, Decoders, Multiplexer and Drivers
Wide Viewing Angle, X Axis ± 55°, Y Axis ± 65°
Categorized for Luminous Intensity
128 Character ASCII Format (Upper and Lower Case
Characters)
8 Bit Bidirectional Data BUS
READ/WRITE Capability
Dual In-Line Package Configuration, 15.2 mm (0.600")
Wide,
2.54 mm (0.100") Pin Centers
End-Stackable Package
Internal or External Clock
Built-in Character Generator ROM
TTL Compatible
Easily Cascaded for Multidisplay Operation
Less CPU Time Required
Software Controlled Features:
- Programmable Highlight Attribute (Blinking,
Non-Blinking)
- Asynchronous Memory Clear Function
- Lamp Test
- Display Blank Function
5.08 mm by 3.56 mm (0.20" by 0.14") (PD243X),
6.86 mm by 5.08 mm (0.27" by 0.20") (PD353X), and
11.43 mm by 6.86 mm (0.45" by 0.27") (PD443X)
5 x 7 dot matrix arrays constructed with the latest solid
state technology in light emitting diodes. Driving and
controlling the LED arrays is a silicon gate CMOS inte-
grated circuit. This integrated circuit provides all neces-
sary LED drivers and complete multiplexing control
logic.
•
•
•
•
•
•
•
Additionally, the IC has the necessary ROM to decode
128 ASCII alphanumeric characters and enough RAM to
store the display’s complete four digit ASCII message
with special attributes. These attributes, all software pro-
grammable at the user’s discretion, include a lamp test,
brightness control, displaying cursors, alternating cursors
and characters, and flashing cursors or characters.
•
•
•
•
•
•
•
The CMOS IC also incorporates special interface control
circuitry to allow the user to control the module as a fully
supported microprocessor peripheral. The module, under
internal or external clock control, has asynchronous
read, write, and memory clear over an eight bit parallel,
TTL compatible, bi-directional data bus. Each module is
fully encapsulated within a package
25.4 x 17.8 x 5.08 mm (1.0" x 0.7" x 0.2") (PD253X),
35.6 x 18.3 x 7.24 mm (1.4" x 0.72" x 0.285") (PD353X),
and
- Single or Multiple Character Blinking Function
- Programmable Intensity (Three Brightness Levels)
Extended Operating Temperature Range:
PD243X, PD353X: –40°C to +85°C
PD443X: –40°C to +70°C
•
•
•
38.1 x 20.8 x 7.24 mm (1.5" x 0.82" x 0.285") (PD443X).
The standard 20 pin DIP construction with two rows
spaced at 15.2 mm (0.6") on 2.54 mm (0.1") centers is
wave solderable.
See the end of this data sheet or refer to Appnotes 18, 19,
22, and 23 for further details on handling and assembling
OSRAM Programmable Displays.
2006-01-23
1
PD243X, PD353X, PD443X
Ordering Information
Type
Color of Emission Character Height Ordering Code
mm (inch)
PD2435
PD2436
PD2437
high efficiency red
red
bright green
Q68000A3561
Q68000A8366
Q68000A3562
5.08
(0.200)
PD3535
PD3536
PD3537
high efficiency red
red
bright green
Q68000A7964
Q68000A8365
Q68000A7965
6.86
(0.270)
PD4435
PD4436
PD4437
high efficiency red
red
bright green
Q68000A8367
Q68000A8368
Q68000A8369
11.43
(0.450)
2006-01-23
2
PD243X, PD353X, PD443X
Maximum Ratings
Parameter
Symbol
Values
Unit
Operating temperature range
Storage temperature range
Viewing angle (off normal axis)
Top
– 40 … + 85
–40…+70 °C
Tstg
– 40 … +100
°C
hor. (typ.) 2ϕ
ver. (typ.)
± 55
± 65
± 55
± 65
± 40
± 65
deg
deg.
DC Supply Voltage
-0.5 to + 7.0
-0.5 to VCC +0.5
260
Vdc
Vdc
°C
Input Voltage Relative to GND (all inputs)
Solder temperature
Ts
1.59 mm (0.063“) below seating plane, t < 5.0 s
Characteristics
(TA = 25 °C)
Parameter
Symbol
Values
Unit
high
red
green
efficiency
red
Wavelength at peak emission
IF = 50 mA
(typ.) λpeak
630
660
565
nm
Character Height
h
0.145
3.7
0.145
3.7
0.145
3.7
inch
mm
Time averaged luminous intensity1)
LED to LED intensity matching
Device to Device (one bin)
(min.)
(max.)
(max.)
(max.)
90
30
90
µcd/LED
1.8:1.0 1.8:1.0 1.8:1.0
1.5:1.0 1.5:1.0 1.5:1.0
1.9:1.0 1.9:1.0 1.9:1.0
Bin to Bin (adjacent bins)
1) Peak luminous intensity values can be calculated by multiplying these values by 7.
2006-01-23
3
PD243X, PD353X, PD443X
PD243X
Dimensions in mm (inch)
Pin 1 Indicator
EIA Date Code
Luminous
Intensity
Code
PD243X
OSRAM
Z
YYWW
V
2.54 (0.100) typ.
15.24 (0.600)
At Seating Plane
and centered
on package
0.46 (0.018) x 0.31 (0.012) typ.
1.27 (0.050)
±0.1 (0.004)
1.78 (0.070) typ.
25.4 (1.000) max.
6.35 (0.250) 3.56 (0.140)
3.18 (0.125)
Pin 1
Location
Tolerance: 0.51 (0.020)
IDOD5016
PD353X
Dimensions in mm (inch)
Pin 1 Identifier and ESD Warning
11.43 (0.450)
EIA Date Code
Part No.
Luminous
Intensity
Code
PD353X
OSRAM
Z
YYWW
V
2.54 (0.100) typ.
0.46 (0.018) x 0.31 (0.012) typ.
15.24 (0.600)
At Seating Plane
and centered
on package
6.35 (0.250)
35.56 (1.400) max.
8.89 (0.350) typ.
5.08 (0.200) typ.
4.45 (0.175)
Tolerance: 0.25 (0.010) unless max.
IDOD5017
2006-01-23
4
PD243X, PD353X, PD443X
PD443X
Dimensions in mm (inch)
Pin 1 Indicator
Part No.
EIA Date Code
Luminous
15.24 (0.600)
Intensity
Code
PD443X
OSRAM
Z
YYWW
V
15.24 (0.600) typ.
2.54 (0.100) typ.
At seating plane
and centered
on package
±0.05 (0.002)
0.46 (0.018) x 0.31 (0.012) typ.
7.62 (0.300)
38.1 (1.500) max.
9.53 (0.375) typ.
1.27 (0.050)
6.86 (0.270) typ.
Tolerance: 0.51 (0.020)
IDOD5018
Top View
20
11
Digit 3
Digit 2
Digit 1
Digit 0
1
10
20
11
Digit 3
Digit 2
Digit 1
Digit 0
1
20
10
11
Digit 3
Digit 2
Digit 1
Digit 0
1
10
IDPA5109
2006-01-23
5
PD243X, PD353X, PD443X
Timing Characteristics—Data “Write” Cycle
Timing Characteristics—Data “Read” Cycle
2.0 V
0.8 V
CE0, CE1
2.0 V
0.8 V
*
CE0, CE1
*
T
CES
T
CEH
T
CES
T
CEH
2.0 V
0.8 V
A0, A1
D0–D6
2.0 V
0.8 V
*
*
A0–A3
D0–D6
*
*
T
AS
T
AH
T
AS
T
AH
2.0 V
0.8 V
2.0 V
0.8 V
DATA OUT
T
DS
T
DH
T
DH
T
DD
T
RI
2.0 V
0.8 V
RD
2.0 V
0.8 V
*
*
*
*
T
RS
T
RH
WR
RD
T
WS
T
WH
WR
2.0 V
0.8 V
2.0 V
0.8 V
T
W
T
R
T
ACC
T
RACC
Notes:
3. These waveforms are not edge triggered.
1. Wait 1.0 µs between any Reads or Writes after writing a Control
Word with a Clear (D7=1). Wait 1.0 µs between any Reads or
Writes after Clearing a Control Word with a Clear (D7=0). All
other Reads and Writes can be back to back.
4. Data out voltages are measured with 100 pF on the data bus
and the ability to source =–40 mA and sink=1.6 mA The rise and
fall times are 60 ns. VOL=0.4 V, VOH=2.4 V.
2. All input voltages are VIL=0.8 V, VIH=2.0 V.
Switching Specifications (VCC=4.5 V)
Write Cycle Timing
Switching Specifications (VCC=4.5 V)
Read Cycle Timing
Para-
meter
Description
Specification Minimum
Para-
meter
Description
Specification Minimum
–40°C 25°C 85°C Units
–40°C 25°C 85°C Units
(1)
TCLR
Clear RAM
1.0
1.0
1.0
10
0
1.0
1.0
10
0
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TAS
TCES
TWS
TDD
TR
Address Setup
Chip Enable
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
(1)
TCLRD
TAS
Clear RAM Disable 1.0
0
0
Address Setup
10
0
Write Enable Setup 20
30
150
175
0
40
175
200
0
TCES
TRS
Chip Enable Setup
Data Delay Time
Read Pulse
100
Read Enable Setup 10
10
30
70
30
30
0
10
50
90
40
40
0
150
0
TDS
Data Setup
20
60
20
20
0
TAH
TDH
TTRI
Address Hold
Data Hold
TW
Write Pulse
0
0
0
TAH
Address Hold
Data Hold
Time to Tristate
(Max. time)
30
40
50
TDH
TCEH
TRH
TACC
TCEH
TWH
Chip Enable Hold
Write Enable Hold
0
0
0
ns
ns
ns
Chip Enable Hold
Read Enable Hold
30
200
40
245
50
290
20
90
30
110
40
140
TACC
Total Access
Time =Setup
Time + Read
Time +Time to
Tristate
Total Access
Time =Setup
Time + Write
Time +Hold Time
(1)
TWAIT
Wait Time between
Reads
0
0
0
ns
2006-01-23
6
PD243X, PD353X, PD443X
DC Characteristics at 25°C
Parameter
Limits
Min.
4.5
Conditions
Typ.
5.0
Max.
5.5
Units
VCC
Volts
mA
Nominal
ICC (Blank)
—
2.5
3.5
VCC=5.0 V, A2=1, all other inputs low.
ICC 80 LEDs/unit (100% Bright)
—
PD243X
PD353X
PD443X
115
145
150
130
165
170
mA
mA
mA
VCC=5.0 V
VCC=5.0 V
VCC=5.0 V
VIL
—
—
—
—
—
—
—
—
—
—
0.8
—
Volts
Volts
µA
VCC=4.5 V to 5.5 V
VCC=4.5 V to 5.5 V
VCC=4.5 V to 5.5 V, VIN=0.8 V
VCC=4.5 V to 5.5 V
VCC=4.5 V to 5.5 V
VCC=4.5 V, VOH=2.4 V
VCC=4.5 V, VOL=0.4 V
—
VIH
2.0
25
IIL (except D0 to D7) (1)
100
0.4
—
VOL
—
Volts
Volts
mA
VOH
2.4
–8.9
1.6
—
IOH
—
IOL
—
mA
Data I/O Bus Loading
100
240
pF
Clock I/O Bus Loading
—
pF
—
1)
D0 to D7 have no pull-up resistors so current is negligible.
Pin Assignments and Definitions
Pin Function Definition
Pin Function Definition
1
RD
Active low, will enable a processor to read all
registers in the display.
11
WR
Write. Active low. If the device is selected, a
low on the write input loads the data into mem-
ory.
2
CLK I/O
If CLK SEL (pin 3) is low, then expect an exter- 12
nal clock source into this pin. If CLK SEL is
high, then this pin will be the master or source
into this pin. If CLK SEL is high, then this pin
will be the master or source for all other
devices which have CLK SEL low.
D7
Data Bus bit 7 (MSB).
3
4
CLKSEL
RST
CLOCK SELECT determines the action of pin
2. CLK I/O, see the section on Cascading for
an example.
13
D6
D5
Data Bus bit 6.
Data Bus bit 5.
Reset. Used to synchronize blinking. Will not
clear the display. The reset pulse should be
less than 1 ms
14
5
CE1
CE0
A2
Chip enable (active high).
Chip enable (active low).
Address input (MSB).
Address input.
15
16
17
18
19
20
D4
D3
D2
D1
D0
VCC
Data Bus bit 4.
6
Data Bus bit 3.
7
Data Bus bit 2.
8
A1
Data Bus bit 1.
9
A0
Address input (LSB).
Ground.
Data Bus bit 0 (LSB).
Positive power pin.
10
GND
2006-01-23
7
PD243X, PD353X, PD443X
Functional Description
Input Buffering
The block diagram includes 5 major blocks and internal registers
(indicated by dotted lines).
If a cable length of 6 inches or more is used, all inputs to the display
should be buffered with a tri-state non-inverting buffer mounted as
close to the display as conveniently possible. Recommended
buffers are: 74LS245 for the data lines and 74LS244 for the control
lines.
Display Memory consists of a 5 x 8 bit RAM block. Each of the
four 8-bit words holds 7-bits of ASCII data (bits D0–D6) and an
attribute select bit (Bit D6). The fifth 8-bit memory word is used
as a control word register. A detailed description of the control
register and its functions can be found in the Control Word sec-
tion. Each 8-bit word is addressable and can be read from or writ-
ten to.
Block Diagram
The Control Logic dictates all of the features of the display
device and is discussed in the Control Word section of this data
sheet.
The Character Generator converts the 7-bit ASCII data into the
proper dot pattern for the 128 characters shown in the character
set chart.
The Clock Source can originate either from the internal oscillator
clock or from an external source—usually from the output of
another display in a multiple module array.
14
Control
Reg
1 x 8
128 Char
ROM
128 x 5
8
7
Display Memory
(RAM) 4 x 8
D0-D7
8
4
15
20
1
CE0, CE1
A0-A2
RD, WR
Decode
and
Mux
Output
Control
Logic
5
Output
Latch
The Display Multiplexer controls all display output to the digit
drivers so no additional logic is required for a display system.
1
The Column Drivers are connected directly to the display.
CLK SEL
XCLK
RST
3
OSC
Logic
Display
Multiplexer
Column
Drivers
The Display has four digits. Each of the four digits is com-prised of
35 LEDs in a 5 x 7 dot array which makes up the alphanumeric
characters.
3
3
20
The intensity of the display can be varied by the Control Word in
steps of 0% (Blank), 25%, 50%, and full brightness.
Row
Drivers
The Reset pin when activated clears the internal counter. A reset is
usually done after power up and is of very short duration-nanosec-
onds or microseconds. If the reset pin is held low for a longer time
(milliseconds) some or all LEDs in the bottom row may light up. The
appearance of lit LEDs during a “reset” is not an indication of a mal-
functioning part. It is advisable to keep the reset pulse as short as
possible to avoid displaying a row of lit LEDs.
Display
IDBD5065
Mode Selection
CEO
CE1
1
RD
0
WR
0
Operation
None
Microprocessor Interface
The interface to the microprocessor is through the address lines.
(A0–A2), the data bus (D0–D7), two chip select lines (CE0, CE1),
and read (RD) and write (WR) lines.
0
1
X
X
X
X
X
None
The CE0 should be held low when executing a read, or write oper-
ation. CE1 must be held high.
0
X
X
None
X
1
1
None
The read and write lines are both active low. During a valid read
the data input lines (D0–D7) become outputs. A valid write will
enable the data as input lines.
0=Low logic level, 1=High logic level, X=Don’t care
Data Input Commands
CEO CE1 RD
WR A2
A1
X
0
A0
X
0
D7
X
X
0
D6
X
X
0
D5
X
X
1
D4
X
X
0
D3
X
X
0
D2
X
X
1
D1
X
X
0
D0
X
X
0
Operation
1
0
0
0
0
0
0
0
1
1
1
1
1
1
X
0
1
1
1
1
1
X
1
0
0
0
0
0
X
1
1
1
1
1
1
No Change
Read Digit 0 Data to Bus
($) Written to Digit 0
(W) Written to Digit 1
(f) Written to Digit 2
(3) Written to Digit 3
0
0
0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
X
X
X
X
X
X
X
Char. Written to Digit 0 and
Cursor Enabled
2006-01-23
8
PD243X, PD353X, PD443X
There are five registers within the display. Four of these registers
are used to hold the ASCII/attribute code of the four display char-
acters. The fifth register is the Control Word, which is used to blink,
blank, clear, or dim the entire display, or to change the presenta-
tion (attributes) of individual characters.
Control Word
When address bit A2 is taken low, the Control Word is accessed.
The same Control Word appears in all four of the lower address
spaces of the display. Through the Control Word, the display can
be cleared, the lamps can be tested, display brightness can be
selected, and attributes can be set for any characters which have
been loaded with their most significant bit (D7) set high.
Adressing
The addresses within the display device are shown below. Digit 0
is the rightmost digit of the display, while digit 3 is on the left.
Although there is only one Control Word, it is duplicated at the four
address locations 0–3. Data can be read from any of these loca-
tions. When one of these locations is written to, all of them will
change together.
Brightness (D0, D1): The state of the lower two bits of the Control
Word are used to set the brightness of the entire display, from 0%
to 100%. The table below shows the correspondence of these bits
to the brightness.
D7 D6 D5 D4 D3 D2 D1 D0 Operation
Address
Contents
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
Blank
A2
0
A1
X
0
A0
X
0
25% brightness
50% brightness
Full brightness
Control Word
Digit 0 (rightmost)
Digit 1
1
1
0
1
X=don't care
1
1
0
Digit 2
Attributes (D2–D4): Bits D2, D3, and D4 control the visual
attributes (i.e., blinking) of those display digits which have been
written with bit D7 set high. In order to use any of the four
attributes, the Cursor Enable bit (D4 in the Control Word) must be
set. When the Cursor Enable bit is set, and bit D7 in a character
location is set, the character will take on one of the following dis-
play attributes.
1
1
1
Digit 3 (leftmost)
Bit D7 of any of the display digit locations is used to allow an at-
tribute to be assigned to that digit. The attributes are discussed in
the next section. If Bit D7 is set to a one, that character will be dis-
played using the attribute. If bit D7 is cleared, the character will dis-
play normally.
Control Word Format
D7
D6
D5
D4
D3
D2
D1
Brightness
D1 D0 Brightness
D0
Lamp
Test
Attribute
Enable
Clear
Blink
Attributes
0
0
1
1
0
1
0
1
0% (blank)
25%
50%
D3 D2 Attributes
0
0
Display cursor instead
of character
100%
0
1
1
0
Blink character
Display blinking cursor
instead of character
Alternate character
with cursor
1
1
D4 Attribute Enable
0
1
Disable above attributes
Enable above attributes
D5 Blink
0
1
Blink attribute disabled
Blink entire display
D6 Lamp Test
0
1
Standard operation
Display all dots at 50% brightness
D7 Clear
0
1
Standard operation
Clear entire display
IDCW5163
2006-01-23
9
PD243X, PD353X, PD443X
D7 D6 D5 D4 D3 D2 D1 D0 Operation
D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
0
0
0
X
X
B
B
Disable high-
light attribute
0
0
1
X
X
X
B
B
Blinking display
0
0
0
1
0
0
B
B
Display cursor*
instead of
character
Lamp Test (D6): When the Lamp Test bit is set, all dots in the
entire display are lit at half brightness. When this bit is cleared, the
display returns to the characters that were showing before the
lamp test.
0
0
0
0
0
0
1
1
0
1
1
0
B
B
B
B
Blink single
character
D7 D6 D5 D4 D3 D2 D1 D0 Operation
Display blink-
ing cursor*
instead of char-
acter
0
1
0
X
X
X
X
X
Lamp test
Clear Data (D7): When D7 is set (D7=1) in the Control Word, all (dis-
play) memory bits are reset to zero and the display goes blank.
0
0
0
1
1
1
B
B
Alternate char-
acter with cur-
sor*
D7 D6 D5 D4 D3 D2 D1 D0 Operation
*“Cursor”= all dots in a single character space lit to half brightness
X=Don't care
1
0
X
X
X
X
X
X
Clear
B=Depends on the selected brightness.
A second control word must be written into the chip with D7 reset
(D7=0) to set up attributes and brightness levels.
Attributes are non-destructive. If a character with bit D7 set is
replaced by a cursor (Control Word bit D4 is set, and D3=D2=0)
the character will remain in memory and can be revealed again by
clearing D4 in the Control Word.
The SMC-4740 oscillator is designed to drive up to 16 displays
with input loading of 15 pF each.
The general requirements for cascading 16 displays are:
1.Determine the correct address for each display.
2.Tie CE0 to ground and use CE1 from an address.
Blink (D5): The entire display can be caused to blink at a rate of
approximately 2.0 Hz by setting bit D5 in the Control Word. This blink-
ing is independent of the state of D7 in all character locations.
3.Select one of the displays to provide the clock for the
other displays.
To synchronize the blink rate in a bank of these devices, it is nec-
essary to tie all devices' clocks and resets together as described in
a later section of this data sheet.
4.Tie CLKSEL to ground on other displays.
5.Use RST to synchronize the blinking between the displays.
Cascading Diagram
RST
RD
WR
VCC
WR RD RST CLK CLK
I/O SEL
Programmable Display
WR RD RST CLK CLK
I/O SEL
Programmable Display
14 more displays
in between
D0-D7 A0-A2 CE0 CE1
D0-D7 A0-A2 CE0
CE1
Data I/O
Address
A4
A5
A6
Address Decode Chip 1 to 14
Address
Decoder
IDCD5032
2006-01-23
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PD243X, PD353X, PD443X
How to Load Information Into the Display
Add Another Blinking Character
Information loaded into the display can be either ASCII data or
Control Word data. The following procedure (see also Typical
Loading Sequence) will demonstrate a typical loading sequence
and the resulting visual display. The word STOP is used in all of
the following examples.
Step 8
Step 9
Into the left hand digit, load the hex code “D3”
which gives an “S” with the D7 bit added as a
control bit. The display should show “STOP”
with flashing “O” and a flashing “S.”
Alternate Character/Cursor Enable
Set Brightness
Load enable alternate character/cursor into the
control word register. The display now should
show “STOP” with the “O” and the “S” alternating
between the letter and cursor (all dots lit).
Step 1
Set the brightness level of the entire display to
your preference (example: 100%)
Load Four Characters
Initiate Four Character Blinking
Step 2
Step 3
Step 4
Step 5
Load an “S” in the left hand digit.
Load a “T” in the next digit.
Load an “O” in the next digit.
Load a “P” in the right hand digit.
(Regardless of Control Bit setting)
Load enable display blinking. The display now
should show the entire word “STOP” blinking.
Step 10
If you loaded the information correctly, the display
now should show the word “STOP.”
Blink a Single Character
Step 6
Step 7
Into the digit, second from the right, load the hex
code “CF,” which is the code for an “O” with the
D7 bit added as a control bit.
Note:
The “O” is the only digit which has the control bit
(D7) added to normal ASCII data.
Load enable blinking character into the control
word register. The display should show “STOP”
with a flashing “O”.
Typical Loading Sequence
CEO CE1 RD WR
A2
L
A1
X
H
H
L
A0
X
H
L
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
1
Display
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
0
1
0
1
0
0
1
1
S
0
1
0
1
0
1
0
0
ST
H
L
0
1
0
0
1
1
1
1
STO
L
0
1
0
1
0
0
0
0
STOP
STOP
STO*P
S*TO*P
S†TO†P
S*T*O*P*
L
H
X
H
X
X
1
1
0
0
1
1
1
1
X
H
X
X
0
0
0
1
0
1
1
1
H
L
1
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
L
0
0
1
0
0
0
1
1
* Blinking character
† Character alternating with cursor (all dots lit)
2006-01-23
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PD243X, PD353X, PD443X
Electrical and Mechanical Considerations
Power Down Sequence
The CMOS IC of the display is designed to provide resistance to
both Electrostatic Discharge Damage and Latch Up due to voltage
or current surges. Several precautions are strongly recommended
to avoid overstressing these built-in safeguards.
1.Float all active signals by tri-stating the inputs to the display.
2.Turn off the power to the display.
Soldering Considerations
These displays can be hand soldered with SN63 solder using a
grounded iron set to 260°C.
ESD Protection
Display users should be careful to handle the devices consistent
with Standard ESD protection procedures. Operators should wear
appropriate wrist, ankle or feet ground straps and avoid clothing
that collects static charges. Work surfaces, tools and transport car-
riers that come into contact with unshielded devices or assemblies
should also be appropriately grounded.
Wave soldering is also possible following these conditions: Pre-
heat that does not exceed 93°C on the solder side of the PC board
or a package surface temperature of 85°C. Water soluble organic
acid flux (except carboxylic acid) or rosin-based RMA flux without
alcohol can be used.
Wave temperature is 245°C ±5°C with a dwell between 1.5 sec to
3.0 sec. Exposure to the wave should not exceed temperatures
above 260°C, for 5 sec at 1.59 mm (0.063") below the seating
plane. The packages should not be immersed in the wave.
Latch up Protection
Latch up is a condition that occurs in CMOS ICs after the input
protection diodes have been broken down. These diodes can be
reversed through several means:
Voltage Transient Suppression
VIN<GND, VIN>VCC + 0.5 V, or through excessive currents forced
on the inputs. When these situations exist, the IC may develop the
response of an SCR and begin conducting as much as one amp
through the VCC pin. This destructive condition will persist (latched)
until device failure or the device is turned off.
It has become common practice to provide 0.01 µF bypass capac-
itors liberally in digital systems. Like other CMOS circuitry, the
Intelligent Display controller chip has very low power consumption
and the usual 0.01 µF would be adequate were it not for the
LEDs. To prevent power supply transients, capacitors with low
inductance and high capacitance at high frequencies are
required. This suggests a solid tantalum or ceramic disc for high
frequency bypass. For multiple display module systems distribute
the bypass capacitors evenly, keeping capacitors as close to the
power pins as possible. Use a 0.01 µF capacitor for each display
module and a 22 µF for every third display module.
The Voltage Transient Suppression Techniques and buffer inter-
faces for longer cable runs help considerably to prevent latch con-
ditions from occurring. Additionally, the following Power Up and
Power Down sequence should be observed.
Power up Sequence
1. Float all active signals by tri-stating inputs to displays.
2. Apply VCC and GND to the display.
Notes:
3. Apply active signals to the displays by enabling all input
signals per application.
1. A2 must be held high for ASCII data.
2. Bit D7=1 enables attributes for the assigned digit.
Character Set
D0
D1
D2
D3
0
0
0
0
0
1
0
0
0
1
0
1
0
0
2
1
1
0
0
3
0
0
1
0
4
1
0
1
0
5
0
1
1
0
6
1
1
1
0
7
0
0
0
1
8
1
0
0
1
9
0
1
0
1
A
1
1
0
1
B
0
0
1
1
C
1
0
1
1
D
0
1
1
1
E
1
1
1
1
F
ASCII
CODE
D6 D5 D4 HEX
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
IDCS5087
2006-01-23
12
PD243X, PD353X, PD443X
Revision History: 2006-01-23
Previous Version: 2004-12-09
Page
Subjects (major changes since last revision)
Lead free device
Date of change
all
2006-01-23
Attention please!
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved. Due to technical requirements components may contain
dangerous substances. For information on the types in question please contact our Sales Organization.
If printed or downloaded, please find the latest version in the Internet.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.
By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing
material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs
incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose! Critical
components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS.
1) A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure
of that life-support device or system, or to affect its safety or the effectiveness of that device or system.
2) Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human
life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered.
2006-01-23
13
PD243X, PD353X, PD443X
Post Solder Cleaning Procedures
Optical Considerations
The least offensive cleaning solution is hot D.l. water (60°C) for
less than 15 minutes. Addition of mild saponifiers is acceptable.
Do not use commercial dishwasher detergents.
The character heights of these displays allows readability up to
eight feet. Proper filter selection allows the user to build a display
that can be used over this distance.
For faster cleaning, solvents may be used. Carefully choose the
solvents as some may chemically attack the package. Maximum
exposure should not exceed two minutes at elevated tempera-
tures. Acceptable solvents are: TF (trichlorotrifluoroethane), TA,
111 Trichloroethane, and unheated acetone. (1)
Filters allow the user to enhance the contrast ratio between a lit
LED and the character background. This will maximize discrimina-
tion of different characters as perceived by the display user. The
only limitation is cost. So first consider the ambient lighting envi-
ronment to maximize the cost benefit ratio for using filters.
Incandescent (with almost no green) or fluorescent (with almost no
red) lights do not have the flat spectral response of sunlight. Plas-
tic band-pass filters are inexpensive and effective in optimizing
contrast ratios. The PD2435/3535/4435 is high efficiency red dis-
play and should be matched with a long wavelength pass filter in
the 570 nm to 590 nm range. The PD2436/3536/4436 is a stan-
dard red display and should be matched with a long wavelength
pass filter in the 600 nm to 620 nm range. The PD2437/3537/4437
should be matched with a yellow-green band-pass filter that peaks
at 565 nm. For displays of multiple colors, neutral density grey fil-
ters offer the best compromise.
Note:
1)
Acceptable commercial solvents are: Basic TF Arklone P.
Genesolv D, Genesolv DA, BlacoTron TF and Blaco-Tron TA.
Do not use solvents containing alcohol, methanol, methylene chlo-
ride, ethanol, TP35, TCM, TMC, TMS+, TE, and TES. Since many
commercial mixtures exist, you should contact your preferred sol-
vent vendor for chemical composition information. Some major sol-
vent manufacturers are: Allied Chemical Corporation, Specialty
Chemical Division, Morristown, NJ; Baron-Blakeslee, Chicago, IL;
Dow Chemical, Midland, Ml; E.l. DuPont de Nemours & Co., Wilm-
ington, DE.
Additional contrast enhancement can be gained through shading
the displays. Plastic band-pass filters with built-in louvers offer the
“next step up” in contrast improvement. Plastic filters can be fur-
ther improved with anti-reflective coatings to reduce glare. The
trade-off is “fuzzy” characters. Mounting the filters close to the dis-
play reduces this effect. Care should be taken not to overheat the
plastic filters by allowing for proper air flow.
For further information refer to Appnotes 18 and 19.
An alternative to soldering and cleaning the display modules is to
use sockets. Naturally, 20 pin DIP sockets 15.24 mm (0.600")
wide with 2.54 mm (0.100") centers work well for single displays.
Multiple display assemblies are best handled by longer SIP sock-
ets or DIP sockets when available for uniform package alignment.
Socket manufacturers include: Aries Electronics, Inc., French-
town, NJ; Garry Manufacturing, New Brunswick, NJ; Robin-
son-Nugent, New Albany, IN; and Samtec Electronic Hardware,
New Albany, IN.
Optimal filter enhancements for any condition can be gained
through the use of circular polarized, anti-reflective, band-pass fil-
ters. The circular polarizing further enhances contrast by reducing
the light that travels through the filter and reflects back off the dis-
play to less than 1%. Proper intensity selection of the displays will
allow 10,000 foot candle sunlight viewability.
For further information refer to Appnote 22.
Several filter manufacturers supply quality filter materials. Some of
them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homa-
lite, Wilmington, DE; 3M Company, Visual Products Division, St.
Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge,
MA; Marks Polarized Corporation, Deer Park, NY; Hoya Optics,
Inc., Fremont, CA.
One last note on mounting filters: recessing display and bezel
assemblies is an inexpensive way to provide a shading effect in
overhead lighting situations. Several Bezel manufacturers are:
R.M.F. Products, Batavia, IL; Nobex Components, Griffith Plastic
Corp., Burlingame, CA; Photo Chemical Products of California,
Santa Monica, CA; I.E.E.Atlas, Van Nuys, CA.
See Appnote 23.
Published by
OSRAM Opto Semiconductors GmbH
Wernerwerkstrasse 2, D-93049 Regensburg
www.osram-os.com
© All Rights Reserved.
2006-01-23
14
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