STK682-010-E [ONSEMI]
Bipolar Ultra-micro Stepping Motor Driver;
| 型号： | STK682-010-E |
| 厂家： | 
ONSEMI |
| 描述： | Bipolar Ultra-micro Stepping Motor Driver 电动机控制 |
| 文件： | 总20页 (文件大小：600K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA2252A
STK682-010-E
Thick Film Hybrid IC
2-phase Stepping Motor Driver
http://onsemi.com
Overview
The STK682-010-E is a hybrid IC for use as a Bipolar, 2-phase stepping motor driver with PWM current control.
Function
Output on-resistance (High side 0.3 Ω, Low side 0.25 Ω, Total 0.55 Ω ; Ta = 25C, I = 2.5A)
O
VMmax=36V(DC), Iopmax=3.0A
2, 1-2, W1-2, 2W1-2, 4W1-2, 8W1-2, 16W1-2, 32W1-2 phase excitation are selectable
With built-in automatic half current maintenance energizing function
Over current protection circuit
Thermal shutdown circuit
Input pull down resistance
With reset pin and enable pin
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Supply voltage
Symbol
VMmax
Conditions
Ratings
36.0
Unit
V
Peak output current
Logic input voltage
VREF input voltage
Iopmax
3.0
6.0
A
V
VINmax
VREFmax
6.0
V
Operating substrate temperature Tc
Storage temperature Tstg
20 to +105
40 to +125
C
C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of this data sheet.
Semiconductor Components Industries, LLC, 2013
December, 2013
D1813HK 018-13-0030/D1113HK No.A2252-1/20
STK682-010-E
Recommended Operating Conditions at Tc = 25C
Parameter
Supply voltage range
Logic input voltage range
Symbol
VM
Conditions
Ratings
Unit
V
9.0 to 32.0
VIN
V
CC
0 to 5.0
0 to 5.0
0 to 3.0
3.0
V
V
V
A
A
A
V
CC
input voltage range
VREF input voltage range
Output current1
VREF
Io1
1-2 Phase-ex, Tc 90C
1-2 Phase-ex, Tc=105C
2 Phase-ex, Tc=105C
Output current2
Io2
2.5
Output current3
Io3
1.8
Electrical Characteristics at Tc 25C, V
= 5V
CC
Ratings
typ
Parameter
Standby mode current drain
Current drain
Symbol
IMstn
IM
Conditions
Unit
min
150
max
100
70
VCC=”L”
μA
VCC=”H”, ENABLE="H"
No Load
3.3
4.6
mA
Design guarantee
Design guarantee
180
40
8
210
C
C
μA
μA
Thermal shutdown temperature
Thermal hysteresis width
TSD
∆TSD
IinL1
IinH1
3
15
VIN=0.8V
Logic pin input current
30
50
83
70
VIN=5V
V
CC
51
115
V
CC
pin input current
15pin=5V
μA
V
Vinh
Vinl
2.0
Logic input high-level voltage
Logic input low-level voltage
FDT pin high-level voltage
FDT pin middle-level voltage
FDT pin low-level voltage
Pins 2,3,16,17,18,19
Pins 2,3,16,17,18,19
Pin 6
0.8
V
Vfdth
Vfdtm
Vfdtl
3.5
1.1
V
3.1
0.8
Pin 6
V
Pin 6
V
Fch
58
83
10
1
108
kHz
μA
V
Chopping frequency
C1=100pF
Iosc1
Vtup1
Vtdown1
Iref
Chopping frequency
Chopping oscillator circuit
0.5
threshold voltage
V
0.5
μA
mV
Hz
μs
VREF pin input voltage
DOWN output residual voltage
Hold current switching frequency
Blanking time
VREF=1.5V, CLK=10kHz
Idown=1mA, CLK=Low
VolDO
Falert
Tb1
40
1.6
1
Output block
Ronu
Rond
0.30
0.25
0.42
0.35
I =2.0A, high-side ON resistance
O
I =2.0A, low-side ON resistance
O
Ω
Ω
Output on-resistance
Output leakage current
Diode forward voltage
Ioleak
VD
50
μA
V
VM=36V
1.1
1.4
ID=2.0A
VRF
300
mV
Current setting reference voltage
VREF=1.5V, Current ratio 100%
Output short-circuit protection block
Timer latch time
Tscp
256
μs
No.A2252-2/20
STK682-010-E
Package Dimensions
unit : mm
SIP19 29.2x14.4
CASE 127CF
ISSUE O
19
1
No.A2252-3/20
STK682-010-E
Block diagram
OUT1A
12
OUT2B
NFA
OUT2A
NFB
OUT1B
1
9
11
8
7
VM
VREG2
14
Regulator 2
PGNDA
PGNDB
VREG1
1.2k
Regulator 1
Output control logic
VREF
DOWN
Current select
circuit
Current select
circuit
5
Oscillator
Decay Mode
setting circuit
OSC2
6
4
10
18
3
19
1
15
16 17
2
GND
CLK
PGND
VCC
M1 M2 M3
FDT OSC1
ENABLE
CW/CCW
Application Circuit Example
VM
CW/CCW
CLK
14
7
2
VM=24V
3
OUT2B
OUT1B
STK682-010-E
VREF
5V
5
9
R1
VCC
M1
15
16
OUT2A
OUT1A
11
13
M2
17
18
19
M3
ENABLE
6
4
1
FDT
OSC1
GND
C3
C2
10
PGND
12
8
NFB
NFA
RFA
R2
RFB
C1
GND
No.A2252-4/20
STK682-010-E
Pin Functions
Pin No.
1
Pin symbol
GND
Pin Functions
Circuit GND
2
3
CW/CCW
CLK
Forward / Reverse signal input
Clock pulse signal input
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
OSC1
VREF
FDT
OUT2B
NFB
OUT1B
PGND
OUT2A
NFA
OUT1A
VM
Chopping frequency setting capacitor connection
Constant-current control reference voltage input
Decay mode select voltage input
B phase OUTB output
B phase current sense resistance connection
B phase OUTA output
Power GND
A phase OUTB output
A phase current sense resistance connection
A phase OUTA output
Motor supply connection
VCC
M1
M2
M3
Chip enable input
Excitation-mode switching pin
Output enable signal input
ENABLE
No.A2252-5/20
STK682-010-E
Equivalent circuit diagram
Pin No.
Pin type
CLK
Equivalent Circuit Diagram
3
2
CW/CCW
ENABLE
M3
M2
M1
19
18
17
16
15
VCC
Internal reset
Input pin
13
10
14
12
11
9
OUT1A
PGND
VM
NFA
OUT2A
OUT1B
NFB
8
7
OUT2B
5
VREF
4
OSC1
6
FDT
No.A2252-6/20
STK682-010-E
Description of functions
(1) Excitation setting method
Set the excitation setting as shown in the following table by setting M1 pin, M2 pin and M3 pin
Input signal
M2
Initial position
A phase
M3
M1
MODE (Excitation)
current
100%
100%
100%
100%
100%
100%
100%
100%
B phase current
L
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
2 Phase
1-2 Phase
100%
0%
0%
0%
0%
0%
0%
0%
W1-2 Phase
2W1-2 Phase
4W1-2 Phase
8W1-2 Phase
16W1-2 Phase
32W1-2 Phase
L
H
H
H
H
The initial position is also the default state at start-up and excitation position at counter-reset in each excitation
mode
(2) Output current setting
Output current is set as shown below by the VREF pin (applied voltage) and a resistance value between
NFA (B) pin and GND.
I
= (VREF / 5) / NFA (B) resistance
OUT
* The setting value above is a 100% output current in each excitation mode.
(Example) When VREF=1.5V and NFA (B) resistance is 0.3 Ω, the setting current is shown below.
I
= (1.5 V / 5) / 0.3 Ω = 1.0 A
OUT
(3) Chip enable terminal/ VCC function
When Chip enable terminal/ V
turned OFF.
pin is at low levels, the IC enters stand-by mode, all logic is reset and output is
pin is at high levels, the stand-by mode is released
CC
When Chip enable terminal/ V
CC
(4) Step pin function
CLK pin step signal input allows advancing excitation step
Input
Operation
V
CC
L
CLK
*
Stand-by mode
H
H
Excitation step feed
Excitation step hold
No.A2252-7/20
STK682-010-E
(5) Forward / reverse switching function
CW/CCW
Operation
CW
L
H
CCW
CCW mode
CW / CCW
CLK
CW mode
CW mode
Excitation
position
(1) (2) (3) (4) (5) (6) (5) (4) (3) (4) (5)
A phase output
B phase output
The internal D/A converter proceeds by a bit on the rising edge of the step signal input to the CLK pin. In addition,
CW and CCW mode are switched by CW and CCW pin setting.
In CW mode, the B phase current is delayed by 90 relative to the A phase current. In CCW mode, the B phase
current is advanced by 90 relative to the A phase current.
(6) Output enable function
When the ENABLE pin is set Low, the output is forced OFF and goes to high impedance. However, the internal logic
circuits are operating, so the excitation position proceeds when the CLK is input. Therefore, when ENABLE pin is
returned to High, the output level conforms to the excitation position proceeded by the CLK input.
ENABLE
CLK
A phase output
0%
B phase output
High impedance output
No.A2252-8/20
STK682-010-E
(7) DECAY mode
The DECAY mode of the output current becomes only MIXED DECAY.
DECAY method
SLOW DECAY
MIXED DECAY
FAST DECAY
FDT voltage
3.5V to
1.1V to 3.1V or OPEN
to 0.8V
(8) Chopping frequency setting function
Chopping frequency is set as shown below by a capacitor between OSC1 pin and GND.
-6
Fch = 1 / (C1+20pF / 10×10 ) (Hz)
(Example) When Cosc1=100pF, the chopping frequency is shown below.
-12
-6
Fch = 1 / ((20+ 100)×10
/ 10×10 ) (Hz) = 83.3 (kHz)
Note
The 20pF is a stray capacitance which is involved by the package of STK682-010-E.
(9) Output short-circuit protection circuit
Build-in output short-circuit protection circuit makes output to enter in stand-by mode. This function prevents the IC
from damaging when the output shorts circuit by a voltage short or a ground short, etc. When output short state is
detected, short-circuit detection circuit starts the operating and output is once turned OFF. After the timer latch time
(typ : 256μs), output is turned ON again. Still the output is at short state, the output is turned OFF and fixed in
stand-by mode.
When output is fixed in stand-by mode by output short protection circuit, output is released the latch by setting Chip
enable terminal/ V ="L"
CC
(10) Internal DOWN pin
The DOWN pin is an open drain connection.
This pin is turned ON when no rising edge of CLK between the input signals while a period determined by a
capacitor between OSC2 and GND, and outputs at low levels.
The DOWN pin output in once turned ON, is turned OFF at the next rising edge of CLK.
Holding current switching time (0.6sectyp) is set by an internal capacitor between OSC2 pin and GND.
(11) Output current tolerance
STK682-010-E Output current tolerance Io Tc
3.5
3
2.5
2
1-2 phase excitation
and more
1.5
2 phase excitation
1
0.5
0
0
10 20
30
40
50 60
70
80
90 100 110
Operating substrate temperature Tc C
No.A2252-9/20
STK682-010-E
(12) When mounting multiple drivers on a single PC board
When mounting multiple drivers on a single PC board, the GND design should mount a VCC
decoupling capacitor,C2 and C3, for each driver to stabilize the GND potential of the other drivers.
The key wiring points are as follows.
VM=24V
5V
5V
CW/CC
CW/CC
2
2
VM
VM
CLK
FDT
CLK
FDT
14
R1
14
STK682-010-E
7
R1
3
6
3
6
STK682-010-E
VREF
VREF
5
5
OUT2
OUT1
OUT2
OUT1
VCC
VCC
7
9
15
16
15
16
M1
M2
M1
M2
9
2phase
stepping
motor
2phase
17
18
19
4
17
18
19
4
stepping
motor
M3
M3
OUT
2A
OUT2A
OUT
ENABLE
11
13
ENABLE
11
OSC1
GND
OSC1
GND
OUT
13
1
1
PGND
PGND
8
8
10 12
10 12
NFB
RFB
NFA
RFA
NFB
RFB
R2
R2
NFA
RFA
C3
C2
C3
C2
C1
C1
GND
No.A2252-10/20
STK682-010-E
(13) Output current vector locus (1 step normalized 90)
100.0
66.7
33.3
0.0
0.0
33.3
66.7
100.0
Channel 2 current ratio (%)
No.A2252-11/20
STK682-010-E
(14) Current setting ratio in each excitation mode
32W1-2 phase(%)16W1-2 phase(%) 8W1-2 phase(%) 4W1-2 phase(%) 2W1-2 phase(%) W1-2 phase(%) 1-2 phase(%) 2 phase(%)
32W1-2 phase(%)16W1-2 phase(%)8W1-2 phase(%) 4W1-2 phase(%) 2W1-2 phase(%) W1-2 phase(%) 1-2 phase(%) 2 phase(%)
Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch
Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch
70 72
69 72 69 72
68 73
67 74 67 74 67 74
66 75
65 76 65 76
64 77
STEP
θ0
θ1
θ2
θ3
θ4
θ5
θ6
θ7
STEP
θ65
θ66
θ67
θ68
θ69
θ70
θ71
θ72
100
100
100
100
100
100
100
100
0
1
2
4
5
6
7
9
100
100
100
100
0
2
5
7
100
0
100
0
100
0
100
0
100
0
100
5
63 77 63 77 63 77 63 77
θ8
100 10 100 10 100 10 100 10
θ73
62 78
θ9
99 11
θ74
62 79 62 79
θ10
θ11
θ12
θ13
θ14
θ15
θ16
θ17
θ18
θ19
θ20
θ21
θ22
θ23
θ24
θ25
θ26
θ27
θ28
θ29
θ30
θ31
θ32
θ33
θ34
θ35
θ36
θ37
θ38
θ39
θ40
θ41
θ42
θ43
θ44
θ45
θ46
θ47
θ48
θ49
θ50
θ51
θ52
θ53
θ54
θ55
θ56
θ57
θ58
θ59
θ60
θ61
θ62
θ63
θ64
99 12 99 12
99 13
99 15 99 15 99 15
99 16
99 17 99 17
98 18
98 20 98 20 98 20 98 20 98 20
98 21
98 22 98 22
97 23
97 24 97 24 97 24
97 25
96 27 96 27
96 28
96 29 96 29 96 29 96 29
95 30
95 31 95 31
95 33
94 34 94 34 94 34
94 35
93 36 93 36
93 37
92 38 92 38 92 38 92 38 92 38 92 38
92 39
91 41 91 41
91 42
90 43 90 43 90 43
90 44
89 45 89 45
89 46
88 47 88 47 88 47 88 47
88 48
87 49 87 49
86 50
86 51 86 51 86 51
85 52
84 53 84 53
84 55
83 56 83 56 83 56 83 56 83 56
82 57
82 58 82 58
81 59
80 60 80 60 80 60
80 61
θ75
θ76
θ77
θ78
θ79
θ80
θ81
θ82
θ83
θ84
θ85
θ86
θ87
θ88
θ89
θ90
θ91
θ92
θ93
θ94
θ95
θ96
θ97
θ98
61 80
60 80 60 80 60 80
59 81
58 82 58 82
57 82
56 83 56 83 56 83 56 83 56 83
55 84
53 84 53 84
52 85
51 86 51 86 51 86
50 86
49 87 49 87
48 88
47 88 47 88 47 88 47 88
46 89
45 89 45 89
44 90
43 90 43 90 43 90
42 91
41 91 41 91
39 92
38 92 38 92 38 92 38 92 38 92 38 92
37 93
36 93 36 93
35 94
34 94 34 94 34 94
33 95
31 95 31 95
30 95
29 96 29 96 29 96 29 96
28 96
27 96 27 96
25 97
24 97 24 97 24 97
23 97
22 98 22 98
21 98
θ99
θ100
θ101
θ102
θ103
θ104
θ105
θ106
θ107
θ108
θ109
θ110
θ111
θ112
θ113
θ114
θ115
θ116
θ117
θ118
θ119
θ120
θ121
θ122
θ123
θ124
θ125
θ126
θ127
θ128
20 98 20 98 20 98 20 98 20 98
18 98
17 99 17 99
16 99
15 99 15 99 15 99
13 99
12 99 12 99
11 99
10 100 10 100 10 100 10 100
79 62 79 62
78 62
77 63 77 63 77 63 77 63
77 64
76 65 76 65
75 66
74 67 74 67 74 67
73 68
9
7
6
5
4
2
1
0
100
100
100
100
100
100
100
100
7
5
2
0
100
100
100
100
5
0
100
100
72 69 72 69
72 70
0
100
0
100
0
100
0 100
71 71 71 71 71 71 71 71 71 71 71 71 71 71 100 100
No.A2252-12/20
STK682-010-E
(15) Current wave example in each excitation mode (2 phase, 1-2 phase, W1-2 phase, 4W1-2 phase)
2 phase excitation (CW mode)
CLK
(%)
100
0
IA
(%)
-100
100
0
IB
-100
1-2 phase excitation (CW mode)
CLK
(%)
100
0
IA
IB
-100
(%)
100
0
-100
No.A2252-13/20
STK682-010-E
W1-2 phase excitation (CW mode)
CLK
(%)
100
IA
IB
0
-100
(%)
100
0
-100
4W1-2 phase excitation (CW mode)
STP
MO
(%)
100
50
I1
0
-50
-100
(%)
100
50
0
I2
-50
-100
No.A2252-14/20
STK682-010-E
(16) Current control operation
SLOW DECAY current control operation
When FDT pin voltage is a voltage over 3.5 V, the constant-current control is operated in SLOW
DECAY mode.
(Sine-wave increasing direction)
CLK
Setting current
Setting current
Coil current
Blanking Time
fchop
Current mode
CHARGE
SLOW
CHARGE
SLOW
(Sine-wave decreasing direction)
C LK
Setting current
C oil current
Setting current
B lanking Tim e
fchop
C urrent m ode
C H AR GE
B lanking Tim e
B lanking Tim e
SLO W
SLO W
SLO W
Each of current modes operates with the follow sequence.
The IC enters CHARGE mode at a rising edge of the chopping oscillation.
(A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1 μs, regardless of the current
value of the coil current (ICOIL) and set current (IREF) ).
After the period of the blanking time, the IC operates in CHARGE mode until ICOIL ≥ IREF. After that,
the mode switches to the SLOW DECAY mode and the coil current is attenuated until the end of a
chopping period.
At the constant-current control in SLOW DECAY mode, following to the setting current from the coil
current may take time (or not follow) for the current delay attenuation.
No.A2252-15/20
STK682-010-E
FAST DECAY current control operation
When FDT pin voltage is a voltage under 0.8V, the constant-current control is operated in FAST DECAY mode.
(Sine-wave increasing direction)
CLK
Setting current
Setting current
Coil current
Blanking Time
fchop
Current mode
CHARGE
FAST
CHARGE
FAST
(Sine-wave decreasing direction)
CLK
Setting current
Coil current
Setting current
Blanking Time
fchop
Current mode
CHARGE
FAST
Blanking Time
FAST
CHARGE
FAST
Each of current modes operates with the follow sequence.
The IC enters CHARGE mode at a rising edge of the chopping oscillation.
(A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1s, regardless of the current value
of the coil current (ICOIL) and set current (IREF)).
After the period of the blanking time, The IC operates in CHARGE mode until ICOIL IREF. After that,
the mode switches to the FAST DECAY mode and the coil current is attenuated until the end of a chopping period.
At the constant-current control in FAST DECAY mode, following to the setting current from the coil current takes
short-time for the current fast attenuation, but, the current ripple value may be higher.
MIXED DECAY current control operation
No.A2252-16/20
STK682-010-E
(Sine-wave increasing direction)
CLK
Setting current
Setting current
Coil current
Blanking Time
fchop
Current mode
CHARGE
SLOW
FAST
CHARGE
SLOW
FAST
(Sine-wave decreasing direction)
CLK
Setting current
Coil current
Setting current
Blanking Time
fchop
Current mode
CHARGE
SLOW
FAST
Blanking Time
FAST
CHARGE
SLOW
Each of current modes operates with the follow sequence.
The IC enters CHARGE mode at a rising edge of the chopping oscillation.
(A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1 μs, regardless of the current
value of the coil current (ICOIL) and set current (IREF)).
In a period of Blanking Time, the coil current (ICOIL) and the setting current (IREF) are compared.
If an ICOIL = IREF state exists during the charge period:
The IC operates in CHAGE mode until ICOIL IREF. After that, it switches to SLOW DECAY mode and then
switches to FAST DECAY mode in the last approximately 1 μs of the period.
If no ICOIL = IREF state exists during the charge period:
The IC switches to FAST DECAY mode and the coil current is attenuated with the FAST DECAY operation until the
end of a chopping period.
The above operation is repeated.
Normally, in the sine wave increasing direction the IC operates in SLOW (+FAST) DECAY mode, and in the sine
wave decreasing direction the IC operates in FAST DECAY mode until the current is attenuated and reaches the set
value and the IC operates in SLOW (+FAST) DECAY mode.
No.A2252-17/20
STK682-010-E
Power Dissipation
Power dissipation calculation of STK682-010-E following becomes.
2-phase excitation
Pd=IOH×(Ronu + Rond)2
1-2-phase excitation
Pd=0.71×IOH×(Ronu + Rond)2
Please by substituting from electrical characteristic table value of Rond and Ronu.
Thermal design
[Operating range in which a heat sink is not used]
Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the
quality of the HIC.
The size of heat sink for the HIC varies depending on the magnitude of the average power loss, PdAV, within the HIC.
The value of PdAV increases as the output current increases. To calculate PdAV, refer to “Calculating Internal HIC
Loss for the STK672-640C-E in the specification document.
Calculate the internal HIC loss, PdAV, assuming repeat operation such as shown in Figure 1 below, since conduction
during motor rotation and off time both exist during actual motor operations,
I 1
O
Motor phase current
(sink side)
I 2
O
0A
-I 1
O
T1
T3
T2
T0
Figure 1 Motor Current Timing
T1 : Motor rotation operation time
T2 : Motor hold operation time
T3 : Motor current off time
T2 may be reduced, depending on the application.
T0 : Single repeated motor operating cycle
IO1 and IO2 : Motor current peak values
Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form.
Note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ.
The hybrid IC internal average power dissipation PdAV can be calculated from the following formula.
PdAV= (T1P1+T2P2+T30) TO ---------------------------- (I)
(Here, P1 is the PdAV for IO1 and P2 is the PdAV for IO2)
If the value calculated using Equation (I) is 1.5W or less, and the ambient temperature, Ta, is 60C or less, there is no
need to attach a heat sink. Refer to Figure 2 for operating substrate temperature data when no heat sink is used.
[Operating range in which a heat sink is used]
Although a heat sink is attached to lower Tc if PdAV increases, the resulting size can be found using the value of
c-a in Equation (II) below and the graph depicted in Figure 3.
c-a = (Tc max-Ta) PdAV ---------------------------- (II)
Tc max : Maximum operating substrate temperature =105C
Ta : HIC ambient temperature
Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and
confirm that the substrate temperature, Tc, is 105C or less.
No.A2252-18/20
STK682-010-E
Figure 2 Substrate temperature rise, Tc (no heat
Figure 3 Heat sink area (Board thickness: 2mm) - c-a
sink) - Internal average power dissipation, PdAV
Tc - PdAV
c-a - S
80
100
7
5
70
60
50
40
30
20
3
2
10
7
5
3
2
10
0
1.0
10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2
3
5
7
2
3
5
7
1000
100
Heat sink area, S - cm2
Hybrid IC internal average power dissipation, PdAV - W
ITF02553
ITF02554
Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta
Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink.
The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta.
Power loss of up to 3.1W is allowable at Ta=25C, and of up to 1.75W at Ta=60C.
Allowable power dissipation, PdPK(no heat sink) - Ambient temperature, Ta
PdPK - Ta
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
80
100
120
Ambient temperature,Ta - C
ITF02511
No.A2252-19/20
STK682-010-E
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
15 / Tube
SIP-19
(Pb-Free)
STK682-010-E
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PS No.A2252-20/20
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