SRV05-4MR6T1G [ONSEMI]
Transient Voltage Suppressors ESD Protection Diodes with Low Clamping Voltage; 瞬态电压抑制器ESD保护二极管具有钳位电压低
| 型号： | SRV05-4MR6T1G |
| 厂家： | 
ONSEMI |
| 描述： | Transient Voltage Suppressors ESD Protection Diodes with Low Clamping Voltage |
| 文件： | 总9页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SRV05-4MR6
Transient Voltage
Suppressors
ESD Protection Diodes with Low
Clamping Voltage
http://onsemi.com
The SRV05−4MR6 transient voltage suppressor is designed to
protect high speed data lines from ESD, EFT, and lighting.
LOW CAPACITANCE
TVS ARRAY
Features
• Protects 4 I/O Lines
• Low Working Voltage: 5 V
• Low Clamping Voltage
• Low Capacitance (<5 pF) for High Speed Interfaces
• Transient Protection for High Speed Lines to:
IEC61000−4−2 (ESD) 15 kV (air), 8 kV (contact)
IEC61000−4−4 (EFT) 40 A
300 WATTS PEAK POWER
6 VOLTS
PIN CONFIGURATION
AND SCHEMATIC
I/O 1
6 I/O
IEC61000−4−5 (Lightning) 12 A
V
N
2
5 V
• TSOP−6 is Footprint Compatible with SOT−23 6 Lead,
SC−59 6 Lead and SC−74
P
• UL Flammability Rating of 94 V−0
• This is a Pb−Free Device
I/O 3
4 I/O
6
Typical Applications
• High Speed Communication Line Protection
• USB 1.1 and 2.0 Power and Data Line Protection
• Digital Video Interface (DVI)
1
TSOP−6
CASE 318G
PLASTIC
• Monitors and Flat Panel Displays
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
MARKING DIAGRAM
Rating
Symbol
Value
Unit
Peak Power Dissipation
P
pk
300
W
8 x 20 ms @ T = 25°C (Note 1)
A
63
G
G
Operating Junction Temperature Range
Storage Temperature Range
T
−55 to +125
−55 to +150
260
°C
°C
°C
J
T
stg
63 = Specific Device Code
M = Date Code
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
G
= Pb−Free Package
(Note: Microdot may be in either location)
Human Body Model (HBM)
Machine Model (MM)
IEC 61000−4−2 Air (ESD)
IEC 61000−4−2 Contact (ESD)
ESD
16000
400
15000
8000
V
*Date Code orientation may vary
depending upon manufacturing location.
IEC 61000−4−4 (5/50 ns)
IEC 61000−4−5 (8 x 20 ms)
EFT
40
12
A
A
ORDERING INFORMATION
−
Device
Package
Shipping
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
SRV05−4MR6T1G TSOP−6 3000/Tape & Reel
(Pb−Free)
1. Non−repetitive current pulse per Figure 5 (Pin 5 to Pin 2)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
November, 2009 − Rev. 0
SRV05−4MR6/D
SRV05−4MR6
ELECTRICAL CHARACTERISTICS
A
I
(T = 25°C unless otherwise noted)
I
F
Symbol
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
I
PP
V
C
PP
V
Working Peak Reverse Voltage
RWM
V
C
V
V
BR RWM
V
I
V
F
I
R
Maximum Reverse Leakage Current @ V
R
T
RWM
I
V
Breakdown Voltage @ I
Test Current
BR
T
I
T
F
I
Forward Current
I
PP
V
F
Forward Voltage @ I
F
P
Peak Power Dissipation
Capacitance @ V = 0 and f = 1.0 MHz
pk
Uni−Directional TVS
C
R
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (T =25°C unless otherwise specified)
J
Parameter
Reverse Working Voltage
Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Symbol
Conditions
Min
Typ
Max
Unit
V
V
RWM
(Note 2)
I =1 mA, (Note 3)
5.0
V
BR
6.0
V
T
I
R
V
RWM
= 5 V
5.0
12.5
17.5
5.0
mA
V
V
C
I
PP
I
PP
= 1 A (Note 4)
= 5 A (Note 4)
Clamping Voltage
V
C
V
Junction Capacitance
Junction Capacitance
Clamping Voltage
C
C
V
V
= 0 V, f=1 MHz between I/O Pins and GND
= 0 V, f=1 MHz between I/O Pins
3.0
1.5
pF
pF
V
J
J
R
3.0
R
V
C
Per IEC 61000−4−2 (Note 5)
Figure 1 and 2
2. TVS devices are normally selected according to the working peak reverse voltage (V
or continuous peak operating voltage level.
), which should be equal or greater than the DC
RWM
3. V is measured at pulse test current I .
BR
T
4. Non−repetitive current pulse per Figure 5 (Any I/O Pin to Ground)
5. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Figure 2. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Negative 8 kV Contact per IEC61000−4−2
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2
SRV05−4MR6
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
Test
Voltage
(kV)
First Peak
Current
(A)
100%
90%
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 5. 8 X 20 ms Pulse Waveform
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3
SRV05−4MR6
TYPICAL PERFORMANCE CURVES
(T = 25°C unless otherwise noted)
J
5.0
4.5
4.0
3.5
3.0
30
25
20
15
I/O−Ground
2.5
2.0
1.5
1.0
0.5
0.0
10
5
I/O lines
0
0
1
2
3
4
5
0
2
4
6
8
10
12
V
BR
, REVERSE VOLTAGE (V)
PEAK PULSE CURRENT (A)
Figure 6. Junction Capacitance vs Reverse Voltage
Figure 7. Clamping Voltage vs. Peak Pulse Current
(8 x 20 ms Waveform)
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4
SRV05−4MR6
APPLICATIONS INFORMATION
The new SRV05−4MR6 is a low capacitance TVS diode
Option 2
array designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD events or transient
overvoltage conditions. Because of its low capacitance, it
can be used in high speed I/O data lines. The integrated
design of the SRV05−4MR6 offers surge rated, low
capacitance steering diodes and a TVS diode integrated in a
single package (TSOP−6). If a transient condition occurs,
the steering diodes will drive the transient to the positive rail
of the power supply or to ground. The TVS device protects
the power line against overvoltage conditions to avoid
damage to the power supply and any downstream
components.
Protection of four data lines with bias and power supply
isolation resistor.
I/O 1
I/O 2
V
CC
1
2
3
6
5
4
10 k
I/O 3
I/O 4
SRV05−4MR6 Configuration Options
The SRV05−4MR6 can be isolated from the power supply
The SRV05−4MR6 is able to protect up to four data lines
against transient overvoltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
by connecting a series resistor between pin 5 and V . A
CC
10 kW resistor is recommended for this application. This
will maintain a bias on the internal TVS and steering diodes,
reducing their capacitance.
protected line exceeds the reference voltage (Vf or V
+
CC
Vf). The diodes will force the transient current to bypass the
sensitive circuit.
Option 3
Protection of four data lines using the internal TVS diode
as reference.
Data lines are connected at pins 1, 3, 4 and 6. The negative
reference is connected at pin 2. These pins must be
connected directly to ground by using a ground plane to
minimize the PCB’s ground inductance. It is very important
to reduce the PCB trace lengths as much as possible to
minimize parasitic inductances.
I/O 1
I/O 2
1
2
3
6
5
4
Option 1
Protection of four data lines and the power supply using
NC
V
CC
as reference.
I/O 1
I/O 2
I/O 3
I/O 4
1
2
3
6
5
4
In applications lacking a positive supply reference or
those cases in which a fully isolated power supply is
required, the internal TVS can be used as the reference. For
these applications, pin 5 is not connected. In this
configuration, the steering diodes will conduct whenever the
voltage on the protected line exceeds the working voltage of
V
CC
I/O 3
I/O 4
the TVS plus one diode drop (Vc = Vf + V
).
TVS
ESD Protection of Power Supply Lines
For this configuration, connect pin 5 directly to the
When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes
reduces their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:
positive supply rail (V ), the data lines are referenced to
CC
the supply voltage. The internal TVS diode prevents
overvoltage on the supply rail. Biasing of the steering diodes
reduces their capacitance.
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5
SRV05−4MR6
Even with good board layout, some disadvantages are still
Power
Supply
present when discrete diodes are used to suppress ESD
events across datalines and the supply rail. Discrete diodes
with good transient power capability will have larger die and
therefore higher capacitance. This capacitance becomes
problematic as transmission frequencies increase. Reducing
capacitance generally requires reducing die size. These
small die will have higher forward voltage characteristics at
typical ESD transient current levels. This voltage combined
with the smaller die can result in device failure.
I
ESDpos
V
CC
I
ESDpos
D1
D2
Protected
Device
I
Data Line
ESDneg
VF + V
CC
I
ESDneg
The ON Semiconductor SRV05−4MR6 was developed to
overcome the disadvantages encountered when using
discrete diodes for ESD protection. This device integrates a
TVS diode within a network of steering diodes.
−VF
Looking at the figure above, it can be seen that when a
positive ESD condition occurs, diode D1 will be forward
biased while diode D2 will be forward biased when a
negative ESD condition occurs. For slower transient
conditions, this system may be approximated as follows:
D1
D2
D3
D4
D5
D6
D7
D8
For positive pulse conditions:
Vc = V + Vf
CC
D1
For negative pulse conditions:
Vc = −Vf
D2
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect
of parasitic inductance must be considered. A pictorial
representation of this is shown below.
0
Power
Supply
Figure 8. SRV05−4MR6 Equivalent Circuit
I
ESDpos
During an ESD condition, the ESD current will be driven
to ground through the TVS diode as shown below.
V
CC
I
ESDpos
D1
D2
I
Protected
Device
ESDneg
Power
Supply
Data Line
V
I
= V + Vf + (L diESD/dt)
C
CC
V
CC
ESDneg
I
ESDpos
D1
D2
Protected
Device
V
C
= −Vf − (L diESD/dt)
Data Line
An approximation of the clamping voltage for these fast
transients would be:
For positive pulse conditions:
Vc = V + Vf + (L di
/dt)
CC
ESD
For negative pulse conditions:
Vc = −Vf – (L di /dt)
As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
ESD
The resulting clamping voltage on the protected IC will
be:
Vc = VF + V
The clamping voltage of the TVS diode is provided in
Figure 7 and depends on the magnitude of the ESD current.
The steering diodes are fast switching devices with unique
forward voltage and low capacitance characteristics.
.
TVS
L d
/dt factor. A relatively small trace inductance can
iESD
result in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached to
that rail. This highlights the importance of good board
layout. Taking care to minimize the effects of parasitic
inductance will provide significant benefits in transient
immunity.
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6
SRV05−4MR6
TYPICAL APPLICATIONS
UPSTREAM
USB PORT
V
BUS
V
BUS
V
BUS
D+
D−
V
D+
BUS
R
R
T
DOWNSTREAM
USB PORT
T
D−
V
V
BUS
BUS
SRV05−4MR6
USB
Controller
GND
GND
C
C
T
T
V
BUS
V
BUS
NUP2201DT1
R
R
T
DOWNSTREAM
USB PORT
D+
T
D−
GND
C
C
T
T
Figure 9. ESD Protection for USB Port
RJ45
Connector
TX+
TX+
TX−
TX−
Coupling
PHY
Ethernet
(10/100)
Transformers
RX+
RX+
RX−
RX−
SRV05−4MR6
V
CC
GND
N/C
N/C
Figure 10. Protection for Ethernet 10/100 (Differential mode)
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7
SRV05−4MR6
R1
RTIP
R3
R2
RRING
T1
V
CC
T1/E1
TRANCEIVER
SRV05−4MR6
R4
R5
TTIP
TRING
T2
Figure 11. TI/E1 Interface Protection
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8
SRV05−4MR6
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE T
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
6
5
2
4
E
A
H
E
1
3
b
MILLIMETERS
INCHES
DIM
A
A1
b
c
D
E
e
L
MIN
0.90
0.01
0.25
0.10
2.90
1.30
0.85
0.20
2.50
0°
NOM
1.00
0.06
0.38
0.18
3.00
1.50
0.95
0.40
2.75
−
MAX
MIN
0.035
0.001
0.010
0.004
0.114
0.051
0.034
0.008
0.099
0°
NOM
0.039
0.002
0.014
0.007
0.118
0.059
0.037
0.016
0.108
−
MAX
0.043
0.004
0.020
0.010
0.122
0.067
0.041
0.024
0.118
10°
e
1.10
0.10
0.50
0.26
3.10
1.70
1.05
0.60
3.00
10°
q
c
0.05 (0.002)
L
A1
H
E
q
SOLDERING FOOTPRINT*
2.4
0.094
0.95
0.037
1.9
0.075
0.95
0.037
0.7
0.028
1.0
0.039
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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SRV05−4MR6/D
相关型号：
SRV0505
Trans Voltage Suppressor Diode, 50W, 5V V(RWM), Unidirectional, 5 Element, Silicon, PLASTIC PACKAGE-6
MCC
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