SN74LS374DW [ONSEMI]
LOW POWER SCHOTTKY; 小功率肖特基
| 型号： | SN74LS374DW |
| 厂家： | 
ONSEMI |
| 描述： | LOW POWER SCHOTTKY |
| 文件： | 总8页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The SN74LS373 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appear transparent
to the data (data changes asynchronously) when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop
featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops. The SN74LS374 is
manufactured using advanced Low Power Schottky technology and is
compatible with all ON Semiconductor TTL families.
LOW
POWER
SCHOTTKY
20
• Eight Latches in a Single Package
• 3-State Outputs for Bus Interfacing
• Hysteresis on Latch Enable
• Edge-Triggered D-Type Inputs
1
PLASTIC
N SUFFIX
CASE 738
• Buffered Positive Edge-Triggered Clock
• Hysteresis on Clock Input to Improve Noise Margin
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
20
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
1
V
CC
SOIC
DW SUFFIX
CASE 751D
T
A
Operating Ambient
Temperature Range
°C
I
Output Current – High
Output Current – Low
–2.6
24
mA
mA
OH
I
OL
ORDERING INFORMATION
Device
Package
16 Pin DIP
16 Pin
Shipping
SN74LS373N
SN74LS373DW
SN74LS374N
SN74LS374DW
1440 Units/Box
2500/Tape & Reel
1440 Units/Box
16 Pin DIP
16 Pin
2500/Tape & Reel
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
December, 1999 – Rev. 6
SN74LS373/D
SN74LS373 SN74LS374
CONNECTION DIAGRAM DIP (TOP VIEW)
SN74LS374
SN74LS373
V
O
D
D
O
O
D
D
O
4
LE
11
V
O
D
D
O
O
D
D
O
4
CP
11
CC
7
7
6
6
5
5
4
CC
7
7
6
6
5
5
4
20 19 18 17 16 15 14 13 12
20 19 18 17 16 15 14 13 12
1
2
3
4
5
6
8
9
10
7
1
2
3
4
5
6
8
9
10
7
NOTE:
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
(Note a)
LOW
LOADING
HIGH
PIN NAMES
D – D
LE
CP
OE
Data Inputs
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0
7
Latch Enable (Active HIGH) Input
Clock (Active HIGH Going Edge) Input
Output Enable (Active LOW) Input
Outputs
O – O
0
7
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
TRUTH TABLE
LS373
LS374
LE
D
LE
H
H
L
OE
L
O
D
OE
L
O
n
n
n
n
H
H
H
H
L
X
X
L
L
L
L
L
L
Q
X
X
H
Z*
0
X
H
Z*
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
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2
SN74LS373 SN74LS374
LOGIC DIAGRAMS
SN74LS373
3
4
7
8
13
14
17
18
V
CC
= PIN 20
D
D
D
D
D
D
D
D
7
GND = PIN 10
= PIN NUMBERS
0
1
2
3
4
5
6
D
D
D
D
D
D
D
D
Q
G
Q
G
Q
G
Q
G
Q
G
Q
G
Q
G
Q
G
LATCH
ENABLE
LE
11
OE
1
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2
5
6
9
12
15
16
19
SN74LS374
3
4
7
8
13
14
17
18
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
11
CP
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
OE
1
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2
5
6
9
12
15
16
19
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
V
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.1
–1.5
V
V
= MIN, I = –18 mA
IN
IK
CC
= MIN, I = MAX, V = V
IH
CC
OH
IN
2.4
OH
or V per Truth Table
IL
V
V
= V MIN,
CC
0.25
0.35
0.4
0.5
V
V
I
I
= 12 mA
= 24 mA
CC
OL
= V or V
IH
V
OL
Output LOW Voltage
IN
IL
per Truth Table
OL
I
I
Output Off Current HIGH
Output Off Current LOW
20
–20
20
µA
µA
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V
= MAX, V
= 2.7 V
= 0.4 V
OZH
OUT
OUT
OZL
µA
= MAX, V = 2.7 V
IN
I
IH
Input HIGH Current
0.1
mA
mA
mA
mA
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
–0.4
–130
40
= MAX, V = 0.4 V
IL
IN
Short Circuit Current (Note 1)
Power Supply Current
–30
= MAX
= MAX
OS
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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3
SN74LS373 SN74LS374
AC CHARACTERISTICS (T = 25°C, V = 5.0 V)
A
CC
Limits
LS373
LS374
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Typ
Max
Min
Max
f
Maximum Clock Frequency
35
50
MHz
MAX
t
t
Propagation Delay,
Data to Output
12
12
18
18
PLH
PHL
ns
ns
ns
ns
C = 45 pF,
R = 667 Ω
L
L
t
t
Clock or Enable
to Output
20
18
30
30
15
19
28
28
PLH
PHL
t
t
15
25
28
36
20
21
28
28
PZH
PZL
Output Enable Time
Output Disable Time
t
t
12
15
20
25
12
15
20
25
PHZ
PLZ
C = 5.0 pF
L
AC SETUP REQUIREMENTS (T = 25°C, V = 5.0 V)
A
CC
Limits
LS373
LS374
Symbol
Parameter
Unit
Min
Max
Min
Max
t
t
t
Clock Pulse Width
Setup Time
15
5.0
20
15
20
0
ns
ns
ns
W
s
Hold Time
h
DEFINITION OF TERMS
SETUP TIME (t ) — is defined as the minimum time
HOLD TIME (t ) — is defined as the minimum time
s
h
required for the correct logic level to be present at the logic
input prior to LE transition from HIGH-to-LOW in order to
be recognized and transferred to the outputs.
following the LE transition from HIGH-to-LOW that the
logic level must be maintained at the input in order to ensure
continued recognition.
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4
SN74LS373 SN74LS374
SN74LS373
AC WAVEFORMS
t
W
t
W
1.3 V
LE
t
s
t
h
D
n
t
t
PHL
PLH
OUTPUT
Figure 1.
OE
V
OE
1.3 V
1.3 V
1.3 V
1.3 V
t
t
t
t
PHZ
PZL
PLZ
PZH
V
OH
1.3 V
OUT
1.3 V
1.3 V
0.5 V
V
OUT
1.3 V
V
OL
0.5 V
Figure 2.
Figure 3.
AC LOAD CIRCUIT
V
CC
SWITCH POSITIONS
R
L
SYMBOL
SW1
Open
SW2
Closed
Open
t
PZH
SW1
t
t
Closed
Closed
Closed
PZL
PLZ
PHZ
Closed
Closed
TO OUTPUT
UNDER TEST
t
5.0 kΩ
C *
L
SW2
* Includes Jig and Probe Capacitance.
Figure 4.
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5
SN74LS373 SN74LS374
SN74LS374
AC WAVEFORMS
t H
W
t L
W
OE
1.3 V
1.3 V
CP
1.3 V
1.3 V
1.3 V
t
h
t
t
PZL
PLZ
t
s
V
OUT
≈ 1.3 V
1.3 V
D
n
1.3 V
V
OL
t
t
PHL
PLH
0.5 V
Figure 6.
OUTPUT
1.3 V
1.3 V
Figure 5.
OE
1.3 V
1.3 V
t
t
PHZ
PZH
≥ V
OH
≈ 1.3 V
0.5 V
V
OUT
1.3 V
Figure 7.
AC LOAD CIRCUIT
V
CC
SWITCH POSITIONS
SYMBOL
SW1
Open
SW2
Closed
Open
R
L
t
PZH
t
t
Closed
Closed
Closed
PZL
PLZ
PHZ
SW1
Closed
Closed
t
TO OUTPUT
UNDER TEST
5.0 kΩ
C *
L
SW2
* Includes Jig and Probe Capacitance.
Figure 8.
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6
SN74LS373 SN74LS374
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.260
0.180
0.022
6.10
3.81
0.39
–T–
SEATING
PLANE
K
1.27 BSC
M
0.070
1.27
1.77
N
E
G
0.100 BSC
2.54 BSC
J
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0
0.51
0.38
3.55
G
F
K
L
M
N
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0
15
0.040
15
1.01
0.020
M
M
0.25 (0.010)
T A
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
20
11
10
E
1
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
B
20X B
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
12.65 12.95
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
T
0.25
A
B
A
0.25
0.50
0
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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7
SN74LS373 SN74LS374
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SN74LS373/D
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