SN74LS253D [ONSEMI]
LOW POWER SCHOTTKY; 小功率肖特基
| 型号： | SN74LS253D |
| 厂家： | 
ONSEMI |
| 描述： | LOW POWER SCHOTTKY |
| 文件： | 总8页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The LSTTL/MSI SN74LS253 is a Dual 4-Input Multiplexer with
3-state outputs. It can select two bits of data from four sources using
common select inputs. The outputs may be individually switched to a
high impedance state with a HIGH on the respective Output Enable
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(E ) inputs, allowing the outputs to interface directly with bus oriented
0
systems. It is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.
LOW
POWER
SCHOTTKY
• Schottky Process for High Speed
• Multifunction Capability
• Non-Inverting 3-State Outputs
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
16
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
1
V
CC
PLASTIC
N SUFFIX
CASE 648
T
A
Operating Ambient
Temperature Range
°C
I
Output Current – High
Output Current – Low
–2.6
24
mA
mA
OH
I
OL
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
16 Pin DIP
16 Pin
Shipping
SN74LS253N
SN74LS253D
2000 Units/Box
2500/Tape & Reel
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
December, 1999 – Rev. 6
SN74LS253/D
SN74LS253
CONNECTION DIAGRAM DIP (TOP VIEW)
V
CC
E
0b
S
0
I
3b
I
2b
I
1b
I
0b
Z
b
16
15
14
13
12
11
10
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
2
3
4
5
6
8
7
E
0a
S
1
I
3a
I
2a
I
1a
I
0a
Z
a
GND
LOADING (Note a)
HIGH
LOW
PIN NAMES
S , S
Common Select Inputs
0.5 U.L.
0.25 U.L.
0
1
Multiplexer A
E
Output Enable (Active LOW) Input
Multiplexer Inputs
Multiplexer Output
0.5 U.L.
0.5 U.L.
65 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0a
– I
I
0a 3a
Z
a
Multiplexer B
E
Output Enable (Active LOW) Input
Multiplexer Inputs
Multiplexer Output
0.5 U.L.
0.5 U.L.
65 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0b
– I
I
0b 3b
Z
b
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
LOGIC SYMBOL
1
6
5
4
3
10 11 12 13 15
E
I
I
I
I
I
I
I
I
E
0a 0a 1a 2a 3a 0b 1b 2b 3b 0b
14
2
S
S
0
1
Z
Z
b
a
7
9
V
CC
= PIN 16
GND = PIN 8
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2
SN74LS253
LOGIC DIAGRAM
E
0b
I
3b
I
2b
I
1b
I
0b
S
0
S
1
I
3a
I
2a
I
1a
I
0a
E
0a
15
13
12
11
10
14
2
3
4
5
6
1
V
= PIN 16
CC
9
7
Z
b
GND = PIN 8
= PIN NUMBERS
Z
a
FUNCTIONAL DESCRIPTION
The LS253 contains two identical 4-Input Multiplexers
with 3-state outputs. They select two bits from four sources
If the outputs of 3-state devices are tied together, all but
one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
selected by common select inputs (S , S ). The 4-input
0
1
multiplexers have individual Output Enable (E , E )
0a
0b
inputs which when HIGH, forces the outputs to a high
impedance (high Z) state.
The LS253 is the logic implementation of a 2-pole,
4-position switch, where the position of the switch is
determined by the logic levels supplied to the two select
inputs. The logic equations for the outputs are shown below:
Za = E0a (I0a S1 S0 + I1a S1 S0 I2a S1 S0 + I3a S1 S0)
Zb = E0b (I0b S1 S0 + I1b S1 S0 I2b S1 S0 + I3b S1 S0)
TRUTH TABLE
SELECT
OUTPUT
ENABLE
DATA INPUTS
INPUTS
OUTPUT
Z
S
0
S
1
I
0
I
1
I
2
I
3
E
0
X
L
L
H
H
L
L
H
H
X
L
L
L
L
H
H
H
H
X
L
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
(Z)
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
H
X
X
X
X
X
X
H
H
H = HIGH Level
L = LOW Level
X = Irrelevant
(Z) = High Impedance (off)
Address inputs S and S are common to both sections.
0
1
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3
SN74LS253
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
V
2.0
V
IH
0.8
Guaranteed Input LOW Voltage for
All Inputs
Input LOW Voltage
V
IL
V
V
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.1
–1.5
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
2.4
= MIN, I = MAX, V = V
OH IN IH
OH
CC
or V per Truth Table
IL
V
V
= V MIN,
CC
0.25
0.35
0.4
0.5
V
V
I
I
= 12 mA
= 24 mA
CC
OL
= V or V
IH
V
OL
Output LOW Voltage
IN
IL
per Truth Table
OL
I
I
Output Off Current HIGH
Output Off Current LOW
20
–20
20
µA
µA
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V
= MAX, V
= 2.7 V
= 0.4 V
OZH
OUT
OUT
OZL
µA
= MAX, V = 2.7 V
IN
I
IH
Input HIGH Current
0.1
mA
mA
mA
mA
mA
= MAX, V = 7.0 V
IN
I
I
Input LOW Current
–0.4
–130
12
= MAX, V = 0.4 V
IL
IN
Short Circuit Current (Note 1)
–30
= MAX
OS
= MAX, V = 0 V
E
I
Power Supply Current
CC
14
= MAX, V = 4.5 V
E
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V = 5.0 V) See SN74LS251 for Waveforms
A
CC
Limits
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Max
t
t
Propagation Delay,
Data to Output
17
13
25
20
PLH
ns
Figure 1
Figure 1
PHL
t
t
Propagation Delay,
Select to Output
30
21
45
32
C = 45 pF,
PLH
PHL
L
ns
ns
ns
R = 667 Ω
L
t
t
15
15
28
23
PZH
PZL
Output Enable Time
Output Disable Time
Figures 4, 5
Figures 3, 5
t
t
27
18
41
27
C = 5.0 pF,
L
R = 667 Ω
L
PHZ
PLZ
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4
SN74LS253
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
–T–
G
H
J
K
L
M
S
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
PLANE
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
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5
SN74LS253
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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6
SN74LS253
Notes
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7
SN74LS253
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SN74LS253/D
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