RFD16N05SM9A [ONSEMI]

N 沟道,功率 MOSFET,50V,16A,47mΩ;
RFD16N05SM9A
型号: RFD16N05SM9A
厂家: ONSEMI    ONSEMI
描述:

N 沟道,功率 MOSFET,50V,16A,47mΩ

PC 开关 晶体管
文件: 总10页 (文件大小:758K)
中文:  中文翻译
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RFD16N05SM  
Data Sheet  
September 2013  
N-Channel Power MOSFET  
Features  
50V, 16A, 47 mΩ  
• 16A, 50V  
• r = 0.047Ω  
The RFD16N05 and RFD16N05SM N-channel power  
MOSFETs are manufactured using the MegaFET process.  
This process, which uses feature sizes approaching those of  
LSI integrated circuits, gives optimum utilization of silicon,  
resulting in outstanding performance. They were designed  
for use in applications such as switching regulators,  
DS(ON)  
®
Temperature Compensating PSPICE Model  
• Peak Current vs Pulse Width Curve  
• UIS Rating Curve  
o
switching converters, motor drivers, and relay drivers. These  
transistors can be operated directly from integrated circuits.  
• 175 C Operating Temperature  
• Related Literature  
Formerly developmental type TA09771.  
- TB334 “Guidelines for Soldering Surface Mount  
Components to PC Boards”  
Ordering Information  
Symbol  
PART NUMBER  
PACKAGE  
BRAND  
D16N05  
D
RFD16N05SM9A  
TO-252AA  
G
S
Packaging  
JEDEC TO-252AA  
DRAIN (FLANGE)  
GATE  
SOURCE  
©2003 Fairchild Semiconductor Corporation  
RFD16N05SM Rev. C0  
RFD16N05SM  
o
Absolute Maximum Ratings  
T = 25 C, Unless Otherwise Specified  
C
RFD16N05SM9A  
UNITS  
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
50  
V
V
A
DSS  
DGR  
Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
50  
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
16  
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
Refer to Peak Current Curve  
DM  
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V  
±20  
Refer to Figure 5  
72  
V
GS  
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E  
AS  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P  
W
D
o
o
Derate above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
0.48  
W/ C  
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T  
Maximum Temperature for Soldering  
T
-55 to 175  
C
J, STG  
o
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T  
300  
260  
C
L
o
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T  
C
pkg  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
o
o
1. T = 25 C to 150 C.  
J
o
Electrical Specifications  
T = 25 C, Unless Otherwise Specified  
C
PARAMETER  
SYMBOL  
TEST CONDITIONS  
= 250µA, V = 0V (Figure 11)  
GS  
MIN  
TYP  
MAX  
UNITS  
V
Drain to Source Breakdown Voltage  
Gate Threshold Voltage  
BV  
I
50  
2
-
-
-
-
-
-
4
DSS  
D
V
V
V
V
= V , I = 250µA  
V
GS(TH)  
GS  
DS  
DS  
DS  
D
Zero Gate Voltage Drain Current  
I
= Rated BV  
, V  
DSS GS  
= 0V  
1
µA  
DSS  
= 0.8 x Rated BV  
= 150 C  
, V  
= 0V,  
-
25  
µA  
DSS GS  
o
T
C
Gate to Source Leakage Current  
I
V
= ±20V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±100  
nA  
GSS  
GS  
= 16A, V = 10V (Figure 9)  
GS  
Drain to Source On Resistance (Note 2)  
Turn-On Time  
r
I
0.047  
DS(ON)  
D
t
V
V
= 25V, I = 8A, R = 3.125,  
= 10V, R  
-
65  
ns  
ns  
ns  
ns  
ns  
ns  
nC  
nC  
nC  
pF  
pF  
pF  
(ON)  
DD  
D
L
= 25Ω  
GS  
GS  
Turn-On Delay Time  
t
14  
30  
55  
30  
-
-
d(ON)  
(Figure 13)  
Rise Time  
t
-
r
Turn-Off Delay Time  
t
-
-
d(OFF)  
Fall Time  
t
f
Turn-Off Time  
t
125  
80  
45  
2.2  
-
(OFF)  
Total Gate Charge  
Q
V
V
V
V
= 0V to 20V  
= 0V to 10V  
= 0V to 2V  
V = 40V, ID 16A,  
DD  
-
g(TOT)  
GS  
GS  
GS  
DS  
R
= 2.5Ω  
L
Gate Charge at 10V  
Q
-
g(10)  
I
= 0.8mA  
g(REF)  
Threshold Gate Charge  
Input Capacitance  
Q
(Figure 13)  
-
(TH)  
C
= 25V, V  
GS  
= 0V, f = 1MHz  
900  
325  
100  
-
ISS  
OSS  
RSS  
(Figure 12)  
Output Capacitance  
C
-
Reverse Transfer Capacitance  
Thermal Resistance Junction to Case  
Thermal Resistance Junction to Ambient  
C
-
o
R
2.083  
100  
C/W  
θJC  
θJA  
o
R
TO-251 and TO-252  
-
C/W  
Source to Drain Diode Specifications  
PARAMETER  
Source to Drain Diode Voltage  
Diode Reverse Recovery Time  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
1.5  
UNITS  
V
I
I
= 16A  
-
-
-
-
V
SD  
SD  
t
= 16A, dI /dt = 100A/µs  
SD  
125  
ns  
rr  
SD  
NOTES:  
2. Pulse test: pulse width 250µs, duty cycle 2%.  
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current  
Capability Curve (Figure 5).  
©2003 Fairchild Semiconductor Corporation  
RFD16N05SM Rev. C0  
RFD16N05SM  
Typical Performance Curves Unless Otherwise Specified  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
20  
16  
12  
8
4
0
0
25  
50  
75  
100  
125  
o
150  
175  
25  
50  
75  
100  
125  
150  
175  
o
T
, CASE TEMPERATURE ( C)  
T , CASE TEMPERATURE ( C)  
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE  
TENPERATURE  
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs  
CASE TEMPERATURE  
2
1
0.5  
0.2  
P
DM  
0.1  
0.1  
0.05  
t
1
0.02  
0.01  
t
2
NOTES:  
DUTY FACTOR: D = t /t  
SINGLE PULSE  
1
2
PEAK T = P  
x Z  
x R  
+ T  
JA A  
J
DM  
JA  
θ
θ
0.01  
10  
-5  
-4  
10  
-3  
10  
-2  
10  
-1  
0
1
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE  
SINGLE PULSE  
FOR TEMPERATURES  
ABOVE 25 C DERATE PEAK  
CURRENT AS FOLLOWS:  
T
= MAX RATED  
J
o
100  
10  
1
o
V
= 20V  
T
= 25 C  
200  
100  
GS  
C
175 - T  
V
= 10V  
C
GS  
I = I  
25  
150  
100µs  
o
T
= 25 C  
C
1ms  
OPERATION IN THIS  
AREA MAY BE  
LIMITED BY r  
DS(ON)  
10ms  
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
100ms  
DC  
V
= 50V  
DSS(MAX)  
10  
, DRAIN TO SOURCE VOLTAGE (V)  
1
100  
10  
10  
-5  
-4  
-3  
-2  
-1  
0
1
10  
10  
10  
10  
10  
10  
V
DS  
t, PULSE WIDTH (s)  
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA  
FIGURE 5. PEAK CURRENT CAPABILITY  
©2003 Fairchild Semiconductor Corporation  
RFD16N05SM Rev. C0  
RFD16N05SM  
Typical Performance Curves Unless Otherwise Specified (Continued)  
50  
40  
30  
20  
10  
0
100  
10  
1
V
= 20V  
V
= 10V  
GS  
V
= 8V  
GS  
GS  
V
= 7V  
GS  
o
STARTING T = 25 C  
J
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
o
T
= 25 C  
C
V
= 6V  
= 5V  
GS  
o
STARTING T = 150 C  
J
If R = 0  
= (L)(I )/(1.3*RATED BV  
V
GS  
t
- V  
)
DD  
AV  
If R 0  
AS  
DSS  
V
= 4.5V  
GS  
t
= (L/R)ln[(I *R)/(1.3*RATED BV  
-V ) +1]  
AV  
AS  
DSS DD  
1
V , DRAIN TO SOURCE VOLTAGE (V)  
DS  
0
2
3
4
0.01  
0.1  
1
10  
t
, TIME IN AVALANCHE (ms)  
AV  
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.  
FIGURE 7. SATURATION CHARACTERISTICS  
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING  
2.5  
2.0  
50  
PULSE DURATION = 80µs  
V
= 15V  
DD  
o
o
175 C  
-55 C  
DUTY CYCLE = 0.5% MAX  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
V
= 10V, I = 16A  
GS  
D
40  
30  
20  
o
25 C  
1.5  
1.0  
0.5  
0
10  
0
-80  
-40  
0
40  
80  
120  
160  
200  
0
2
V
4
6
8
10  
o
, GATE TO SOURCE VOLTAGE (V)  
T , JUNCTION TEMPERATURE ( C)  
GS  
J
FIGURE 8. TRANSFER CHARACTERISTICS  
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON  
RESISTANCE vs JUNCTION TEMPERATURE  
2.0  
1.5  
2.0  
1.5  
V
= V , I = 250µA  
DS  
I
= 250µA  
GS  
D
D
1.0  
1.0  
0.5  
0
0.5  
0
-80  
-40  
0
40  
80  
120  
160  
200  
-80  
-40  
0
40  
80  
120  
200  
160  
o
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs  
JUNCTION TEMPERATURE  
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN  
VOLTAGE vs JUNCTION TEMPERATURE  
©2003 Fairchild Semiconductor Corporation  
RFD16N05SM Rev. C0  
RFD16N05SM  
Typical Performance Curves Unless Otherwise Specified (Continued)  
10  
7.5  
5
50  
1600  
V
= 0V, f = 1MHz  
GS  
V
= BV  
DSS  
V
= BV  
DSS  
DD  
C
C
C
= C  
+ C  
DD  
ISS  
GS  
= C  
GD  
RSS  
OSS  
GD  
37.5  
25  
1200  
800  
400  
0
C
+ C  
DS  
GS  
C
ISS  
0.75 BV  
0.50 BV  
0.25 BV  
DSS  
DSS  
DSS  
C
C
OSS  
RSS  
2.5  
0
12.5  
0
R
= 3.125Ω  
G(REF)  
L
I
= 0.8mA  
V
= 10V  
GS  
I
I
G(REF)  
G(REF)  
---------------------  
t, TIME (ms)  
0
5
10  
15  
20  
25  
20------------------------  
80  
I
I
G(ACT)  
G(ACT)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.  
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR  
CONSTANT GATE CURRENT  
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE  
Test Circuits and Waveforms  
V
DS  
BV  
DSS  
L
t
P
V
DS  
I
VARY t TO OBTAIN  
P
AS  
+
-
V
DD  
R
REQUIRED PEAK I  
G
AS  
V
DD  
V
GS  
DUT  
t
P
I
AS  
0V  
0
0.01Ω  
t
AV  
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT  
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS  
t
t
ON  
OFF  
t
d(OFF)  
t
d(ON)  
V
DS  
t
t
f
r
V
DS  
90%  
90%  
R
L
V
GS  
+
10%  
10%  
0
0
V
DD  
-
DUT  
90%  
50%  
R
GS  
V
GS  
50%  
PULSE WIDTH  
10%  
V
GS  
FIGURE 16. SWITCHING TIME TEST CIRCUIT  
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS  
©2003 Fairchild Semiconductor Corporation  
RFD16N05SM Rev. C0  
RFD16N05SM  
Test Circuits and Waveforms (Continued)  
V
DS  
V
Q
DD  
R
g(TOT)  
L
V
DS  
V
= 20V  
GS  
V
Q
GS  
g(10)  
+
-
V
DD  
V
= 10V  
V
GS  
GS  
DUT  
V
= 2V  
GS  
I
0
G(REF)  
Q
g(TH)  
I
G(REF)  
0
FIGURE 18. GATE CHARGE TEST CIRCUIT  
FIGURE 19. GATE CHARGE WAVEFORM  
©2003 Fairchild Semiconductor Corporation  
RFD16N05SM Rev. C0  
RFD16N05SM  
PSPICE Electrical Model  
.SUBCKT RFD16N05 2 1 3 ;  
rev 10/31/94  
CA 12 8 1.788e-10  
CB 15 14 1.875e-10  
CIN 6 8 8.33e-10  
DPLCAP  
5
5
DRAIN  
2
10  
DBODY 7 5 DBDMOD  
LDRAIN  
DBREAK 5 11 DBKMOD  
DPLCAP 10 5 DPLCAPMOD  
RSCL1  
51  
+
DBREAK  
RSCL2  
EBREAK 11 7 17 18 64.89  
EDS 14 8 5 8 1  
ESCL  
51  
EGS 13 8 6 8 1  
ESG 6 10 6 8 1  
EVTO 20 6 18 8 1  
50  
-
+
-
DBODY  
6
8
11  
RDRAIN  
ESG  
17  
18  
16  
EBREAK  
+
VTO  
+
IT 8 17 1  
MOS2  
EVTO  
GATE  
1
21  
+
-
6
9
20  
18  
8
LDRAIN 2 5 1e-9  
LGATE 1 9 4.56e-9  
LSOURCE 3 7 4.13e-9  
MOS1  
8
LGATE RGATE  
RIN  
CIN  
LSOURCE  
RSOURCE  
7
MOS1 16 6 8 8 MOSMOD M = 0.99  
MOS2 16 21 8 8 MOSMOD M = 0.01  
3
SOURCE  
S1A  
S2A  
RBREAK 17 18 RBKMOD 1  
RDRAIN 50 16 RDSMOD 0.4e-3  
RGATE 9 20 3.0  
12  
RBREAK  
15  
13  
8
14  
13  
17  
18  
S1B  
CA  
S2B  
13  
RIN 6 8 1e9  
RSCL1 5 51 RSCLMOD 1e-6  
RSCL2 5 50 1e3  
RSOURCE 8 7 RDSMOD 21.5e-3  
RVTO 18 19 RVTOMOD 1  
RVTO  
19  
CB  
+
IT  
14  
+
-
VBAT  
5
8
6
8
EGS  
EDS  
+
-
S1A 6 12 13 8 S1AMOD  
S1B 13 12 13 8 S1BMOD  
S2A 6 15 14 13 S2AMOD  
S2B 13 15 14 13 S2BMOD  
VBAT 8 19 DC 1  
VTO 21 6 0.82  
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/94,7))}  
.MODEL DBDMOD D (IS = 2.5e-13 RS = 7.1e-3 TRS1 = 3.04e-3 TRS2 = -10e-6 CJO = 1.12e-9 TT = 5.6e-8)  
.MODEL DBKMOD D (RS = 2.51e-1 TRS1 = -6.57e-4 TRS2 = 1.66e-6)  
.MODEL DPLCAPMOD D (CJO = 6.1e-10 IS = 1e-30 N = 10)  
.MODEL MOSMOD NMOS (VTO = 3.96 KP = 16.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)  
.MODEL RBKMOD RES (TC1 = 1.07e-3 TC2 = -7.19e-7)  
.MODEL RDSMOD RES (TC1 = 5.45e-3 TC2 = 1.66e-5)  
.MODEL RSCLMOD RES (TC1 = 1.25e-3 TC2 = 17e-6)  
.MODEL RVTOMOD RES (TC1 = -5.15e-3 TC2 = -4.83e-6)  
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.25 VOFF= -3.25)  
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.25 VOFF= -5.25)  
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.56 VOFF= 5.56)  
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.56 VOFF= 0.56)  
.ENDS  
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global  
Temperature Options; written by William J. Hepp and C. Frank Wheatley.  
©2003 Fairchild Semiconductor Corporation  
RFD16N05SM Rev. C0  
RFD16N05SM  
TRADEMARKS  
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not  
intended to be an exhaustive list of all such trademarks.  
AccuPower™  
AX-CAP *  
BitSiC™  
Build it Now™  
CorePLUS™  
CorePOWER™  
CROSSVOLT™  
CTL™  
F-PFS™  
FRFET  
Sync-Lock™  
®*  
®
®
®
tm  
®
Global Power ResourceSM  
GreenBridge™  
Green FPS™  
PowerTrench  
PowerXS™  
Programmable Active Droop™  
QFET  
QS™  
Quiet Series™  
RapidConfigure™  
®
TinyBoost  
TinyBuck  
®
®
Green FPS™ e-Series™  
Gmax™  
GTO™  
TinyCalc™  
®
TinyLogic  
TINYOPTO™  
TinyPower™  
TinyPWM™  
TinyWire™  
TranSiC™  
TriFault Detect™  
Current Transfer Logic™  
IntelliMAX™  
®
DEUXPEED  
ISOPLANAR™  
Marking Small Speakers Sound Louder  
and Better™  
MegaBuck™  
MICROCOUPLER™  
MicroFET™  
MicroPak™  
MicroPak2™  
MillerDrive™  
MotionMax™  
Dual Cool™  
®
EcoSPARK  
Saving our world, 1mW/W/kW at a time™  
SignalWise™  
SmartMax™  
EfficentMax™  
ESBC™  
®
TRUECURRENT *  
SerDes™  
SMART START™  
®
Solutions for Your Success™  
®
®
SPM  
Fairchild  
®
STEALTH™  
SuperFET  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
Fairchild Semiconductor  
FACT Quiet Series™  
®
®
UHC  
®
Ultra FRFET™  
UniFET™  
VCX™  
VisualMax™  
VoltagePlus™  
XS™  
®
mWSaver  
OptoHiT™  
OPTOLOGIC  
OPTOPLANAR  
FACT  
FAST  
®
®
FastvCore™  
FETBench™  
FPS™  
®
®
SupreMOS  
SyncFET™  
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.  
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE  
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY  
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.  
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY  
THEREIN, WHICH COVERS THESE PRODUCTS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE  
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As used here in:  
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Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,  
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Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their  
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PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Datasheet contains the design specifications for product development. Specifications  
may change in any manner without notice.  
Advance Information  
Formative / In Design  
Datasheet contains preliminary data; supplementary data will be published at a later  
date. Fairchild Semiconductor reserves the right to make changes at any time without  
notice to improve design.  
Preliminary  
First Production  
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to  
make changes at any time without notice to improve the design.  
No Identification Needed  
Obsolete  
Full Production  
Datasheet contains specifications on a product that is discontinued by Fairchild  
Semiconductor. The datasheet is for reference information only.  
Not In Production  
Rev. I66  
©2003 Fairchild Semiconductor Corporation  
RFD16N05SM Rev. C0  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
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