NVTFWS070N10MCLTAG [ONSEMI]
Single N-Channel Power MOSFET 100 V, 13 A, 64.4 mΩ;型号: | NVTFWS070N10MCLTAG |
厂家: | ONSEMI |
描述: | Single N-Channel Power MOSFET 100 V, 13 A, 64.4 mΩ |
文件: | 总8页 (文件大小:276K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET - Power, Single
N-Channel
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
65 mW @ 10 V
90 mW @ 4.5 V
100 V
13 A
100 V, 65 mW, 13 A
N−Channel
D (5 − 8)
NVTFS070N10MCL
Features
• Small Footprint (3.3 x 3.3 mm) for Compact Design
G (4)
• Low R
to Minimize Conduction Losses
DS(on)
• Low Capacitance to Minimize Driver Losses
• NVTFWS070N10MCL − Wettable Flanks Product
• AEC−Q101 Qualified and PPAP Capable
S (1, 2, 3)
MARKING
DIAGRAM
• These Devices are Pb−Free and are RoHS Compliant
1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
1
J
WDFN8
(m8FL)
CASE 511AB
XXXXX
Parameter
Drain−to−Source Voltage
Symbol
Value
100
20
Unit
V
AYWWG
G
V
DSS
Gate−to−Source Voltage
V
GS
V
Continuous Drain
Current R
T
= 25°C
= 100°C
= 25°C
I
13
A
C
D
q
JC
XXXX
AYWWG
G
T
C
9.0
25
(Notes 1, 2, 3)
Steady
State
Power Dissipation
T
C
P
W
A
D
WDFNW8
(u8FL WF)
CASE 515AN
R
(Notes 1, 2)
q
JC
T
C
= 100°C
12
Continuous Drain
Current R
T = 25°C
A
I
D
4.5
3.2
2.9
1.5
47
q
JA
T = 100°C
A
(Notes 1, 2, 3)
XXXXX = Specific Device Code
Steady
State
A
Y
= Assembly Location
= Year
Power Dissipation
T = 25°C
A
P
W
D
R
(Notes 1, 2)
q
JA
WW
G
= Work Week
T = 100°C
A
= Pb−Free Package
Pulsed Drain Current
T
C
= 25°C, t = 10 ms
I
DM
A
p
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
Single Pulse Drain−to−Source Avalanche
E
423
260
19
mJ
°C
A
AS
Energy (I
= 0.5 A)
L(pk)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
Source Current (Body Diode)
I
S
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Value
6.0
Unit
Junction−to−Case − Steady State (Note 2)
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
q
JC
R
51
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
February, 2022 − Rev. 0
NVTFS070N10MCL/D
NVTFS070N10MCL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
100
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
67
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
DS
= 0 V,
T = 25°C
1.0
100
100
DSS
GS
J
V
= 100 V
mA
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
V
V
= V , I = 15 mA
1.0
3.0
V
GS(TH)
GS
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
−5.2
54
mV/°C
GS(TH)
J
R
V
= 10 V
I
I
= 3 A
= 2 A
65
90
DS(on)
GS
D
mW
V
GS
= 4.5 V
72
D
Forward Transconductance
g
FS
V
DS
= 10 V, I = 3 A
11
S
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
305
135
1.9
2.7
5.5
0.6
1.0
0.6
2.6
ISS
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
C
OSS
C
RSS
V
V
= 0 V, f = 1 MHz, V = 50 V
pF
nC
GS
DS
Q
= 4.5 V, V = 50 V; I = 2 A
DS D
G(TOT)
GS
V
= 10 V, V = 50 V; I = 3 A
DS D
GS
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
G(TH)
Q
nC
V
GS
GD
GP
V
= 10 V, V = 50 V; I = 3 A
GS
DS
D
Q
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
5.1
1.3
d(ON)
Rise Time
t
r
V
= 10 V, V = 50 V,
DS
GS
D
ns
V
I
= 3 A, R = 6 W
G
Turn−Off Delay Time
t
12.1
2.8
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
V
= 0 V, I = 3 A, T = 25°C
0.84
0.72
19
8
1.3
SD
RR
GS
S
J
V
GS
= 0 V, I = 3 A, T = 125°C
S J
Reverse Recovery Time
Reverse Recovery Charge
Charge Time
t
ns
Q
nC
RR
VGS = 0 V, di/dt = 100 A/ms,
= 1 A
I
S
t
9
S
Discharge Time
t
D
10
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVTFS070N10MCL
TYPICAL CHARACTERISTICS
14
12
10
8
14
V
3.2 V
to10 V
=
GS
3.2 V
V
DS
= 10 V
12
10
8
3.0 V
2.8 V
2.6 V
6
6
T = 25°C
J
4
4
2.4 V
2.2 V
2
2
T = 125°C
J
T = −55°C
J
0
0
0
1
2
3
4
5
0
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
200
180
160
140
120
100
80
100
90
80
70
60
50
40
30
20
T = 25°C
D
T = 25°C
J
J
I
= 3 A
V
= 4.5 V
= 10 V
GS
V
GS
60
40
20
0
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
2.5
2
10
1
T = 175°C
J
V
= 10 V
= 3 A
GS
I
D
T = 150°C
J
T = 125°C
J
0.1
0.01
1.5
1
T = 85°C
J
0.001
0.0001
0.00001
T = 25°C
J
0.5
−50 −25
0
25
50
75
100 125 150 175
10
20
30
40
50
60
70
80
90 100
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVTFS070N10MCL
TYPICAL CHARACTERISTICS
1000
100
10
10
9
C
ISS
8
7
6
5
4
3
2
1
0
C
OSS
Q
Q
GD
GS
V
= 50 V
DS
V
= 0 V
GS
T = 25°C
J
T = 25°C
J
C
I
D
= 3 A
RSS
f = 1 MHz
1
0
1
2
3
4
5
6
0
10 20 30 40 50 60 70 80 90 100
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
100
10
1
10
T = 175°C
J
V
V
= 10 V
= 50 V
= 3 A
V
GS
= 0 V
GS
DS
I
D
T = 125°C
J
T = 85°C
J
t
r
t
T = 25°C
d(off)
J
t
d(on)
T = −55°C
J
t
f
1
1
10
R , GATE RESISTANCE (W)
100
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
, SOURCE−TO−DRAIN VOLTAGE (V)
1
V
SD
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
100
10
1
V
≤ 10 V
GS
Single Pulse
= 25°C
T
C
1 ms
10 ms
T
= 25°C
J(initial)
0.5 ms
T
= 100°C
J(initial)
1
R
Limit
DS(on)
Thermal Limit
Package Limit
10 ms
0.1
0.1
0.1
1
10
100
1000
0.00001
0.0001
0.001
0.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
NVTFS070N10MCL
TYPICAL CHARACTERISTICS
100
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.1
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVTFS070N10MCLTAG
70L1
WDFN8
1500 / Tape & Reel
1500 / Tape & Reel
(Pb−Free)
NVTFWS070N10MCLTAG
70W1
WDFN8
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB
1
SCALE 2:1
2X
ISSUE D
DATE 23 APR 2012
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
D
A
B
E
2X
D1
MILLIMETERS
INCHES
NOM
0.030
−−−
0.012
0.20
C
8
1
7
6
5
4
DIM
A
A1
b
c
MIN
0.70
0.00
0.23
0.15
NOM
0.75
−−−
0.30
0.20
MAX
MIN
MAX
0.031
0.002
0.016
0.010
0.80
0.05
0.40
0.25
0.028
0.000
0.009
0.006
4X
q
E1
0.008
D
3.30 BSC
3.05
2.11
3.30 BSC
3.05
1.60
0.30
0.65 BSC
0.41
0.80
0.43
0.130 BSC
0.120
0.083
0.130 BSC
0.120
0.063
0.012
0.026 BSC
0.016
0.032
0.017
0.005
0.059
−−−
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
2.95
1.98
3.15
2.24
0.116
0.078
0.124
0.088
c
2
3
A1
TOP VIEW
2.95
1.47
0.23
3.15
1.73
0.40
0.116
0.058
0.009
0.124
0.068
0.016
0.10
0.10
C
C
A
C
6X
e
0.012
0.026
0.012
0.002
0.055
0
0.020
0.037
0.022
0.008
0.063
0.30
0.65
0.30
0.06
1.40
0
0.51
0.95
0.56
0.20
1.60
SEATING
PLANE
0.13
1.50
−−−
DETAIL A
SIDE VIEW
DETAIL A
q
12
12
_
_
_
_
8X b
0.10
0.05
C
C
A
B
SOLDERING FOOTPRINT*
8X
e/2
0.42
0.65
4X
L
4X
0.66
PITCH
1
8
4
5
PACKAGE
OUTLINE
K
E2
M
E3
3.60
L1
D2
G
2.30
BOTTOM VIEW
0.57
0.47
0.75
GENERIC
MARKING DIAGRAM*
2.37
3.46
1
XXXXX
DIMENSION: MILLIMETERS
AYWWG
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
G
XXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30561E
WDFN8 3.3X3.3, 0.65P
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF)
CASE 515AN
ISSUE O
DATE 25 AUG 2020
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
*This information is generic. Please refer to
A
Y
= Assembly Location
= Year
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXX
AYWWG
G
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON24556H
WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
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