NVTFS5C471NLWFTAG [ONSEMI]
MOSFET â Power, Single N-Channel;型号: | NVTFS5C471NLWFTAG |
厂家: | ONSEMI |
描述: | MOSFET â Power, Single N-Channel |
文件: | 总7页 (文件大小:276K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MOSFET – Power, Single
N-Channel
40 V, 9.0 mW, 41 A
NVTFS5C471NL
Features
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• Small Footprint (3.3 x 3.3 mm) for Compact Design
• Low R
to Minimize Conduction Losses
DS(on)
• Low Capacitance to Minimize Driver Losses
• NVTFS5C471NLWF − Wettable Flanks Product
• AEC−Q101 Qualified and PPAP Capable
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
9.0 mW @ 10 V
40 V
41 A
• These Devices are Pb−Free and are RoHS Compliant
15.5 mW @ 4.5 V
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
N−Channel
D (5 − 8)
Parameter
Drain−to−Source Voltage
Symbol
Value
40
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
20
V
Continuous Drain
Current R
T
= 25°C
= 100°C
= 25°C
I
41
A
C
D
q
JC
G (4)
T
C
27
(Notes 1, 2, 3, 4)
Steady
State
Power Dissipation
T
C
P
30
W
A
D
R
(Notes 1, 2, 3)
S (1, 2, 3)
q
JC
T
C
= 100°C
15
Continuous Drain
Current R
T = 25°C
A
I
D
12
q
JA
MARKING DIAGRAM
T = 100°C
A
10
(Notes 1, 3, 4)
Steady
State
1
Power Dissipation
T = 25°C
A
P
3.0
2.0
163
W
1
D
S
S
S
G
D
D
D
D
R
(Notes 1, 3)
q
JA
XXXX
AYWWG
G
WDFN8
(m8FL)
CASE 511AB
T = 100°C
A
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
XXXX = Specific Device Code
A
Y
WW
G
= Assembly Location
= Year
= Work Week
Source Current (Body Diode)
I
24
66
A
S
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (I
= 2.2 A)
= Pb−Free Package
L(pk)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
260
°C
(Note: Microdot may be in either location)
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Value
5.2
Unit
Junction−to−Case − Steady State (Note 3)
Junction−to−Ambient − Steady State (Note 3)
R
°C/W
q
JC
R
50
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
2
3. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
4. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
September, 2019 − Rev. 2
NVTFS5C471NL/D
NVTFS5C471NL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
V
= 0 V, I = 250 mA
40
V
(BR)DSS
GS
D
I
T = 25°C
10
mA
DSS
J
V
= 0 V,
= 40 V
GS
DS
V
T = 125°C
J
250
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
I
V
V
V
= 0 V, V = 20 V
nA
GSS
DS
GS
V
= V , I = 20 mA
1.2
2.2
9.0
V
GS(TH)
GS
DS
D
Drain−to−Source On Resistance
R
V
= 10 V, I = 10 A
7.4
12.3
36
mW
DS(on)
GS
D
= 4.5 V, I = 10 A
15.5
GS
D
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
FS
V
= 15 V, I = 20 A
S
DS
D
C
660
270
12
pF
iss
V
GS
= 0 V, f = 1.0 MHz,
Output Capacitance
C
oss
V
DS
= 25 V
Reverse Transfer Capacitance
Total Gate Charge
C
rss
Q
Q
5.5
1.4
2.6
1.8
12
nC
nC
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q
G(TH)
V
= 4.5 V, V = 32 V, I = 20 A
DS D
GS
Q
GS
GD
Q
V
= 10 V, V = 32 V, I = 20 A
nC
ns
G(TOT)
GS
DS
D
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
t
9.0
49
20
6
d(on)
t
r
V
= 4.5 V, V = 32 V,
DS
GS
D
I
= 20 A, R = 1.0 W
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
V
= 0 V,
T = 25°C
0.8
0.7
23
11
1.2
V
SD
GS
S
J
I
= 10 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
a
V
GS
= 0 V, dl /dt = 100 A/ms,
S
I
S
= 20 A
Discharge Time
11
b
Reverse Recovery Charge
Q
10
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NVTFS5C471NL
TYPICAL CHARACTERISTICS
60
50
40
30
20
60
V
DS
= 10 V
10 V to 4.5 V
50
40
30
20
4.0 V
3.8 V
3.6 V
3.4 V
3.2 V
T = 25°C
J
10
0
10
0
T = 125°C
J
T = −55°C
J
0
0.5
1.0
1.5
2.0
2.5
3.0
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
18
16
14
12
50
45
40
35
30
25
20
15
10
T = 25°C
J
T = 25°C
D
J
I
= 10 A
V
= 4.5 V
GS
GS
10
8
V
= 10 V
6
4
5
0
3
4
5
6
7
8
9
10
10
15
20
25
30
35
40
45
50
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
2.0
1.5
1.0
100K
10K
V
I
= 10 V
= 10 A
GS
T = 175°C
J
D
T = 125°C
J
1K
100
10
T = 85°C
J
0.5
0
−50 −25
0
25
50
75
100 125 150 175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVTFS5C471NL
TYPICAL CHARACTERISTICS
1000
100
10
9
C
ISS
8
7
6
5
4
C
OSS
Q
Q
GD
GS
10
1
3
2
1
0
C
V
= 32 V
= 20 A
RSS
DS
V
= 0 V
GS
I
D
T = 25°C
J
T = 25°C
J
f = 1 MHz
0
5
10
15
20
25
30
35
40
0
2
4
6
8
10
12
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
V
GS
= 0 V
100
t
r
t
t
d(off)
d(on)
10
10
1
t
f
V
V
= 4.5 V
= 32 V
= 20 A
GS
DS
I
D
T = 125°C
J
T = 25°C T = −55°C
J
J
1
1
10
R , GATE RESISTANCE (W)
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
10
1000
100
10
T (initial) = 25°C
J
T
V
= 25°C
C
T (initial) = 100°C
J
≤ 10 V
GS
1
Single Pulse
10 ms
0.5 ms
1 ms
1
R
Limit
DS(on)
Thermal Limit
Package Limit
10 ms
0.1
0.1
1E−5
1E−4
1E−3
1E−2
0.1
1
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE(V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
NVTFS5C471NL
TYPICAL CHARACTERISTICS
100
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVTFS5C471NLTAG
471L
WDFN8
1500 / Tape & Reel
1500 / Tape & Reel
(Pb−Free)
NVTFS5C471NLWFTAG
71LW
WDFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB
ISSUE D
1
DATE 23 APR 2012
SCALE 2:1
2X
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
D
A
B
E
2X
D1
MILLIMETERS
INCHES
NOM
0.030
−−−
0.012
0.20
C
8
1
7
6
5
4
DIM
A
A1
b
c
MIN
0.70
0.00
0.23
0.15
NOM
0.75
−−−
0.30
0.20
MAX
MIN
MAX
0.031
0.002
0.016
0.010
0.80
0.05
0.40
0.25
0.028
0.000
0.009
0.006
4X
q
E1
0.008
D
3.30 BSC
3.05
2.11
3.30 BSC
3.05
1.60
0.30
0.65 BSC
0.41
0.80
0.43
0.130 BSC
0.120
0.083
0.130 BSC
0.120
0.063
0.012
0.026 BSC
0.016
0.032
0.017
0.005
0.059
−−−
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
2.95
1.98
3.15
2.24
0.116
0.078
0.124
0.088
c
2
3
A1
TOP VIEW
2.95
1.47
0.23
3.15
1.73
0.40
0.116
0.058
0.009
0.124
0.068
0.016
0.10
0.10
C
C
A
C
6X
e
0.012
0.026
0.012
0.002
0.055
0
0.020
0.037
0.022
0.008
0.063
0.30
0.65
0.30
0.06
1.40
0
0.51
0.95
0.56
0.20
1.60
SEATING
PLANE
0.13
1.50
−−−
DETAIL A
SIDE VIEW
DETAIL A
q
12
12
_
_
_
_
8X b
0.10
0.05
C
C
A
B
SOLDERING FOOTPRINT*
8X
e/2
0.42
0.65
4X
L
4X
0.66
PITCH
1
8
4
5
PACKAGE
OUTLINE
K
E2
M
E3
3.60
L1
D2
G
2.30
BOTTOM VIEW
0.57
0.47
0.75
GENERIC
MARKING DIAGRAM*
2.37
3.46
1
XXXXX
DIMENSION: MILLIMETERS
AYWWG
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
G
XXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30561E
WDFN8 3.3X3.3, 0.65P
PAGE 1 OF 1
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