NVMFD027N10MCLT1G [ONSEMI]
Dual N-Channel Power MOSFET 100 V, 28 A, 26 mΩ;
| 型号： | NVMFD027N10MCLT1G |
| 厂家： | 
ONSEMI |
| 描述： | Dual N-Channel Power MOSFET 100 V, 28 A, 26 mΩ |
| 文件： | 总7页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET - Power, Dual
N-Channel
100 V, 26 mW, 28 A
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
26 mW @ 10 V
35 mW @ 4.5 V
100 V
28 A
NVMFD027N10MCL
D1
D2
Features
• Small Footprint (5x6 mm) for Compact Design
• Low R
to Minimize Conduction Losses
• Low Q and Capacitance to Minimize Driver Losses
DS(on)
G1
G2
G
• AEC−Q101 Qualified and PPAP Capable
• NVMFWD027N10MCL − Wettable Flank Products
• These Devices are Pb−Free, Halogen Free/BFR Free, Beryllium Free
and are RoHS Compliant
S1
DUAL N−CHANNEL
S2
MARKING
DIAGRAM
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
100
20
Unit
V
1
V
DSS
DFN8 5x6
(SO8FL)
CASE 506BT
XXXXXX
AYWZZ
Gate−to−Source Voltage
V
GS
V
Continuous Drain
T
= 25°C
= 100°C
= 25°C
I
28
A
C
D
Current R
(Note 1)
q
JC
T
C
20
Steady
State
XXXXXX = Specific Device Code
Power Dissipation
(Note 1)
T
C
P
46
W
A
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
D
R
q
JC
T
C
= 100°C
23
Continuous Drain
Current R
T = 25°C
I
7.4
5.2
3.1
1.6
115
A
D
q
JA
T = 100°C
A
(Notes 1, 2)
Steady
State
Power Dissipation
T = 25°C
A
P
W
D
ORDERING INFORMATION
R
(Notes 1, 2)
q
JA
T = 100°C
A
Device
Package Shipping†
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
NVMFD027N10MCLT1G
DFN8
(Pb−Free)
1500 /
Tape &
Reel
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
NVMFWD027N10MCLT1G
(Wettable Flanks)
Source Current (Body Diode)
I
S
35
A
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Single Pulse Drain−to−Source Avalanche
E
154
mJ
AS
Energy (I
= 1.3 A)
L(pk)
Lead Temperature Soldering Reflow for Solder-
ing Purposes (1/8″ from case for 10 s)
T
260
°C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Value
3.29
48
Unit
Junction−to−Case − Steady State (Note 1)
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
q
JC
R
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using 1 in pad size, 2 oz. Cu pad.
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
October, 2021 − Rev. 0
NVMFD027N10MCL/D
NVMFD027N10MCL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
100
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
50
mV/°C
(BR)DSS
T
J
Zero Gate Voltage Drain Current
I
T = 25°C
1.0
100
100
mA
DSS
J
V
DS
= 0 V,
GS
V
= 100 V
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS
I
V
V
= 0 V, V = 20 V
nA
GSS
DS
GS
GS
Gate Threshold Voltage
V
= V , I = 38 mA
1
3
V
GS(TH)
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
−5.4
21
mV/°C
mW
GS(TH)
J
R
V
= 10 V, I = 7 A
26
35
DS(on)
GS
D
V
GS
= 4.5 V, I = 5 A
28
D
Forward Transconductance
CHARGES & CAPACITANCES
Input Capacitance
g
V
= 10 V, I = 7 A
27
S
FS
DS
D
C
720
300
6
pF
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0 V, f = 1 MHz, V = 50 V
DS
GS
Reverse Transfer Capacitance
Total Gate Charge
Q
V
= 4.5 V, V = 50 V, I = 7 A
5.5
11
nC
G(TOT)
Q
G(TOT)
GS
DS
D
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
1.1
2
G(TH)
Q
V
GS
= 10 V, V = 50 V, I = 7 A
DS D
GS
GD
GP
Q
V
1.4
2.5
V
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
t
7
ns
d(ON)
Rise Time
t
2.5
19
3.2
r
V
= 10 V, V = 50 V,
DS
GS
D
I
= 7 A, R = 6 W
G
Turn−Off Delay Time
t
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
0.84
0.73
28
1.3
V
SD
RR
J
V
= 0 V,
GS
S
I
= 7 A
T = 125°C
J
Reverse Recovery Time
Reverse Recovery Charge
Charge Time
t
ns
nC
ns
ns
Q
17
RR
V
= 0 V, dI /dt = 100 A/ms,
S
GS
I
S
= 3 A
t
13.9
14.2
a
Discharge Time
t
b
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Switching characteristics are independent of operating junction temperatures
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2
NVMFD027N10MCL
TYPICAL CHARACTERISTICS
25
20
15
10
5
25
V
DS
= 10 V
3.0 V
2.8 V
2.6 V
20
15
10
V
= 10 V to 3.2 V
GS
T = 25°C
J
2.4 V
2.2 V
5
0
T = 150°C
J
T = −55°C
J
0
0
1
2
3
4
5
0
1
2
3
4
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
50
45
40
35
30
25
20
15
10
33
31
29
27
25
23
21
19
T = 25°C
D
J
T = 25°C
J
I
= 7 A
V
= 4.5 V
= 10 V
GS
V
GS
17
15
5
0
2
3
4
5
6
7
8
9
10
2
3
4
5
6
7
8
9
10
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
2.5
2.0
1.5
10
1
V
= 10 V
= 7 A
GS
T = 175°C
J
I
D
T = 150°C
J
T = 125°C
J
0.1
0.01
T = 85°C
J
0.001
0.0001
1.0
0.5
T = 25°C
J
0.00001
−50 −25
0
25
50
75 100 125 150 175
10 20
30
40
50
60
70
80
90 100
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMFD027N10MCL
TYPICAL CHARACTERISTICS
1000
100
10
C
ISS
9
8
7
6
5
4
3
C
OSS
Q
Q
GD
GS
10
1
T = 25°C
V
= 0 V
J
2
1
0
GS
I
D
= 7 A
C
T = 25°C
RSS
J
V
DS
= 50 V
f = 1 MHz
0
2
4
6
8
10
12
0
10 20 30 40
50 60 70 80
90 100
Q , TOTAL GATE CHARGE (nC)
G
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
100
10
V
V
= 10 V
= 50 V
GS
V
GS
= 0 V
t
DS
d(off)
I
D
= 50 A
t
f
t
r
t
d(on)
10
T = 125°C
J
T = 25°C
J
T = −55°C
J
1
1
1
10
R , GATE RESISTANCE (W)
100
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
10
1000
T
= 25°C
C
Single Pulse
≤ 10 V
V
GS
100
10
T
= 25°C
J(initial)
10 ms
T
= 125°C
J(initial)
1
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.5 ms
1 ms
10 ms
0.1
0.1
0.1
1
10
100
1000
0.00001
0.0001
t , TIME IN AVALANCHE (s)
AV
0.001
0.01
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVMFD027N10MCL
TYPICAL CHARACTERISTICS
100
10
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
1
0.1
0.01
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t, PULSE TIME (sec)
Figure 13. Transient Thermal Impedance
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5
NVMFD027N10MCL
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
2X
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
PIN ONE
IDENTIFIER
E1
4X
h
MILLIMETERS
DIM
A
A1
b
b1
c
MIN
0.90
−−−
0.33
0.33
0.20
MAX
−−−
−−−
0.42
0.42
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
c
A1
1
2
3
4
−−−
TOP VIEW
D
5.15 BSC
4.90
4.10
1.70
6.15 BSC
5.90
4.15
1.27 BSC
0.55
−−−
−−−
−−−
0.61
3.50
2.00
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
DETAIL A
A
5.70
3.90
6.10
4.40
C
SEATING
PLANE
NOTE 6
C
NOTE 4
SIDE VIEW
DETAIL A
0.45
−−−
0.51
0.56
0.48
3.25
1.80
0.65
12
−−−
−−−
_
D2
D3
0.71
3.75
2.20
4X L
K
M
N
e
1
4
DETAIL B
SOLDERING FOOTPRINT*
ALTERNATE
DETAIL B
CONSTRUCTION
4.56
2X
2.08
4X
b1
2X
0.56
8X
0.75
N
E2
M
8
5
4X
G
b
8X
4X
1.40
0.10
0.05
C
C
A B
K1
6.59
4.84
2.30
NOTE 3
BOTTOM VIEW
3.70
0.70
4X
1.27
PITCH
1.00
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
NVMFD027N10MCL
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