NTMS4503NR2G [ONSEMI]
功率 MOSFET,28V,14A,7mΩ,单 N 沟道,SO-8;型号: | NTMS4503NR2G |
厂家: | ONSEMI |
描述: | 功率 MOSFET,28V,14A,7mΩ,单 N 沟道,SO-8 开关 光电二极管 晶体管 |
文件: | 总7页 (文件大小:156K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NTMS4503N
Power MOSFET
28 V, 14 A, N−Channel, SOIC−8
Features
• Low R
DS(on)
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• High Power and Current Handling Capability
• Low Gate Charge
I
Max
D
• Pb−Free Package is Available
V
R
DS(on)
Typ
(BR)DSS
(Note 1)
Applications
7.0 mW @ 10 V
8.8 mW @ 4.5 V
28 V
14 A
• DC/DC Converters
• Motor Drives
• Synchronous Rectifier − POL
• Buck Low−Side
D
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Drain−to−Source Voltage
Symbol Value Unit
G
V
28
V
V
A
DSS
Gate−to−Source Voltage − Continuous
Drain Current
V
$20
GS
S
I
D
Continuous @ T = 25°C (Note 1)
14
12
9.0
40
A
MARKING DIAGRAM &
PIN ASSIGNMENT
Continuous @ T = 25°C (Note 2)
A
Continuous @ T = 25°C (Note 3)
A
Single Pulse (tp = 10 ms)
I
DM
D
D
D
D
8
8
Total Power Dissipation
P
W
D
T = 25°C (Note 1)
A
T = 25°C (Note 3)
A
2.5
1.66
0.93
A
1
4503N
AYWW G
G
T = 25°C (Note 2)
SOIC−8
CASE 751
STYLE 12
Operating and Storage Temperature
T , T
−55 to
150
°C
J
stg
1
S
S
S
G
Single Pulse Drain−to−Source Avalanche
E
75
mJ
AS
Energy − Starting T = 25°C
J
4503N = Specific Device Code
(V = 30 V, V = 10 V, I = 12.2 A,
DD
GS
L
A
Y
= Assembly Location
= Year
L = 1.0 mH, R = 25 W)
G
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
T
260
°C
L
WW
G
= Work Week
= Pb−Free Package
THERMAL RESISTANCE RATINGS
Rating
(Note: Microdot may be in either location)
Symbol Value Unit
ORDERING INFORMATION
Thermal Resistance
R
°C/W
q
JA
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Ambient (Note 3)
50
75
135
Device
NTMS4503NR2
Package
Shipping†
SOIC−8
2500/Tape & Reel
2500/Tape & Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using minimum recommended pad size
(Cu area 0.412 in sq), t < 10 s.
NTMS4503NR2G SOIC−8
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
2. Surface−mounted on FR4 board using 1″ pad size
(Cu area 1.127 in sq) steady state.
3. Surface−mounted on FR4 board using minimum recommended pad size
(Cu area 0.412 in sq), steady state.
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
March, 2007 − Rev. 2
NTMS4503N/D
NTMS4503N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V
V
= 0 V, I = 250 mA
28
−
31
22
−
−
V
(BR)DSS
GS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
−
mV/°C
(BR)DSS
T
J
Zero Gate Voltage Drain Current
I
T = 25°C
−
−
−
−
−
−
1.0
25
mA
DSS
J
V
= 0 V, V = 24 V
DS
GS
T = 100°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = $20 V
$100
nA
GSS
DS
GS
V
V
= V , I = 250 mA
1.0
−
−
2.0
−
V
GS(TH)
GS
DS
D
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
−
−5.0
7.0
8.8
30
mV/°C
mW
GS(TH)
J
R
DS(on)
V
= 10 V, I = 14 A
−
8.0
9.8
−
GS
D
V
= 4.5 V, I = 10 A
−
GS
D
Forward Transconductance
g
V
= 10 V, I = 14 A
−
S
FS
DS
D
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
C
−
−
−
−
−
−
−
2400
1000
375
23
−
−
−
−
−
−
−
pF
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0 V, f = 1.0 MHz, V = 16 V
DS
GS
Reverse Transfer Capacitance
Total Gate Charge
Q
nC
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Q
2.0
G(TH)
V
= 4.5 V, V = 16 V, I = 10 A
DS D
GS
Q
5.0
GS
Q
12
GD
SWITCHING CHARACTERISTICS, V = V (Note 5)
GS
Turn−On Delay Time
Rise Time
t
−
−
−
−
18.5
70
−
−
−
−
ns
d(ON)
tr
V
= 4.5 V, V = 16 V, I = 10 A,
GS
DD
D
R
G
= 2.0 W
Turn−Off Delay Time
Fall Time
t
21
d(OFF)
t
23
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
−
−
−
−
−
−
0.82
0.65
48
1.2
−
V
SD
RR
J
V
= 0 V, I = 10 A
S
GS
T = 125°C
J
Reverse Recovery Time
Charge Time
t
−
ns
V
= 0 V,
T
23
−
GS
a
d
ISD
/d = 100 A/ms,
t
S
Discharge Time
T
25
−
I
= 14 A
b
Reverse Recovery Charge
Q
25
−
nC
RR
4. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NTMS4503N
TYPICAL PERFORMANCE CURVES
30
25
20
15
10
35
V
= 10, 3.6, 3.2 V
T = 25°C
GS
J
V
≥ 10 V
DS
3 V
30
25
20
15
10
2.8 V
2.6 V
T = 25°C
J
5
0
5
0
2.4 V
2.2 V
T = −55°C
J
T = 100°C
J
0
1
2
3
4
5
6
7
8
9
10
1
1.5
2
2.5
3
3.5
4
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.012
0.011
0.010
0.009
0.008
T = 25°C
J
I
= 14 A
D
0.011
0.010
0.009
0.008
0.007
0.006
T = 25°C
J
V
V
= 4.5 V
= 10 V
GS
GS
0.007
0.006
0.005
0.004
4
8
12
16
20
9
1
3
5
7
11
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
I
DRAIN CURRENT (AMPS)
D,
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.6
10000
V
= 0 V
I
= 14 A
GS
D
T = 150°C
J
V
= 4.5 V
GS
1.4
1.2
1
1000
100
10
T = 100°C
J
0.8
0.6
−50 −25
0
25
50
75
100 125
150
2
4
6
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
8
10
12
14
16
18
20
T , JUNCTION TEMPERATURE (°C)
V
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NTMS4503N
TYPICAL PERFORMANCE CURVES
5
20
16
12
4200
3600
3000
2400
1800
1200
T = 25°C
QT
J
C
C
iss
4
V
DS
V
GS
3
2
Q
Q
GD
GS
rss
C
iss
8
C
oss
4
0
1
0
600
0
I
= 10 A
D
T = 25°C
J
V
= 0 V
V
V
= 0 V
5
DS
GS
C
rss
10
5
0
10
15
20
0
5
10
15
20
25
Q , TOTAL GATE CHARGE (nC)
V
G
GS
DS
Figure 8. Gate−To−Source and
Drain−To−Source Voltage vs. Total Charge
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000
10
9
V
I
V
= 16 V
= 10 A
= 4.5 V
V
= 0 V
GS
DD
GS
T = 25°C
J
t
D
r
8
t
f
t
7
d(off)
d(on)
100
10
1
t
6
5
4
3
2
1
0
0.4
1
10
100
0.5
0.6
0.7
0.8
0.9
1.0
R , GATE RESISTANCE (OHMS)
G
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
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相关型号:
NTMS4700NR2G
8600mA, 30V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, LEAD FREE, CASE 751-07, SOP-8
ROCHESTER
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