NTD15N06L-1 [ONSEMI]

Power MOSFET 15 Amps, 60 Volts, Logic Level; 功率MOSFET 15安培， 60伏特，逻辑电平


型号：	NTD15N06L-1
厂家：	ONSEMI
描述：	Power MOSFET 15 Amps, 60 Volts, Logic Level 功率MOSFET 15安培， 60伏特，逻辑电平晶体晶体管功率场效应晶体管开关脉冲
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NTD15N06L

Power MOSFET

15 Amps, 60 Volts, Logic Level

N−Channel DPAK

Designed for low voltage, high speed switching applications in

power supplies, converters and power motor controls and bridge

circuits.

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Typical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

15 AMPERES

60 VOLTS

_DS(on)= 85 mW (TYP)

N−Channel

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain−to−Source Voltage

Vdc

DSS

Drain−to−Gate Voltage (R = 1.0 MW)

DGR

Gate−to−Source Voltage

− Continuous

"15

"20

− Non−repetitive (t v10 ms)

Drain Current

− Continuous @ T = 25°C

MARKING DIAGRAMS

Adc

Apk

− Continuous @ T = 100°C

Drain

− Single Pulse (t v10 ms)

Total Power Dissipation @ T = 25°C

0.32

2.1

W/°C

Derate above 25°C

DPAK

Total Power Dissipation @ T = 25°C (Note 1)

CASE 369C

Total Power Dissipation @ T = 25°C (Note 2)

1.5

Style 2

Operating and Storage Temperature Range

T , T

−55 to

+175

°C

stg

Gate

Drain

Single Pulse Drain−to−Source Avalanche

Source

Energy − Starting T = 25°C

(V = 25 Vdc, V = 5.0 Vdc, L = 1.0 mH,

Drain

= 11 A, V = 60 Vdc)

L(pk)

Thermal Resistance

− Junction−to−Case

°C/W

°C

3.13

71.4

100

− Junction−to−Ambient (Note 1)

− Junction−to−Ambient (Note 2)

DPAK

CASE 369D

Style 2

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

260

15N06L

Device Code

= Year

= Work Week

1. When surface mounted to an FR4 board using 0.5 sq. in. pad size,.

2. When surface mounted to an FR4 board using the minimum recommended

pad size.

Gate Drain Source

ORDERING INFORMATION

Device

Package

Shipping

75 Units/Rail

NTD15N06L

NTD15N06L−1

DPAK

Straight Lead

NTD15N06LT4

DPAK

2500/Tape & Reel

Semiconductor Components Industries, LLC, 2003

Publication Order Number:

September, 2003 − Rev. 1

NTD15N06L/D

NTD15N06L

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 3)

Vdc

(BR)DSS

(V = 0 Vdc, I = 250 mAdc)

Temperature Coefficient (Positive)

−

62.9

−

mV/°C

mAdc

Zero Gate Voltage Drain Current

DSS

(V = 60 Vdc, V = 0 Vdc)

−

1.0

(V = 60 Vdc, V = 0 Vdc, T = 150°C)

Gate−Body Leakage Current (V = ±15 Vdc, V = 0 Vdc)

−

±100

nAdc

Vdc

GSS

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage (Note 3)

(V = V , I = 250 mAdc)

GS(th)

1.0

−

1.6

4.2

2.0

−

Threshold Temperature Coefficient (Negative)

mV/°C

Static Drain−to−Source On−Resistance (Note 3)

DS(on)

(V = 5.0 Vdc, I = 7.5 Adc)

−

100

Static Drain−to−Source On−Voltage (Note 3)

(V = 5.0 Vdc, I = 15 Adc)

Vdc

DS(on)

−

1.46

1.2

1.8

−

(V = 5.0 Vdc, I = 7.5 Adc, T = 125°C)

Forward Transconductance (Note 3) (V = 8.0 Vdc, I = 6.0 Adc)

−

9.1

−

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

−

310

106

440

150

iss

(V = 25 Vdc, V = 0 Vdc,

Output Capacitance

oss

f = 1.0 MHz)

Transfer Capacitance

rss

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

−

120

210

−

d(on)

Rise Time

(V = 30 Vdc, I = 15 Adc,

= 5.0 Vdc, R = 9.1 W) (Note 3)

Turn−Off Delay Time

Fall Time

d(off)

Gate Charge

7.3

2.3

4.4

(V = 48 Vdc, I = 15 Adc,

= 5.0 Vdc) (Note 3)

−

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage

(I = 15 Adc, V = 0 Vdc) (Note 3)

−

0.96

0.83

1.2

−

Vdc

(I = 15 Adc, V = 0 Vdc, T = 150°C)

Reverse Recovery Time

−

(I = 15 Adc, V = 0 Vdc,

dI /dt = 100 A/ms) (Note 3)

Reverse Recovery Stored Charge

0.043

3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

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NTD15N06L

= 10 V

6 V

5 V

≥ 10 V

8 V

4.5 V

4 V

3.5 V

3 V

T = 25°C

T = 100°C

T = −55°C

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

Figure 2. Transfer Characteristics

0.32

0.24

0.32

0.24

= 5 V

= 10 V

T = 100°C

0.16

0.08

0.16

0.08

T = 25°C

T = −55°C

I , DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus Drain Current

Figure 4. On−Resistance versus Drain Current

10000

1.8

1.6

1.4

1.2

= 0 V

= 7.5 A

= 5 V

T = 150°C

1000

100

T = 100°C

0.8

0.6

−50 −25

75 100 125 150 175

T , JUNCTION TEMPERATURE (°C)

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with

Temperature

Figure 6. Drain−to−Source Leakage Current

versus Voltage

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NTD15N06L

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (Dt)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The capacitance (C ) is read from the capacitance curve at

a voltage corresponding to the off−state condition when

iss

calculating t

and is read at a voltage corresponding to the

d(on)

on−state when calculating t

d(off)

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is affected by the parasitic circuit elements. If

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

The published capacitance data is difficult to use for

calculating rise and fall because drain−gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a

resistive load, V remains virtually constant at a level

known as the plateau voltage, V . Therefore, rise and fall

SGP

times may be approximated by the following:

t = Q x R /(V − V )

GSP

t = Q x R /V

GSP

where

= the gate drive voltage, which varies from zero to V

R = the gate drive resistance

and Q and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

= R C In [V /(V − V )]

G iss GG GG GSP

d(on)

d(off)

= R C In (V /V )

GG GSP

iss

1200

= 0 V

T = 25°C

1000

800

600

400

iss

rss

iss

200

oss

rss

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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NTD15N06L

1000

= 30 V

= 15 A

= 5 V

100

d(off)

d(on)

= 15 A

T = 25°C

R , GATE RESISTANCE (W)

100

Q , TOTAL GATE CHARGE (nC)

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

= 0 V

T = 25°C

T = 150°C

T = 25°C

0.3

0.4

0.5

0.6

0.7

0.8

0.9

, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain−to−source voltage and

drain current that a transistor can handle safely when it is

forward biased. Curves are based upon maximum peak

A Power MOSFET designated E−FET can be safely used

in switching circuits with unclamped inductive loads. For

reliable operation, the stored energy from circuit inductance

dissipated in the transistor while in avalanche must be less

than the rated limit and adjusted for operating conditions

differing from those specified. Although industry practice is

to rate in terms of energy, avalanche energy capability is not

a constant. The energy rating decreases non−linearly with an

increase of peak current in avalanche and peak junction

temperature.

junction temperature and a case temperature (T ) of 25°C.

Peak repetitive pulsed power limits are determined by using

the thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance −

General Data and Its Use.”

Switching between the off−state and the on−state may

traverse any load line provided neither rated peak current

Although many E−FETs can withstand the stress of

drain−to−source avalanche at currents up to rated pulsed

(I ) nor rated voltage (V ) is exceeded and the

DSS

transition time (t ,t ) do not exceed 10 ms. In addition the total

current (I ), the energy rating is specified at rated

r f

power averaged over a complete switching cycle must not

continuous current (I ), in accordance with industry custom.

exceed (T

− T )/(R ).

The energy rating must be derated for temperature as shown

J(MAX)

qJC

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NTD15N06L

in the accompanying graph (Figure 12). Maximum energy at

currents below rated continuous I can safely be assumed to

equal the values indicated.

SAFE OPERATING AREA

100

= 15 V

= 11 A

SINGLE PULSE

10 ms

= 25°C

100 ms

1 ms

10 ms

LIMIT

DS(on)

THERMAL LIMIT

PACKAGE LIMIT

0.1

100

125

150

175

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

T , STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

1.0

D = 0.5

0.2

0.1

0.05

0.02

(pk)

0.1

(t) = r(t) R

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t

0.01

SINGLE PULSE

J(pk)

− T = P

(t)

(pk)

DUTY CYCLE, D = t /t

0.01

0.00001

0.0001

0.001

0.01

t, TIME (ms)

0.1

Figure 13. Thermal Response

di/dt

TIME

0.25 I

Figure 14. Diode Reverse Recovery Waveform

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NTD15N06L

INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the

total design. The footprint for the semiconductor packages

must be the correct size to ensure proper solder connection

interface between the board and the package. With the

correct pad geometry, the packages will self align when

subjected to a solder reflow process.

6.20

3.0

0.244

0.118

2.58

0.101

5.80

1.6

6.172

0.243

0.228

0.063

inches

SCALE 3:1

DPAK

The power dissipation for a surface mount device is a

175°C − 25°C

71.4°C/W

= 2.1 Watts

P_D=

function of the drain pad size. These can vary from the

minimum pad size for soldering to a pad size given for

maximum power dissipation. Power dissipation for a

The 71.4°C/W for the DPAK package assumes the use of

0.5 sq. in. source pad on a glass epoxy printed circuit board

to achieve a power dissipation of 2.1 W. There are other

alternatives to achieving higher power dissipation from the

surface mount packages. One is to increase the area of the

drain pad. By increasing the area of the drain pad, the

power dissipation can be increased. Although one can

almost double the power dissipation with this method, one

will be giving up area on the printed circuit board which

can defeat the purpose of using surface mount technology.

surface mount device is determined by T

, the

J(max)

maximum rated junction temperature of the die, R , the

thermal resistance from the device junction to ambient, and

the operating temperature, T . Using the values provided

on the data sheet, P can be calculated as follows:

T_J(max)− T_A

P_D=

R_JA

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values

For example, a graph of R versus drain pad area is shown

in Figure 15.

into the equation for an ambient temperature T of 25°C,

one can calculate the power dissipation of the device. For a

DPAK device, P is calculated as follows.

100

Board Material = 0.0625″

G−10/FR−4, 2 oz Copper

2.1 Watts

T = 25°C

3.6 Watts

6.0 Watts

A, AREA (SQUARE INCHES)

Figure 15. Thermal Resistance versus Drain Pad

Area for the DPAK Package (Typical)

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NTD15N06L

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed

pattern of the opening in the stencil for the drain pad is not

critical as long as it allows approximately 50% of the pad to

be covered with paste.

circuit board, solder paste must be applied to the pads.

Solder stencils are used to screen the optimum amount.

These stencils are typically 0.008 inches thick and may be

made of brass or stainless steel. For packages such as the

SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,

SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode

packages, the stencil opening should be the same as the pad

size or a 1:1 registration. This is not the case with the DPAK

SOLDER PASTE

OPENINGS

and D PAK packages. If one uses a 1:1 opening to screen

solder onto the drain pad, misalignment and/or

“tombstoning” may occur due to an excess of solder. For

these two packages, the opening in the stencil for the paste

should be approximately 50% of the tab area. The opening

for the leads is still a 1:1 registration. Figure 16 shows a

STENCIL

Figure 16. Typical Stencil for DPAK and

D²PAK Packages

typical stencil for the DPAK and D PAK packages. The

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated

to a high temperature, failure to complete soldering within

a short time could result in device failure. Therefore, the

following items should always be observed in order to

minimize the thermal stress to which the devices are

subjected.

• Always preheat the device.

• The delta temperature between the preheat and

soldering should be 100°C or less.*

• When shifting from preheating to soldering, the

maximum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and

result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied

during cooling.

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering

method, the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

* * Soldering a device without preheating can cause

excessive thermal shock and stress which can result in

damage to the device.

* * Due to shadowing and the inability to set the wave

height to incorporate other surface mount components, the

D PAK is not recommended for wave soldering.

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NTD15N06L

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of

The line on the graph shows the actual temperature that

might be experienced on the surface of a test board at or

near a central solder joint. The two profiles are based on a

high density and a low density board. The Vitronics

SMD310 convection/infrared reflow soldering system was

used to generate this profile. The type of solder used was

62/36/2 Tin Lead Silver with a melting point between

177−189°C. When this type of furnace is used for solder

reflow work, the circuit boards and solder joints tend to

heat first. The components on the board are then heated by

conduction. The circuit board, because it has a large surface

area, absorbs the thermal energy more efficiently, then

distributes this energy to the components. Because of this

effect, the main body of a component may be up to 30

degrees cooler than the adjacent solder joint.

control settings that will give the desired heat pattern. The

operator must set temperatures for several heating zones,

and a figure for belt speed. Taken together, these control

settings make up a heating “profile” for that particular

circuit board. On machines controlled by a computer, the

computer remembers these profiles from one operating

session to the next. Figure 17 shows a typical heating

profile for use when soldering a surface mount device to a

printed circuit board. This profile will vary among

soldering systems but it is a good starting point. Factors that

can affect the profile include the type of soldering system in

use, density and types of components on the board, type of

solder used, and the type of board or substrate material

being used. This profile shows temperature versus time.

STEP 1

PREHEAT

ZONE 1

“RAMP”

STEP 2

VENT

“SOAK” ZONES 2 & 5

“RAMP”

STEP 3

HEATING

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

STEP 6

VENT

STEP 7

COOLING

205° TO 219°C

PEAK AT

SOLDER

JOINT

170°C

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

200°C

150°C

100°C

5°C

160°C

150°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

100°C

140°C

MASS OF ASSEMBLY)

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

TIME (3 TO 7 MINUTES TOTAL)

MAX

Figure 17. Typical Solder Heating Profile

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NTD15N06L

PACKAGE DIMENSIONS

DPAK

CASE 369C−01

ISSUE O

SEATING

PLANE

−T−

INCHES

DIM MIN MAX

MILLIMETERS

MIN

5.97

6.35

2.19

0.69

0.46

0.94

MAX

6.22

6.73

2.38

0.88

0.58

1.14

0.235 0.245

0.250 0.265

0.086 0.094

0.027 0.035

0.018 0.023

0.037 0.045

0.180 BSC

0.034 0.040

0.018 0.023

0.102 0.114

0.090 BSC

4.58 BSC

0.87

0.46

2.60

1.01

0.58

2.89

2.29 BSC

0.180 0.215

0.025 0.040

4.57

0.63

0.51

0.89

3.93

5.45

1.01

−−−

1.27

−−−

0.020

0.035 0.050

0.155 −−−

−−−

D 2 PL

STYLE 2:

PIN 1. GATE

2. DRAIN

0.13 (0.005)

3. SOURCE

4. DRAIN

DPAK

CASE 369D−01

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

INCHES

DIM MIN MAX

MILLIMETERS

MIN

5.97

6.35

2.19

0.69

0.46

0.94

MAX

6.35

6.73

2.38

0.88

0.58

1.14

0.235 0.245

0.250 0.265

0.086 0.094

0.027 0.035

0.018 0.023

0.037 0.045

0.090 BSC

0.034 0.040

0.018 0.023

0.350 0.380

0.180 0.215

0.025 0.040

0.035 0.050

−T−

SEATING

PLANE

2.29 BSC

0.87

0.46

8.89

4.45

0.63

0.89

3.93

1.01

0.58

9.65

5.45

1.01

1.27

−−−

0.155

−−−

D 3 PL

STYLE 2:

PIN 1. GATE

0.13 (0.005)

2. DRAIN

3. SOURCE

4. DRAIN

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

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NTD15N06L/D

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NTD15N06L-1 [ONSEMI]

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