NTD14N03RT4 [ONSEMI]
Power MOSFET 14 Amps, 25 Volts N−Channel DPAK; 功率MOSFET 14安培， 25伏特N沟道DPAK
| 型号： | NTD14N03RT4 |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 14 Amps, 25 Volts N−Channel DPAK |
| 文件： | 总6页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTD14N03R
Power MOSFET
14 Amps, 25 Volts
N−Channel DPAK
Features
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• Planar HD3e Process for Fast Switching Performance
• Low R
to Minimize Conduction Loss
DS(on)
14 AMPERES, 25 VOLTS
• Low C to Minimize Driver Loss
iss
• Low Gate Charge
RDS(on) = 70.4 mW (Typ)
• Optimized for High Side Switching Requirements in
N−CHANNEL
D
High−Efficiency DC−DC Converters
MAXIMUM RATINGS (T = 25°C unless otherwise specified)
J
Parameter
Drain−to−Source Voltage
Symbol Value Unit
V
25
Vdc
Vdc
DSS
G
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
V
±20
GS
S
R
P
I
I
I
6.0
20.8
14
11.4
28
°C/W
W
A
A
A
q
JC
Total Power Dissipation @ T = 25°C
A
D
4
Drain Current − Continuous @ T = 25°C, Chip
A
D
− Continuous @ T = 25°C, Limited by Package
A
D
D
4
− Single Pulse (tp ≤ 10 ms)
Thermal Resistance − Junction−to−Ambient
(Note 1)
R
80
°C/W
q
JA
2
1
3
2
1
Total Power Dissipation @ T = 25°C
P
I
1.56
3.1
W
A
A
D
3
Drain Current − Continuous @ T = 25°C
A
D
CASE 369C
CASE 369D
Thermal Resistance − Junction−to−Ambient
(Note 2)
R
120
°C/W
DPAK
(Surface Mount)
DPAK
(Straight Lead)
q
JA
Total Power Dissipation @ T = 25°C
P
I
1.04
2.5
W
A
A
D
STYLE 2
STYLE 2
Drain Current − Continuous @ T = 25°C
A
D
MARKING DIAGRAM
& PIN ASSIGNMENTS
Operating and Storage Temperature Range
T , T
−55 to
150
°C
J
stg
4 Drain
4 Drain
Maximum Lead Temperature for Soldering
T
L
260
°C
Purposes, 1/8″ from case for 10 seconds
1. When surface mounted to an FR4 board using 0.5 sq. in pad size.
2. When surface mounted to an FR4 board using minimum recommended pad
size.
1
Gate
3
2
Source
1
3
Drain
Gate
Source
2
14N03 = Device Code
Drain
Y
= Year
WW
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
NTD14N03R
DPAK
75 Units/Rail
DPAK
Straight Lead
NTD14N03R−1
NTD14N03RT4
75 Units/Rail
2500 Tape & Reel
DPAK
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
October, 2003 − Rev. 3
NTD14N03R/D
NTD14N03R
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Characteristics
OFF CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage (Note 3)
V(br)
Vdc
DSS
(V = 0 Vdc, I = 250 mAdc)
25
−
28
−
−
−
GS
D
Temperature Coefficient (Positive)
mV/°C
mAdc
Zero Gate Voltage Drain Current
I
DSS
(V = 20 Vdc, V = 0 Vdc)
−
−
−
−
1.0
10
DS
GS
(V = 20 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current
(V = ±20 Vdc, V = 0 Vdc)
I
−
−
±100
nAdc
GSS
GS
DS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
V
Vdc
GS(th)
(V = V , I = 250 mAdc)
1.0
−
1.5
−
2.0
−
DS
GS
D
Threshold Temperature Coefficient (Negative)
mV/°C
mW
Static Drain−to−Source On−Resistance (Note 3)
R
DS(on)
(V = 4.5 Vdc, I = 5 Adc)
−
−
117
70.4
130
95
GS
D
(V = 10 Vdc, I = 5 Adc)
GS
D
Forward Transconductance (Note 3)
(V = 10 Vdc, I = 5 Adc)
g
Mhos
pF
FS
−
7.0
−
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
115
62
−
−
−
iss
Output Capacitance
C
oss
(V = 20 Vdc, V = 0 V, f = 1 MHz)
DS
GS
Transfer Capacitance
C
33
rss
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
t
−
−
−
−
−
−
−
3.8
27
−
−
−
−
−
−
−
ns
d(on)
t
r
(V = 10 Vdc, V = 10 Vdc,
GS
DD
I
D
= 5 Adc, R = 3 W)
G
Turn−Off Delay Time
Fall Time
t
9.6
2.0
1.8
0.8
0.7
d(off)
t
f
Gate Charge
Q
T
Q
1
Q
2
nC
(V = 5 Vdc, I = 5 Adc,
GS
D
V
DS
= 10 Vdc) (Note 3)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
SD
V
dc
(I = 5 Adc, V = 0 Vdc) (Note 3)
S
GS
−
−
0.93
0.82
1.2
−
(I = 5 Adc, V = 0 Vdc, T = 125°C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
6.6
4.75
1.88
0.002
−
−
−
−
ns
rr
t
a
(I = 5 Adc, V = 0 Vdc,
dI /dt = 100 A/ms) (Note 3)
S
S
GS
t
b
Reverse Recovery Stored Charge
Q
mC
RR
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD14N03R
14
12
10
8
14
12
10 V
8 V
5 V
V
DS
≥ 10 V
7 V
6 V
4.5 V
10
8
4 V
6
6
3.5 V
T = 25°C
J
4
2
0
4
3 V
T = 125°C
2
0
J
T = −55°C
V
= 2.5 V
J
GS
0
2
4
6
8
10
0
1
2
3
4
5
6
V
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.20
0.16
0.12
0.08
0.20
0.16
0.12
0.08
= 10 V
T = 125°C
J
GS
T = 25°C
J
T = 125°C
J
T = −55°C
J
T = 25°C
J
T = −55°C
J
0.04
0
0.04
0
V
GS
= 4.5 V
2
0
2
4
6
8
10
12
14
0
4
6
8
10
12
14
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Temperature
1000
1.8
1.6
1.4
1.2
1
V
GS
= 0 V
I
V
= 5 A
D
= 10 V
GS
T = 150°C
J
100
T = 125°C
J
0.8
0.6
10
−50 −25
0
25
50
75
100
125
150
0
5
10
15
20
25
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTD14N03R
200
160
120
80
8
T = 25°C
V
DS
= 0 V V = 0 V
GS
J
C
C
iss
6
Q
T
rss
C
C
iss
V
GS
Q
Q
2
1
4
oss
2
C
rss
40
0
I
D
= 5 A
T = 25°C
J
0
V
GS
V
DS
10
5
0
5
10
15
20
0
0.4
0.8
1.2
1.6
2.0
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
100
70
60
50
40
30
20
V
= 10 V
= 5 A
= 10 V
DS
V
GS
= 0 V
I
D
V
GS
t
r
10
t
d(off)
T = 150°C
J
t
d(on)
t
f
10
0
T = 25°C
J
1
1
10
R , GATE RESISTANCE (W)
100
0
0.2
0.4
0.6
0.8
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
G
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
6.20
3.0
0.244
0.118
2.58
0.101
5.80
1.6
6.172
0.243
0.228
0.063
mm
inches
ǒ
Ǔ
SCALE 3:1
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4
NTD14N03R
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
SEATING
−T−
PLANE
2. CONTROLLING DIMENSION: INCH.
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
L
H
0.020
0.035 0.050
0.155 −−−
−−−
D 2 PL
M
G
0.13 (0.005)
T
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
DPAK (SINGLE GAUGE)
CASE 369D
ISSUE O
SCALE 1:1
C
B
R
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
V
S
E
INCHES
DIM MIN MAX
MILLIMETERS
4
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
1
2
3
−T−
SEATING
PLANE
2.29 BSC
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D 3 PL
STYLE 2:
PIN 1. GATE
G
M
T
0.13 (0.005)
2. DRAIN
3. SOURCE
4. DRAIN
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5
NTD14N03R
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NTD14N03R/D
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