NTB85N03 [ONSEMI]
Power MOSFET 85 Amps, 28 Volts; 功率MOSFET 85安培， 28伏
| 型号： | NTB85N03 |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 85 Amps, 28 Volts |
| 文件： | 总12页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTP85N03, NTB85N03
Power MOSFET
85 Amps, 28 Volts
N−Channel TO−220 and D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
http://onsemi.com
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
85 AMPERES
28 VOLTS
RDS(on) = 6.1 mW (Typ.)
N−Channel
D
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol Value Unit
Drain−to−Source Voltage
V
28
Vdc
Vdc
DSS
Gate−to−Source Voltage
− Continuous
G
V
"20
GS
4
Drain Current
S
− Continuous @ T = 25°C
I
85*
190
Adc
Apk
C
D
4
− Single Pulse (t = 10 ms)
I
p
DM
1
2
Total Power Dissipation @ T = 25°C
P
D
80
W
C
Derate above 25°C
0.66
W/°C
3
2
Operating and Storage Temperature Range
T , T
−55
to
+150
°C
D PAK
J
stg
TO−220AB
CASE 221A
Style 5
CASE 418AA
Style 2
1
2
Single Pulse Drain−to−Source Avalanche
E
AS
733
mJ
3
Energy − Starting T = 25°C
J
MARKING DIAGRAMS
& PIN ASSIGNMENTS
(V = 28 Vdc, V = 10 Vdc, L = 5.0 mH,
DD
GS
I
= 17 A, RG = 25 W)
L(pk)
4
Thermal Resistance
°C/W
°C
4
Drain
Junction−to−Case
Junction−to−Ambient (Note 1)
R
R
1.55
70
Drain
q
JC
JA
q
Maximum Lead Temperature for Soldering
T
260
L
Purposes, 1/8″ from case for 10 seconds
NTx85N03
LLYWW
NTx85N03
LLYWW
1. When surface mounted to an FR4 board using 1″ pad size,
2
(Cu Area 1.127 in ).
*Chip current capability limited by package.
1
Gate
3
2
1
Gate
3
Source
Drain
Source
NTx85N03 = Device Code
2
x
= P or B
Drain
LL
Y
= Location Code
= Year
WW
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
NTP85N03
NTB85N03
NTB85N03T4
TO−220AB
50 Units/Rail
50 Units/Rail
2
D PAK
2
D PAK
800/Tape & Reel
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
October, 2003 − Rev. 1
NTP85N03/D
NTP85N03, NTB85N03
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
V
Vdc
mV/°C
mAdc
(BR)DSS
28
−
30.6
25
−
−
(V = 0 Vdc, I = 250 mAdc)
GS
D
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
DSS
−
−
−
−
1.0
10
(V = 28 Vdc, V = 0 Vdc)
DS
GS
(V = 28 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current (V = ±20 Vdc, V = 0 Vdc)
I
−
−
±100
nAdc
GS
DS
GSS
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage (Note 2)
V
Vdc
mV/°C
mW
GS(th)
1.0
−
1.9
−3.8
3.0
−
(V = V , I = 250 mAdc)
DS
GS
D
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 2)
R
DS(on)
−
−
−
6.1
9.2
7.0
6.8
−
−
(V = 10 Vdc, I = 40 Adc)
GS
D
(V = 4.5 Vdc, I = 40 Adc)
GS
D
(V = 10 Vdc, I = 10 Adc)
GS
D
Forward Transconductance (Note 2) (V = 15 Vdc, I = 10 Adc)
g
FS
−
20
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
2150
680
−
−
−
iss
(V = 24 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Transfer Capacitance
C
260
rss
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
t
−
−
−
−
−
−
−
10
22
32
30
29
8.0
18
−
−
−
−
−
−
−
ns
d(on)
Rise Time
t
r
(V = 15 Vdc, I = 15 Adc,
V
DD
GS
D
= 10 Vdc, R = 3.3 W)
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
Gate Charge
Q
T
Q
1
Q
2
nC
(V = 24 Vdc, I = 40 Adc,
DS
D
V
= 4.5 Vdc) (Note 2)
GS
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I = 2.3 Adc, V = 0 Vdc)
V
SD
−
−
−
0.75
1.2
0.65
1.0
−
−
Vdc
ns
S
GS
(I = 40 Adc, V = 0 Vdc) (Note 2)
S
GS
(I = 2.3 Adc, V = 0 Vdc, T = 150°C)
S
GS
J
Reverse Recovery Time
t
rr
−
−
−
−
39
21
−
−
−
−
(I = 2.3 Adc, V = 0 Vdc,
S
GS
t
a
dI /dt = 100 A/ms) (Note 2)
S
t
b
18
Reverse Recovery Stored Charge
Q
0.043
mC
RR
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
NTP85N03, NTB85N03
50
80
3.8 V
V
DS
≥ 10 V
T = 25°C
J
V
GS
= 10 V
70
60
50
40
30
20
10
0
8 V
6 V
40
30
20
10
0
3.6 V
5 V
4.5 V
T = 25°C
J
3.4 V
3.2 V
4 V
T = 100°C
J
3 V
2.8 V
T = −55°C
J
0
1
2
3
4
5
2
3
4
5
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.07
0.015
0.01
0.005
0
T = 25°C
J
I
= 10 A
D
0.06
0.05
T = 25°C
J
V
V
= 4.5 V
= 10 V
GS
0.04
0.03
0.02
0.01
0
GS
0
2
4
6
8
10
5
10
15
20
30
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
100
0.01
0.0075
0.005
0.0025
0
V
GS
= 0 V
I
V
= 40 A
D
= 10 V
DS
T = 125°C
J
T = 100°C
J
10
1
−50 −25
0
25
50
75
100
125
150
4
8
12
16
20
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
http://onsemi.com
3
NTP85N03, NTB85N03
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
5000
4500
4000
3500
3000
2500
2000
1500
1000
V
= 0
GS
T = 25°C
J
C
C
iss
oss
C
500
0
rss
−15
−10
−5
0
5
10
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Figure 7. Capacitance Variation
http://onsemi.com
4
NTP85N03, NTB85N03
12
10
8
36
1000
V
I
= 24 V
= 20 A
= 10 V
DD
t
d(off)
D
Q
30
24
18
12
6
T
V
GS
t
f
V
DS
t
r
100
10
1
V
GS
6
t
Q
Q
d(on)
gs
gd
4
I
= 15
T = 25°C
D
2
J
0
0
0
5
10
15
20
25
30
1
10
100
R , GATE RESISTANCE (W)
G
Q , TOTAL GATE CHARGE (nC)
g
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
15
V
GS
= 0 V
T = 25°C
J
12
9
6
3
0
0.1
0.3
0.5
0.7
0.9
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
exceed (T
− T )/(R ).
currents below rated continuous I can safely be assumed to
J(MAX)
C
qJC
D
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
equal the values indicated.
http://onsemi.com
5
NTP85N03, NTB85N03
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.33
8.38
0.08
2.032
0.24
0.42
10.66
6.096
0.04
1.016
0.12
3.05
0.63
17.02
inches
mm
http://onsemi.com
6
NTP85N03, NTB85N03
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
SOLDER PASTE
OPENINGS
2
and D PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 11 shows a
STENCIL
Figure 11. Typical Stencil for DPAK and
D2PAK Packages
2
typical stencil for the DPAK and D PAK packages. The
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* * Due to shadowing and the inability to set the wave
height to incorporate other surface mount components, the
2
D PAK is not recommended for wave soldering.
http://onsemi.com
7
NTP85N03, NTB85N03
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177−189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joint.
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 12 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK” ZONES 2 & 5
“RAMP”
STEP 3
HEATING
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER
JOINT
170°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
200°C
150°C
100°C
5°C
160°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 12. Typical Solder Heating Profile
http://onsemi.com
8
NTP85N03, NTB85N03
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
S
B
F
T
4
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
−−−
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
1
2
3
U
H
G
H
J
K
L
L
R
J
N
Q
R
S
T
V
G
D
U
V
Z
N
0.080
2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
http://onsemi.com
9
NTP85N03, NTB85N03
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
NOTES:
C
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
V
−B−
W
INCHES
DIM MIN MAX
MILLIMETERS
4
MIN
MAX
A
B
C
D
E
F
G
J
K
M
S
V
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.036
0.045 0.055
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
4.83
0.92
1.40
−−−
A
S
1
2
3
0.310
0.100 BSC
0.018 0.025
−−−
2.54 BSC
0.46
2.29
7.11
0.64
2.79
−−−
−T−
SEATING
PLANE
K
0.090
0.280
0.110
−−−
W
0.575 0.625 14.60 15.88
0.045 0.055 1.14 1.40
J
G
STYLE 2:
PIN 1. GATE
D 3 PL
M
M
0.13 (0.005)
T B
2. DRAIN
3. SOURCE
4. DRAIN
VARIABLE
CONFIGURATION
ZONE
U
M
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NTP85N03/D
NTP85N03, NTB85N03
http://onsemi.com
11
NTP85N03, NTB85N03
http://onsemi.com
12
相关型号：
NTB8N50
Power Field-Effect Transistor, 8A I(D), 500V, 0.75ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, D2PAK-3
MOTOROLA
©2020 ICPDF网 联系我们和版权申明