NSBA113EDXV6T1G [ONSEMI]
Dual PNP Bias Resistor Transistors;
| 型号： | NSBA113EDXV6T1G |
| 厂家： | 
ONSEMI |
| 描述： | Dual PNP Bias Resistor Transistors |
| 文件： | 总6页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MUN5130DW1,
NSBA113EDXV6
Dual PNP Bias Resistor
Transistors
R1 = 1 kW, R2 = 1 kW
http://onsemi.com
PIN CONNECTIONS
(2)
PNP Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base−emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
(3)
(1)
R
1
R
2
Q
1
Q
2
R
2
R
1
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
(4)
(5)
(6)
• S and NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
MARKING DIAGRAMS
6
SOT−363
CASE 419B
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
0G M G
Compliant
G
1
1
1
MAXIMUM RATINGS
(T = 25°C, common for Q1 and Q2, unless otherwise noted)
A
SOT−563
CASE 463A
0G M G
Rating
Collector−Base Voltage
Collector−Emitter Voltage
Collector Current − Continuous
Input Forward Voltage
Symbol
Max
50
Unit
Vdc
G
V
CBO
V
CEO
50
Vdc
0G
M
G
=
=
=
Specific Device Code
Date Code*
Pb−Free Package
I
C
100
10
mAdc
Vdc
V
IN(fwd)
(Note: Microdot may be in either location)
Input Reverse Voltage
V
IN(rev)
10
Vdc
*Date Code orientation may vary depending up-
on manufacturing location.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
†
Device
Package
Shipping
MUN5130DW1T1G
SOT−363
(Pb−Free)
3000 / Tape &
Reel
NSBA113EDXV6T1G SOT−363
(Pb−Free)
4000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
November, 2013 − Rev. 2
DTA113ED/D
MUN5130DW1, NSBA113EDXV6
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
MUN5130DW1 (SOT−363) One Junction Heated
Total Device Dissipation
P
D
T = 25°C
(Note 1)
187
256
1.5
2.0
mW
A
(Note 2)
Derate above 25°C
(Note 1)
mW/°C
(Note 2)
Thermal Resistance,
Junction to Ambient
(Note 1)
(Note 2)
R
670
490
°C/W
q
JA
MUN5130DW1 (SOT−363) Both Junction Heated (Note 3)
Total Device Dissipation
P
D
T = 25°C
(Note 1)
250
385
2.0
3.0
mW
A
(Note 2)
Derate above 25°C
(Note 1)
mW/°C
(Note 2)
Thermal Resistance,
Junction to Ambient
(Note 1)
(Note 2)
R
493
325
°C/W
°C/W
°C
q
JA
Thermal Resistance,
Junction to Lead (Note 2)
(Note 1)
R
188
208
q
JL
Junction and Storage Temperature Range
NSBA113EDXV6 (SOT−563) One Junction Heated
Total Device Dissipation
T , T
J
−55 to +150
stg
P
D
T = 25°C
(Note 1)
Derate above 25°C
357
2.9
mW
mW/°C
A
(Note 1)
Thermal Resistance,
Junction to Ambient
R
°C/W
q
JA
D
(Note 1)
350
NSBA113EDXV6 (SOT−563) Both Junction Heated (Note 3)
Total Device Dissipation
P
T = 25°C
(Note 1)
Derate above 25°C
500
4.0
mW
mW/°C
A
(Note 1)
(Note 1)
Thermal Resistance,
Junction to Ambient
R
°C/W
q
JA
250
Junction and Storage Temperature Range
T , T
−55 to +150
°C
J
stg
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0 x 1.0 Inch Pad.
3. Both junction heated values assume total power is sum of two equally powered channels.
http://onsemi.com
2
MUN5130DW1, NSBA113EDXV6
ELECTRICAL CHARACTERISTICS (T = 25°C, common for Q and Q , unless otherwise noted)
A
1
2
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Collector−Base Cutoff Current
I
I
nAdc
nAdc
mAdc
Vdc
CBO
(V = 50 V, I = 0)
−
−
−
−
−
−
−
100
500
4.3
−
CB
E
Collector−Emitter Cutoff Current
(V = 50 V, I = 0)
CEO
CE
B
Emitter−Base Cutoff Current
(V = 6.0 V, I = 0)
I
EBO
−
EB
C
Collector−Base Breakdown Voltage
(I = 10 mA, I = 0)
V
V
(BR)CBO
(BR)CEO
50
50
C
E
Collector−Emitter Breakdown Voltage (Note 4)
(I = 2.0 mA, I = 0)
Vdc
−
C
B
ON CHARACTERISTICS
DC Current Gain (Note 4)
h
FE
(I = 5.0 mA, V = 10 V)
3.0
−
5.0
−
−
0.25
−
C
CE
Collector−Emitter Saturation Voltage (Note 4)
(I = 10 mA, I = 5.0 mA)
V
Vdc
Vdc
Vdc
Vdc
Vdc
kW
CE(sat)
C
B
Input Voltage (off)
(V = 5.0 V, I = 100 mA)
V
V
i(off)
−
1.3
1.7
−
CE
C
Input Voltage (on)
(V = 0.2 V, I = 20 mA)
i(on)
−
−
CE
C
Output Voltage (on)
(V = 5.0 V, V = 2.5 V, R = 1.0 kW)
V
OL
−
0.2
CC
B
L
Output Voltage (off)
V
OH
(V = 5.0 V, V = 0.05 V, R = 1.0 kW)
4.9
0.7
0.8
−
−
CC
B
L
Input Resistor
Resistor Ratio
R1
R /R
1.0
1.0
1.3
1.2
1
2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle ≤ 2%.
400
350
300
(1) SOT−363; 1.0 x 1.0 inch Pad
250
200
150
100
(2) SOT−563; Minimum Pad
(1) (2)
50
0
−50 −25
0
25
50
75
100
125 150
AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
http://onsemi.com
3
MUN5130DW1, NSBA113EDXV6
10
1
100
I /I = 10
V
CE
= 10 V
C
B
T = 150°C
A
10
1
T = 25°C
A
T = 25°C
A
T = 150°C
A
T = −55°C
0.1
0.01
A
T = −55°C
A
0.1
0
10
20
30
40
50
0.1
1
10
100
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 2. VCE(sat) vs. IC
Figure 3. DC Current Gain
100
10
1
100
10
1
V = 0.2 V
o
T = 150°C
A
T = −55°C
A
T = 150°C
A
T = 25°C
A
T = −55°C
A
T = 25°C
V = 5 V
A
o
0.1
0.1
0
0.5
1
1.5
2
2.5
0
10
20
30
40
50
V , INPUT VOLTAGE (V)
in
I , COLLECTOR CURRENT (mA)
C
Figure 4. Output Current vs. Input Voltage
Figure 5. Input Voltage vs. Output Current
12
10
8
f = 10 kHz
I
E
= 0 V
T = 25°C
A
6
4
2
0
0
5
10
15
20
25
30
35
40
V , REVERSE VOLTAGE (V)
R
Figure 6. Output Capacitance
http://onsemi.com
4
MUN5130DW1, NSBA113EDXV6
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
2X
aaa H D
NOTES:
D
H
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
D
GAGE
PLANE
6
1
5
4
3
L
L2
E1
E
DETAIL A
2
aaa C
2X
2X 3 TIPS
bbb H D
e
MILLIMETERS
DIM MIN NOM MAX
−−−
INCHES
MIN
−−−
NOM MAX
−−− 0.043
−−− 0.004
6X b
B
A
−−−
−−−
1.10
A1 0.00
A2 0.70
0.10 0.000
M
ddd
C A-B D
TOP VIEW
0.90
0.20
0.15
2.00
2.10
1.25
0.65 BSC
0.36
1.00 0.027 0.035 0.039
0.25 0.006 0.008 0.010
0.22 0.003 0.006 0.009
2.20 0.070 0.078 0.086
2.20 0.078 0.082 0.086
1.35 0.045 0.049 0.053
0.026 BSC
b
C
D
E
0.15
0.08
1.80
2.00
A2
DETAIL A
A
E1 1.15
e
L
0.26
0.46 0.010 0.014 0.018
0.006 BSC
L2
0.15 BSC
0.15
aaa
bbb
ccc
ddd
0.006
0.012
0.004
0.004
0.30
0.10
0.10
6X
ccc C
A1
SEATING
PLANE
c
C
SIDE VIEW
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
6X
6X
0.30
0.66
2.50
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
MUN5130DW1, NSBA113EDXV6
PACKAGE DIMENSIONS
SOT−563, 6 LEAD
CASE 463A
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
D
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE MATERIAL.
A
−X−
L
6
5
2
4
3
MILLIMETERS
DIM MIN NOM MAX
INCHES
NOM MAX
E
−Y−
MIN
H
E
A
b
C
D
E
e
0.50
0.17
0.08
1.50
1.10
0.55
0.22
0.12
1.60
1.20
0.60 0.020 0.021 0.023
0.27 0.007 0.009 0.011
0.18 0.003 0.005 0.007
1.70 0.059 0.062 0.066
1.30 0.043 0.047 0.051
0.02 BSC
1
b 56 PL
C
0.5 BSC
0.20
e
M
0.08 (0.003)
X Y
L
0.10
1.50
0.30 0.004 0.008 0.012
1.70 0.059 0.062 0.066
H
1.60
E
SOLDERING FOOTPRINT*
0.3
0.0118
0.45
0.0177
1.0
0.0394
1.35
0.0531
0.5
0.5
0.0197 0.0197
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
DTA113ED/D
相关型号：
NSBA113EDXV6T5
100mA, 50V, 2 CHANNEL, PNP, Si, SMALL SIGNAL TRANSISTOR, PLASTIC, CASE 463A-01, 6 PIN
ONSEMI
NSBA113EDXV6T5G
100mA, 50V, 2 CHANNEL, PNP, Si, SMALL SIGNAL TRANSISTOR, LEAD FREE, PLASTIC, CASE 463A-01, 6 PIN
ONSEMI
NSBA114EDXV6T1
100mA, 50V, 2 CHANNEL, PNP, Si, SMALL SIGNAL TRANSISTOR, PLASTIC, CASE 463A-01, 6 PIN
ROCHESTER
NSBA114EDXV6T5
100mA, 50V, 2 CHANNEL, PNP, Si, SMALL SIGNAL TRANSISTOR, PLASTIC, CASE 463A-01, 6 PIN
ROCHESTER
©2020 ICPDF网 联系我们和版权申明