NLV74HC393ADR2G [ONSEMI]
双 4 级二进制波纹计数器;
| 型号： | NLV74HC393ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | 双 4 级二进制波纹计数器 光电二极管 逻辑集成电路 触发器 计数器 |
| 文件： | 总11页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC393A
Dual 4−Stage Binary Ripple
Counter
High−Performance Silicon−Gate CMOS
The MC74HC393A is identical in pinout to the LS393. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4−bit binary ripple counters
with parallel outputs from each counter stage. A ÷ 256 counter can be
obtained by cascading the two binary counters.
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MARKING
DIAGRAMS
14
1
Internal flip−flops are triggered by high−to−low transitions of the
clock input. Reset for the counters is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and should not be used as clocks or as strobes except
when gated with the Clock of the HC393A.
PDIP−14
N SUFFIX
CASE 646
MC74HC393AN
AWLYYWWG
14
1
14
Features
SOIC−14
D SUFFIX
CASE 751A
HC393AG
AWLYWW
14
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
1
1
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7A Requirements
• Chip Complexity: 236 FETs or 59 Equivalent Gates
• Pb−Free Packages are Available
14
HC
TSSOP−14
DT SUFFIX
CASE 948G
14
393A
ALYWG
1
G
1
14
SOEIAJ−14
F SUFFIX
CASE 965
74HC393A
ALYWG
14
1
1
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
W, WW = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006 − Rev. 4
MC74HC393A/D
MC74HC393A
PIN ASSIGNMENT
LOGIC DIAGRAM
CLOCK a
RESET a
1
2
3
4
5
6
7
14
V
3, 11
4, 10
5, 9
CC
Q1
Q2
Q3
Q4
13 CLOCK b
12 RESET b
1, 13
2, 12
BINARY
CLOCK
RESET
Q1
a
Q2
a
COUNTER
6, 8
11 Q1
b
Q3
10 Q2
a
a
b
Q4
9
8
Q3
b
b
GND
Q4
PIN 14 = V
CC
PIN 7 = GND
FUNCTION TABLE
Inputs
Clock
Reset
Outputs
X
H
L
H
L
L
L
L
L
No Change
No Change
No Change
Advance to
Next State
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC393AN
PDIP−14
25 Units / Rail
55 Units / Rail
MC74HC393ANG
PDIP−14
(Pb−Free)
SOIC−14
MC74HC393AD
MC74HC393ADG
SOIC−14
(Pb−Free)
MC74HC393ADR2
MC74HC393ADR2G
SOIC−14
SOIC−14
(Pb−Free)
2500 / Tape & Reel
2000 / Tape & Reel
MC74HC393ADTR2
MC74HC393ADTR2G
MC74HC393AFEL
MC74HC393AFELG
TSSOP−14*
TSSOP−14*
SOEIAJ−14
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HC393A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
± 20
± 25
± 50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
6.0
V , V
in out
DC Input Voltage, Output Voltage (Referenced to
GND)
V
CC
V
T
Operating Temperature, All Package Types
– 55
+ 125
_C
ns
A
t , t
r
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
V
CC
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
f
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
1.5
2.1
3.15
4.2
V
v 85_C
v 125_C
Symbol
Parameter
Test Conditions
= 0.1 V or V – 0.1 V
|I | v 20 mA
Unit
V
IH
Minimum High−Level Input
V
2.0
3.0
4.5
6.0
1.5
2.1
1.5
2.1
V
out
CC
Voltage
out
3.15
4.2
3.15
4.2
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V – 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
V
V
IL
out
CC
|I | v 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IH
|I | v 20 mA
out
V
in
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
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3
MC74HC393A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
0.1
0.1
0.1
v 85_C
0.1
0.1
0.1
v 125_C
V
Symbol
Parameter
Test Conditions
= V or V
|I | v 20 mA
out
Unit
V
OL
Maximum Low−Level Output
V
in
2.0
4.5
6.0
0.1
0.1
0.1
V
IH
IL
Voltage
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
in
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
I
Maximum Input Leakage Current
V
V
= V or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
mA
mA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
4
40
160
CC
in
CC
I
= 0 mA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
25_C
10
15
30
50
V
v 85_C
v 125_C
Symbol
Parameter
Unit
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
9
8
MHz
max
14
28
45
12
25
40
t
t
t
t
,
Maximum Propagation Delay, Clock to Q1
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
24
20
80
45
30
26
90
50
36
31
ns
ns
ns
ns
ns
ns
pF
PLH
t
PHL
,
Maximum Propagation Delay, Clock to Q2
(Figures 1 and 3)
2.0
3.0
4.5
6.0
100
56
34
105
70
45
180
100
55
PLH
t
PHL
20
38
48
,
Maximum Propagation Delay, Clock to Q3
(Figures 1 and 3)
2.0
3.0
4.5
6.0
130
80
44
150
105
55
180
130
70
PLH
t
PHL
37
47
58
,
Maximum Propagation Delay, Clock to Q4
(Figures 1 and 3)
2.0
3.0
4.5
6.0
160
110
52
250
185
65
300
210
82
PLH
t
PHL
44
55
65
t
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
3.0
4.5
6.0
80
48
30
26
95
65
38
33
110
75
50
PHL
43
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
TLH
THL
19
C
Maximum Input Capacitance
—
10
10
10
in
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
35
C
Power Dissipation Capacitance (Per Counter)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
. For load considerations, see Chapter 2 of the
D
PD CC
CC CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
MC74HC393A
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
– 55 to
V
CC
25_C
25
15
10
9
V
v 85_C
30
20
13
11
v 125_C
Symbol
Parameter
Unit
t
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
40
30
15
13
ns
rec
t
t
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
ns
ns
ns
w
19
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
w
19
t , t
r
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
f
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
PIN DESCRIPTIONS
INPUTS
Clock (Pins 1, 13)
Clock input. The internal flip−flops are toggled and the
counter state advances on high−to−low transitions of the
clock input.
OUTPUTS
Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)
Parallel binary outputs Q4 is the most significant bit.
CONTROL INPUTS
Reset (Pins 2, 12)
Active−high, asynchronous reset. A separate reset is
provided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.
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5
MC74HC393A
SWITCHING WAVEFORMS
t
t
r
f
t
w
V
CC
90%
50%
10%
V
CC
RESET
50%
CLOCK
GND
GND
t
w
t
PHL
1/f
max
t
t
PHL
50%
PLH
Q
90%
50%
10%
t
rec
Q
V
CC
50%
CLOCK
GND
t
t
THL
TLH
Figure 1.
Figure 2.
EXPANDED LOGIC DIAGRAM
TEST
POINT
1, 13
CLOCK
C
C
C
C
Q
Q
OUTPUT
3, 11
4, 10
DEVICE
UNDER
TEST
D
D
D
D
Q1
Q2
C *
L
Q
Q
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Q
Q
5, 9
Q3
Q4
Q
Q
6, 8
2, 12
RESET
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6
MC74HC393A
TIMING DIAGRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
CLOCK
RESET
Q1
Q2
Q3
Q4
COUNT SEQUENCE
Outputs
Q4
Q3
Q2
Q1
Count
0
1
2
3
4
5
6
7
8
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
L
L
L
L
H
H
H
H
L
H
H
L
9
L
10
11
12
13
14
15
H
H
L
L
H
H
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7
MC74HC393A
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
J
_
_
K
0.015
0.039
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
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8
MC74HC393A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MC74HC393A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
MILLIMETERS
INCHES
K1
DIM MIN
MAX
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
0.15 0.002 0.006
0.75 0.020 0.030
J J1
−−− 0.047
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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10
MC74HC393A
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
14
8
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN
−−−
VIEW P
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
e
A
−−−
0.05
0.35
0.10
9.90
5.10
2.05
c
A
1
b
c
0.20 0.002
0.50 0.014
0.20 0.004
D
E
e
10.50 0.390
5.45 0.201
A
b
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
0.13 (0.005)
E
0.10 (0.004)
0.50
L
E
M
0
10
0.90 0.028
10
_
0.035
0.056
0
_
_
_
Q
1
0.70
−−−
Z
1.42
−−−
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