NLSX4014_15 [ONSEMI]
4-Bit 100 Mb/s Configurable Dual-Supply Level Translator;
| 型号： | NLSX4014_15 |
| 厂家： | 
ONSEMI |
| 描述： | 4-Bit 100 Mb/s Configurable Dual-Supply Level Translator |
| 文件： | 总13页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLSX4014
4-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX4014 is a 4−bit configurable dual−supply bidirectional
level translator without a direction control pin. The I/O V − and I/O
www.onsemi.com
MARKING
CC
V −ports are designed to track two different power supply rails, V
L
CC
and V respectively. The V supply rail is configurable from 1.3 V
L
CC
DIAGRAMS
to 4.5 V while the V supply rail is configurable from 0.9 V to (V
L
CC
− 0.4) V. This allows lower voltage logic signals on the V side to be
L
UQFN12
MU SUFFIX
CASE 523AE
WAMG
translated into higher voltage logic signals on the V
side, and
CC
G
vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3−state. This significantly reduces the supply
1
WA = Specific Device Code
M
G
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
currents from both V and V . The EN signal is designed to track
CC
L
V .
L
14
SOIC−14
D SUFFIX
CASE 751A
Features
NLSX4014G
AWLYWW
14
• Wide High−Side V Operating Range: 1.3 V to 4.5 V
CC
1
Wide Low−Side V Operating Range: 0.9 V to (V − 0.4) V
L
CC
1
• Power Supply Isolation
♦ All Outputs are in the High Impedance State if Either V or V
L
CC
14
is at Ground
NLSX
4014
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
14
• High−Speed with 100 Mb/s Guaranteed Date Rate for V > 1.6 V
• Low Bit−to−Bit Skew
L
1
1
• Overvoltage Tolerant Enable and I/O Pins
• Non−preferential Powerup Sequencing
• Small packaging: 1.7 mm x 2.0 mm UQFN12
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
A
L, WL
Y, YY
W, WW
G or G
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
• These are Pb−Free Devices
ORDERING INFORMATION
Typical Applications
†
Device
NLSX4014MUTAG
Package
Shipping
• Mobile Phones, PDAs, Other Portable Devices
UQFN12 3000/Tape & Reel
(Pb−Free)
NLVSX4014MUTAG UQFN12 3000/Tape & Reel
(Pb−Free)
NLSX4014DR2G
SO−14
2500/Tape & Reel
(Pb−Free)
NLSX4014DTR2G
TSSOP14 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
December, 2015 − Rev. 5
NLSX4014/D
NLSX4014
V
EN
1
2
3
4
5
6
7
14
13
L
EN
12
I/O V 1
V
CC
L
V
V
L
1
2
3
4
5
11
10
9
CC
I/O V 1
I/O V 2
12 I/O V
1
CC
I/O V
1
CC
L
L
I/O V 2
L
I/O V
I/O V
2
3
CC
11
10
9
I/O V 3
I/O V
I/O V
2
CC
3
CC
L
I/O V 3
L
8
CC
I/O V 4
L
6
7
I/O V
4
CC
I/O V 4
L
NC
NC
GND
(Top View)
8
GND
I/O V
4
CC
Figure 1. Pin Assignments
V
L
V
CC
GND
EN
I/O V 1
I/O V 1
CC
L
I/O V 2
I/O V
I/O V
2
3
L
CC
I/O V 3
L
CC
I/O V 4
I/O V 4
CC
L
Figure 2. Logic Diagram
PIN ASSIGNMENT
Pins
FUNCTION TABLE
Description
EN
L
Operating Mode
V
V
V
Input Voltage
Hi−Z
CC
CC
V Input Voltage
L
H
I/O Buses Connected
L
GND
EN
Ground
Output Enable
I/O V
n
I/O Port, Referenced to V
I/O Port, Referenced to V
CC
CC
I/O V n
L
L
www.onsemi.com
2
NLSX4014
P
V
L
V
CC
One−Shot
+1.8V
+3.6V
4 kW
V
L
V
CC
NLSX4014
N
+1.8 V System
+3.6 V System
I/O1
One−Shot
I/O V
I/O V
CC
L
I/O V 1 I/O V
1
I/O1
L
CC
P
I/On
I/O V n I/O V
n
I/On
L
CC
One−Shot
GND EN
EN
GND
GND
4 kW
N
One−Shot
Figure 3. Typical Application Circuit
Figure 4. Simplified Functional Diagram (1 I/O Line)
(EN = 1)
www.onsemi.com
3
NLSX4014
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
V
V
V
V
Supply Voltage
−0.5 to +5.5
−0.5 to +5.5
CC
CC
V Supply Voltage
L
V
L
I/O V
I/O V
V
−Referenced DC Input/Output Voltage
−0.5 to (V + 0.3)
V
CC
CC
CC
V −Referenced DC Input/Output Voltage
L
−0.5 to (V + 0.3)
V
L
L
V
Enable Control Pin DC Input Voltage
Input Diode Clamp Current
−0.5 to +5.5
−50
V
EN
I
I
I
I
I
V < GND
mA
mA
mA
mA
mA
°C
IK
I
Output Diode Clamp Current
−50
V < GND
O
OK
CC
L
DC Supply Current Through V
$100
CC
DC Supply Current Through V
$100
L
DC Ground Current Through Ground Pin
Storage Temperature
$100
GND
T
STG
−65 to +150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.3
Max
Unit
V
V
CC
V
CC
Supply Voltage
4.5
V
L
V Supply Voltage
L
0.9
V − 0.4
CC
V
V
Enable Control Pin Voltage
Bus Input/Output Voltage
GND
4.5
V
EN
V
I/O V
I/O V
GND
GND
4.5
4.5
V
IO
CC
L
T
Operating Temperature Range
Input Transition Rise or Rate
−40
0
+85
10
°C
A
DI/DV
ns
V , V from 30% to 70% of V ; V = 3.3 V $ 0.3 V
I
IO
CC CC
Functionaloperation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
RecommendedOperating Ranges limits may affect device reliability.
www.onsemi.com
4
NLSX4014
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Typ
Test Conditions
V
CC
(V)
V (V)
L
(Note 4)
(Note 1)
(Note 2)
(Note 3)
Min
Max
Symbol
Parameter
Unit
V
I/O V Input HIGH
Voltage
1.3 to 4.5 0.9 to (V – 0.4)
0.8 *
−
−
−
V
IHC
CC
CC
V
CC
V
V
I/O V Input LOW
1.3 to 4.5 0.9 to (V – 0.4)
−
0.2 *
V
V
V
V
V
V
V
V
V
ILC
CC
CC
Voltage
V
CC
I/O V Input HIGH
1.3 to 4.5 0.9 to (V – 0.4) 0.8 * V
−
−
−
−
−
−
−
−
−
0.2 * V
−
IHL
L
CC
L
Voltage
V
I/O V Input LOW
1.3 to 4.5 0.9 to (V – 0.4)
−
ILL
L
CC
L
Voltage
V
Control Pin Input HIGH
Voltage
T = +25°C
1.3 to 4.5 0.9 to (V – 0.4) 0.8 * V
CC
IH
A
L
V
Control Pin Input LOW
Voltage
T = +25°C
A
1.3 to 4.5 0.9 to (V – 0.4)
−
0.2 * V
−
IL
CC
L
V
OHC
I/O V Output HIGH
I/O V Source Current =
1.3 to 4.5 0.9 to (V – 0.4)
0.8 *
CC
CC
CC
Voltage
20 mA
V
CC
V
I/O V Output LOW
I/O V Sink Current = 20 mA 1.3 to 4.5 0.9 to (V – 0.4)
−
0.2 *
OLC
OHL
CC
CC
CC
Voltage
V
CC
V
I/O V Output HIGH
I/O V Source Current = 20 mA 1.3 to 4.5 0.9 to (V – 0.4) 0.8 * V
−
L
L
CC
L
Voltage
V
OLL
I/O V Output LOW
I/O V Sink Current = 20 mA
1.3 to 4.5 0.9 to (V – 0.4)
−
0.2 * V
L
L
CC
L
Voltage
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performancemay not be indicated by the Electrical Characteristics if operated under different conditions.
1. Normal test conditions are V = 0 V, C
= 15 pF and C
= 15 pF, unless otherwise specified.
EN
IOVCC
IOVL
2. V is the supply voltage associated with the high voltage port, and V ranges from +1.3 V to 4.5 V under normal operating conditions.
CC
CC
3. V is the supply voltage associated with the low voltage port. V must be less than or equal to (V – 0.4) V during normal operation. However,
L
L
CC
during startup and shutdown conditions, V can be greater than (V – 0.4) V.
L
CC
4. Typical values are for V = +2.8 V, V = +1.8 V and T = +25°C. All units are production tested at T = +25°C. Limits over the operating
CC
L
A
A
temperaturerange are guaranteed by design.
www.onsemi.com
5
NLSX4014
POWER CONSUMPTION
−405C to +855C
Test Conditions
V
(V)
V (V)
(Note 7)
CC
L
(Note 5)
(Note 6)
Min
Typ
Max
Symbol
Parameter
Unit
I
Supply Current from EN = V I/O V
= 0 V, I/O V = 0 V, 1.3 to 3.6 0.9 to (V – 0.4)
−
−
1.0
2.0
2.0
1.0
mA
Q−VCC
L;
CCn
Ln
CC
V
CC
I/O V = V or I/O V = V and I = 0
CCn CC Ln L o
0
4.1
−
−
−
−
4.5
0
−
I
Supply Current from EN = V I/O V
= 0 V, I/O V = 0 V, 1.3 to 3.6 0.9 to (V – 0.4)
−
mA
Q−VL
L;
CCn
Ln
CC
V
L
I/O V = V or I/O V = V and I = 0
CCn CC Ln L o
< (V – 0.2)
CC
EN = V , I/O V
= 0 V, I/O V = 0 V,
Ln
L
CCn
0
4.1
0
I/O V
= V or I/O V = (V
−
−
−
−
−
2.0
1.0
CCn
CC
Ln
CC
0.2 V) and I = 0
o
4.5
I
V
Tristate Output
EN = 0 V
1.3 to 3.6 0.9 to (V – 0.4)
mA
mA
mA
TS−VCC
CC
CC
Mode Supply
Current
I
V Tristate Output
EN = 0 V
EN = 0 V
EN = 0 V
EN = 0 V
−
1.3 to 3.6 0.9 to (V – 0.4)
−
−
−
−
−
−
−
−
−
−
0.2
2.0
TS−VL
L
CC
Mode Supply
Current
V
CC
− 0.2
I
I
I/O Tristate Output
Mode Leakage
Current
1.3 to 3.6 0.9 to (V – 0.4)
0.15
2.0
OZ
EN
CC
V
CC
– 0.2
Output Enable Pin
Input Current
1.3 to 3.6 0.9 to (V – 0.4)
1.0
mA
mA
CC
I
V Port
L
I/O V = 0 to 4.1 V
0 to 4.5
0
0
−
−
−
−
2.0
2.0
OFF
Ln
V
CC
Port
I/O V
= 0 to 4.5 V
0 to 4.1
CCn
5. Normal test conditions are V = 0 V, C
= 15 pF and C
= 15 pF, unless otherwise specified.
EN
IOVCC
IOVL
6. V is the supply voltage associated with the high voltage port, and V ranges from +1.3 V to 3.6 V.
CC
CC
7. V is the supply voltage associated with the low voltage port. V must be less than or equal to (V – 0.4) V during normal operation. However,
L
L
CC
during startup and shutdown conditions, V can be greater than (V – 0.4) V.
L
CC
www.onsemi.com
6
NLSX4014
TIMING CHARACTERISTICS
−405C to +855C
Typ
Test Conditions
V
CC
(V)
V (V)
L
(Note 11)
(Note 8)
(Note 9)
(Note 10)
Min
Max
Symbol
Parameter
I/O V Rise Time
Unit
t
C
C
= 15 pF
= 15 pF
= 15 pF
= 15 pF
1.3 to 4.5 0.9 to (V – 0.4)
0.7
2.4
ns
R−VCC
CC
IOVCC
CC
(Output = I/O_V
)
CC
t
I/O V Falltime
1.3 to 4.5 0.9 to (V – 0.4)
0.5
1.0
0.6
30
1.0
3.8
1.2
ns
ns
ns
W
F−VCC
CC
IOVCC
CC
(Output = I/O_V
)
CC
t
I/O V Risetime
C
1.3 to 4.5 0.9 to (V – 0.4)
CC
R−VL
L
IOVL
(Output = I/O_V )
L
t
I/O V Falltime
C
1.3 to 4.5 0.9 to (V – 0.4)
CC
F−VL
L
IOVL
(Output = I/O_V )
L
Z
I/O V One−Shot
1.3 to 4.5 0.9 to (V – 0.4)
CC
O−VCC
CC
Output Impedance
Z
O−VL
I/O V One−Shot
Output Impedance
1.3 to 4.5 0.9 to (V – 0.4)
30
W
L
CC
t
t
Propagation Delay
C
= 15 pF
= 15 pF
= 15 pF
= 15 pF
1.3 to 4.5 0.9 to (V – 0.4)
4.5
9.3
6.5
0.3
0.3
ns
PD_VL−VCC
IOVCC
CC
(Output = I/O_V
,
CC
t
, t
)
PHL PLH
Propagation Delay
(Output = I/O_V ,
C
1.3 to 4.5 0.9 to (V – 0.4)
3.0
0.2
0.2
ns
nS
PD_VCC−VL
IOVL
CC
L
t
, t
)
PHL PLH
t
Channel−to−Channel
Skew (Output =
C
1.3 to 4.5 0.9 to (V – 0.4)
CC
SK VL−VCC
IOVCC
IOVCC
I/O_V )
CC
t
Channel−to−Channel
Skew
C
1.3 to 4.5 0.9 to (V – 0.4)
nS
SK_VCC−VL
CC
(Output = I/O_V )
L
MDR
Maximum Data Rate
(Output = I/O_V
,
1.3 to 4.5 0.9 to (V – 0.4)
110
140
Mb/s
CC
CC
C
IOVCC
= 15 pF)
(Output = I/O_V ,
L
> 2.2
> 1.8
C
IOVL
= 15 pF)
8. Normal test conditions are V = 0 V, C
= 15 pF and C
IOVL
= 15 pF, unless otherwise specified.
EN
IOVCC
9. V is the supply voltage associated with the high voltage port, and V ranges from +1.3 V to 4.5 V under normal operating conditions.
CC
CC
10.V is the supply voltage associated with the low voltage port. V must be less than or equal to (V – 0.4) V during normal operation. However,
L
L
CC
during startup and shutdown conditions, V can be greater than (V – 0.4) V.
L
CC
11. Typical values are for V = +2.8 V, V = +1.8 V and T = +25°C. All units are production tested at T = +25°C. Limits over the operating
CC
L
A
A
temperaturerange are guaranteed by design.
www.onsemi.com
7
NLSX4014
ENABLE / DISABLE TIME MEASUREMENTS
−405C to +855C
Typ
Test Conditions
V
CC
(V)
V (V)
L
(Note 15)
(Note 12)
(Note 13)
(Note 14)
Min
Max
Symbol
Parameter
Unit
t
Turn−On Enable Time (Output =
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 15 pF
1.3 to 4.5 0.9 to (V – 0.4)
130
180
ns
EN−VCC
IOVCC
CC
I/O_V , t
)
CC pZH
Turn−On Enable Time (Output =
I/O_V , t
C
IOVL
1.3 to 4.5 0.9 to (V – 0.4)
100
95
150
185
110
250
190
250
220
ns
ns
ns
ns
ns
ns
ns
CC
)
CC pZL
t
Turn−On Enable Time (Output =
I/O_V , t
1.3 to 4.5 0.9 to (V – 0.4)
CC
EN−VL
IOVCC
)
pZH
L
Turn−On Enable Time (Output =
I/O_V , t
C
IOVL
1.3 to 4.5 0.9 to (V – 0.4)
70
CC
)
pZL
L
t
Turn−Off Disable Time (Output =
I/O_V , t
1.3 to 4.5 0.9 to (V – 0.4)
175
150
180
160
DIS−VCC
IOVCC
CC
)
CC pHZ
Propagation Delay (Output =
I/O_V , t
C
IOVL
1.3 to 4.5 0.9 to (V – 0.4)
CC
)
CC PLZ
t
Turn−Off Disable Time (Output =
I/O_V , t
1.3 to 4.5 0.9 to (V – 0.4)
CC
DIS−VL
IOVCC
)
pHZ
L
Propagation Delay (Output = I/O_V ,
C
1.3 to 4.5 0.9 to (V – 0.4)
L
IOVL
CC
t
)
PLZ
12.Normal test conditions are V = 0 V, C
= 15 pF and C = 15 pF, unless otherwise specified.
IOVL
EN
IOVCC
13.V is the supply voltage associated with the high voltage port, and V ranges from +1.3 V to 4.5 V under normal operating conditions.
CC
CC
14.V is the supply voltage associated with the low voltage port. V must be less than or equal to (V – 0.4) V during normal operation. However,
L
L
CC
during startup and shutdown conditions, V can be greater than (V – 0.4) V.
L
CC
15.Typical values are for V = +2.8 V, V = +1.8 V and T = +25 °C. All units are production tested at T = +25 °C. Limits over the operating
CC
L
A
A
temperature range are guaranteed by design.
NLSX4014
NLSX4014
V
L
V
CC
V
L
V
CC
EN
EN
I/O V
I/O V
L
I/O V
L
I/O V
CC
CC
Source
C
IOVL
C
IOVCC
Source
t
v
I/O V
t
RISE/FALL
v 3 ns
RISE/FALL
I/O V
CC
L
3 ns
90%
50%
10%
90%
50%
10%
t
L
t
t
t
PD_VCC−VL
PD_VCC−VL
PD_VL−VCC
PD_VL−VCC
I/O V
I/O V
CC
90%
50%
10%
90%
50%
10%
t
t
R−VCC
t
t
R−VL
F−VCC
F−VL
Figure 5. Driving I/O VL Test Circuit and Timing
Figure 6. Driving I/O VCC Test Circuit and Timing
www.onsemi.com
8
NLSX4014
V
CC
2xV
CC
OPEN
R
1
PULSE
GENERATOR
DUT
R
T
C
L
R
L
Test
Switch
t
t
, t
Open
PZH PHZ
, t
2 x V
CC
PZL PLZ
C = 15 pF or equivalent (Includes jig and probe capacitance)
L
R = R = 50 kW or equivalent
L
1
OUT
R = Z
T
of pulse generator (typically 50 W)
Figure 7. Test Circuit for Enable/Disable Time Measurement
t
t
F
V
R
L
50%
EN
V
CC
90%
50%
10%
Input
GND
GND
t
t
PLZ
PZL
t
t
PHL
PLH
HIGH
90%
50%
IMPEDANCE
50%
Output
Output
10%
90%
V
OL
10%
t
t
PHZ
PZH
t
t
F
V
OH
R
50%
Output
HIGH
IMPEDANCE
Figure 8. Timing Definitions for Propagation Delays and Enable/Disable Measurement
www.onsemi.com
9
NLSX4014
IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture
Uni−Directional versus Bi−Directional Translation
The NLSX4014 can function as a non−inverting
uni−directional translator. One advantage of using the
translator as a uni−directional device is that each I/O pin
can be configured as either an input or output. The
configurable input or output feature is especially useful in
applications such as SPI that use multiple uni−directional
I/O lines to send data to and from a device. The flexible I/O
port of the auto sense translator simplifies the trace
connections on the PCB.
The NLSX4014 auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, V and V , which set the logic levels on
L
CC
the input and output sides of the translator. When used to
transfer data from the V to the V ports, input signals
L
CC
referenced to the V supply are translated to output signals
L
with a logic level matched to V . In a similar manner, the
CC
V
CC
to V translation shifts input signals with a logic level
L
compatible to V to an output signal matched to V .
CC
L
Power Supply Guidelines
It is recommended that the V supply should be less than
or equal to the value of the V
sequencing of the power supplies will not damage the
device during the power up operation; however, the current
The NLSX4014 consists of four bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for high−to−low and low−to−high transitions.
L
minus 0.4 V. The
CC
consumption of the device will increase if V exceeds V
minus 0.4 V. In addition, the I/O V and I/O V pins are
L
CC
CC
L
Input Driver Requirements
in the high impedance state if either supply voltage is equal
to 0 V.
For optimal performance, 0.01 to 0.1 mF decoupling
For proper operation, the input driver to the auto sense
translator should be capable of driving 2.0 mA of peak
output current.
capacitors should be used on the V and V power supply
L
CC
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the power supply voltage
lines to the ground plane of the PCB. The noise immunity
will be maximized by placing the capacitors as close as
possible to the supply and ground pins, along with
minimizing the PCB connection traces.
Output Load Requirements
The NLSX4014 is designed to drive CMOS inputs.
Resistive pullup or pulldown loads of less than 50 kW
should not be used with this device. The NLSX3373 or
NLSX3378 open−drain auto sense translators are alternate
translator options for an application such as the I C bus that
requires pullup resistors.
2
The NLSX4014 provides power supply isolation if either
supply voltage V or V is equal to 0 V. The isolation
L
CC
occurs because the I/O pins are in the high impedance state.
It is recommended that pulldown resistors should be used
Enable Input (EN)
The NLSX4014 has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the device and drives the I/O V and I/O V pins to a high
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
if the V or V are floated or in a high impedance state.
L
CC
A pulldown resistor connected from the supply voltage to
ground ensures that the translator’s supply voltage is equal
to 0 V.
CC
L
is referenced to the V supply and has Over−Voltage
L
Tolerant (OVT) protection.
www.onsemi.com
10
NLSX4014
PACKAGE DIMENSIONS
UQFN12 1.7x2.0, 0.4P
CASE 523AE
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
D
A B
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
L1
PIN 1 REFERENCE
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH 0.03
MAX ON BOTTOM SURFACE OF
TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
DETAIL A
E
NOTE 5
0.10
0.10
C
C
2X
2X
MILLIMETERS
TOP VIEW
DIM MIN
MAX
0.55
0.05
A
A1
A3
b
0.45
0.00
0.127 REF
DETAIL B
A
0.15
0.25
0.05
0.05
C
DETAIL B
OPTIONAL
CONSTRUCTION
D
1.70 BSC
2.00 BSC
0.40 BSC
E
e
12X
C
K
0.20
----
0.55
0.03
A1
SEATING
PLANE
C
L
0.45
0.00
0.15 REF
A3
SIDE VIEW
L1
L2
8X
K
5
1
7
DETAIL A
12X L
e
MOUNTING FOOTPRINT
SOLDERMASK DEFINED
2.00
11
12X
b
1
L2
M
M
C
C
A B
0.10
0.05
BOTTOM VIEW
NOTE 3
0.40
0.32
PITCH
2.30
11X
0.22
12X
0.69
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
www.onsemi.com
11
NLSX4014
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C
A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
www.onsemi.com
12
NLSX4014
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X K REF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
−U−
L
N
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
K1
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
0.65 BSC
0.50
0.09
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
J1 0.09
0.19
K
0.10 (0.004)
K1 0.19
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
DETAIL E
D
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent− Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in
SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products
are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products
for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against
all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended
or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your loca
Sales Representative
NLSX4014/D
相关型号：
©2020 ICPDF网 联系我们和版权申明