NFVA23512NP2T [ONSEMI]
Intelligent Power Module (IPM), AEC-Q & AQG324, Automotive, Inverter 1200V, 35A;
| 型号： | NFVA23512NP2T |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Power Module (IPM), AEC-Q & AQG324, Automotive, Inverter 1200V, 35A 电动机控制 |
| 文件： | 总15页 (文件大小：752K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASPM34 Series
Automotive 3−Phase 1200 V, 35 A IGBT
Intelligent Power Module
NFVA23512NP2T
General Description
NFVA23512NP2T is an advanced Auto IPM module providing a
fully−featured, high−performance inverter output stage for hybrid and
electric vehicles. These modules integrate optimized gate drive of the
built−in IGBTs to minimize EMI and losses, while also providing
multiple on−module protection features including under−voltage
lockouts, over−current shutdown, thermal monitoring of drive IC, and
fault reporting. The built−in, high−speed HVIC requires only a single
supply voltage and translates the incoming logic−level gate inputs to
the high−voltage, high−current drive signals required to properly drive
the module’s internal IGBTs. Separate negative IGBT terminals are
available for each phase to support the widest variety of control
algorithms.
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Features
®
• Automotive SPM in 34 pin DIP package
• AEC & AQG324 Qualified and PPAP Capable
• 1200 V − 35 A 3−Phase IGBT Inverter with Integral Gate Drivers
and Protection
3D Package Drawing
(Click to Activate 3D Content)
• Low−Loss, Short−Circuit Rated IGBTs
• Very Low Thermal Resistance using Al O DBC Substrate
2
3
DIP34 80x33, AUTOMOTIVE MODULE
CASE MODGL
• Built−In Bootstrap Diodes and Dedicated Vs Pins Simplify PCB
Layout
• Separate Open−Emitter Pins from Low−Side IGBTs for Three−Phase
Current Sensing
MARKING DIAGRAM
• Single−Grounded Power Supply Supported
• Built−In NTC Thermistor for Temperature Monitoring and
Management
• Adjustable Over−Current Protection via Integrated Sense−IGBTs
• Isolation Rating of 2500 Vrms/1 min
• This is a Pb−Free Device
Applications
• Automotive High Voltage Auxiliary Motors
♦ Climate e−Compressors
♦ Oil/Water Pumps
XXXXXXXXXXXX = Specific Device Code
ZZZ
AT
Y
= Lot ID
= Assembly & Test Location
= Year
♦ Super/Turbo Chargers
♦ Variety Fans
W
NNN
= Work Week
= Serial Number
• Motion Control
♦ Industrial Motor
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
Related Resources
®
• AN−9075 − Users Guide for 1200V SPM 2 Series
®
• AN−9076 − Mounting Guide for New SPM 2 Package
®
• AN−9079 − Thermal Performance of 1200V Motion SPM 2 Series
by Mounting Torque
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
December, 2019 − Rev. 4
NFVA23512NP2T/D
NFVA23512NP2T
Integrated Power Functions
• For inverter low−side IGBTs: gate drive circuit,
Short−Circuit Protection (SCP) control supply circuit,
Under−Voltage Lock−Out Protection (UVLO)
• Fault signaling: corresponding to UVLO (low−side
supply) and SC faults
• 1200 V−35 A IGBT inverter for three−phase DC/AC
power conversion (Refer to Figure 1)
Integrated Drive, Protection and System Control
Functions
• For inverter high−side IGBTs: gate drive circuit,
high−voltage isolated high−speed level shifting control
circuit, Under−Voltage Lock−Out Protection (UVLO)
• Input interface: active−high interface, works with 3.3/5
V logic, schmitt−trigger input
PIN CONFIGURATION
(34) VS(W)
(33) VB(W)
(32) VBD(W)
(31) VDD(WH)
(1) P
(30) IN
(WH)
(29) VS(V)
(28) VB(V)
(2) W
(3) V
(27) VBD(V)
(26) VDD(VH)
(25) IN
(VH)
(24) VS(U)
(23) VB(U)
Case Temperature (T )
Detecting Point
C
(22) VBD(U)
(21) VDD(UH)
(20) COM
(H)
(4) U
(19) IN
(UH)
(18) RSC
(17) CSC
(5) NW
(6) NV
(7) NU
(16) CFOD
(15) VFO
(14) IN
(WL)
(13) IN
(VL)
(12) IN
(UL)
(8) RTH
(9) VTH
(11) COM(L)
(10) VDD(L)
Figure 1. Top View
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2
NFVA23512NP2T
PIN DESCRIPTIONS
Pin Number
Pin Name
Pin Description
1
2
P
W
V
Positive DC−Link Input
Output for W Phase
3
Output for V Phase
4
U
Output for U Phase
5
N
Negative DC−Link Input for W Phase
Negative DC−Link Input for V Phase
Negative DC−Link Input for U Phase
W
6
N
V
U
7
N
8
R
V
Series Resistor for Thermistor (Temperature Detection)
Thermistor Bias Voltage
TH
9
TH
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
V
Low−Side Bias Voltage for IC and IGBTs Driving
Low−Side Common Supply Ground
DD(L)
COM
(L)
(UL)
IN
IN
Signal Input for Low−Side U Phase
Signal Input for Low−Side V Phase
(VL)
IN
Signal Input for Low−Side W Phase
(WL)
V
Fault Output
FO
C
Capacitor for Fault Output Duration Selection
Shut Down Input for Short−Circuit Current Detection Input
Resistor for Short−Circuit Current Detection
Signal Input for High−Side U Phase
FOD
C
SC
SC
R
IN
(UH)
COM
High−Side Common Supply Ground
(H)
V
High−Side Bias Voltage for U Phase IC
DD(UH)
V
BD(U)
Anode of Bootstrap Diode for U Phase High−Side Bootstrap Circuit
High−Side Bias Voltage for U Phase IGBT Driving
High−Side Bias Voltage Ground for U Phase IGBT Driving
Signal Input for High−Side V Phase
V
B(U)
V
S(U)
IN
(VH)
V
High−Side Bias Voltage for V Phase IC
DD(VH)
V
BD(V)
Anode of Bootstrap Diode for V Phase High−Side Bootstrap Circuit
High−Side Bias Voltage for V Phase IGBT Driving
High−Side Bias Voltage Ground for V Phase IGBT Driving
Signal Input for High−Side W Phase
V
B(V)
S(V)
(WH)
V
IN
V
High−Side Bias Voltage for W Phase IC
DD(WH)
V
BD(W)
Anode of Bootstrap Diode for W Phase High−Side Bootstrap Circuit
High−Side Bias Voltage for W Phase IGBT Driving
High−Side Bias Voltage Ground for W Phase IGBT Driving
V
B(W)
V
S(W)
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3
NFVA23512NP2T
INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS
P (1)
(33) VB(W)
VB
(32) VBD(W)
(31) VDD(WH)
OUT
V S
VDD
COM
IN
HVIC
HVIC
(30) IN(WH)
(34) VS(W)
W (2)
(28) VB(V)
(27) VBD(V)
(26) VDD(VH)
VB
VDD
OUT
VS
COM
IN
(25) IN(VH)
(29) VS(V)
V (3)
(23) VB(U)
VB
(22) V BD(U)
(21) V DD(UH)
VDD
COM
IN
OUT
VS
HVIC
(H)
(20) COM
(19) IN(UH)
(24) VS(U)
U (4)
CSC
CFOD
VFO
OUT
OUT
OUT
(17) CSC
(16) CFOD
(15) VFO
N
W (5)
(14) IN (WL)
IN
LVIC
IN
IN
(13) IN (VL)
(12) IN (UL)
(11) COM(L)
NV (6)
NU (7)
COM
VDD
(10) VDD(L)
R
TH (8)
Thermistor
VTH (9)
(18) RSC
NOTES:
1. Inverter low−side is composed of three IGBTs, freewheeling diodes for each IGBT, and one control IC. It has gate drive and protection
functions.
2. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
3. Inverter high−side is composed of three IGBTs, freewheeling diodes, and three drive ICs for each IGBT.
Figure 2. Internal Block Diagram
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4
NFVA23512NP2T
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Conditions
Rating
Unit
INVERTER PART
V
Supply Voltage
Applied between P−N , N , N
900
1000
1200
35
V
V
V
A
PN
PN(Surge)
U
V
W
V
Supply Voltage (Surge)
Applied between P−N , N , N
U V
W
V
CES
Collector−Emitter Voltage
Each IGBT Collector Current
I
C
T = 100°C, T ≤150°C, V ≥ 15 V
C J DD
(Note 4)
I
Each IGBT Collector Current (Peak)
T
= 25°C, T ≤150°C, Under 1 ms
70
A
CP
C
J
Pulse Width (Note 4)
P
C
Collector Dissipation
T
C
= 25°C per One Chip (Note 4)
171
W
T
J
Operating Junction Temperature
V
V
= 960 V
−40∼150
−40∼125
°C
CES
= 1200 V
CES
CONTROL PART
V
Control Supply Voltage
Applied between V
, V − COM
DD(H) DD(L)
20
20
V
V
DD
V
High−Side Control Bias Voltage
Applied between V
−V
,
BS
B(U) S(U)
−V
V
−V
, V
B(V) S(V) B(W) S(W)
V
IN
Input Signal Voltage
Applied between IN
, IN
, IN
,
−0.3∼V +0.3
V
(UH)
(VH)
(WH)
DD
IN
, IN
, IN
− COM
(UL)
(VL)
(WL)
V
Fault Output Supply Voltage
Fault Output Current
Applied between V − COM
−0.3∼V +0.3
V
mA
V
FO
FO
DD
I
Sink Current at V pin
2
FO
FO
V
SC
Current Sensing Input Voltage
Applied between C − COM
−0.3∼V +0.3
SC
DD
BOOTSTRAP DIODE PART
V
Maximum Repetitive Reverse Voltage
Forward Current
1200
1.0
V
A
A
RRM
I
F
T
T
= 25°C, T ≤150°C (Note 4)
J
C
I
Forward Current (Peak)
= 25°C, T ≤150°C, Under 1 ms
2.0
FP
C
J
Pulse Width (Note 4)
T
J
Operating Junction Temperature
(Note 5)
−40∼150
°C
TOTAL SYSTEM
t
Short Circuit Withstand Time
V
J
= V ≤ 16.5 V, V ≤ 800 V,
3
ms
°C
SC
DD
BS
PN
T = 150°C
Non−repetitive
T
STG
Storage Temperature
Isolation Voltage
−40∼150
V
60 Hz, Sinusoidal, AC 1 minute,
Connection Pins to Heat Sink Plate
2500
V
rms
ISO
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. These values had been made an acquisition by the calculation considered to design factor.
THERMAL RESISTANCE
Symbol
Parameter
Conditions
Min.
Typ.
−
Max.
0.73
1.26
−
Unit
°C/W
°C/W
nH
R
Junction to Case Thermal Resistance Inverter IGBT part (per 1/6 module)
−
−
−
th(j−c)Q
(Note 5)
R
Inverter FWD part (per 1/6 module)
−
th(j−c)F
L
s
Package Stray Inductance
P to N , N , N (Note 6)
32
U
V
W
5. For the measurement point of case temperature (T ), please refer to Figure 1. DBC discoloration and Picker Circle Printing allowed, please
C
®
refer to application note AN−9190 (Impact of DBC Oxidation on SPM Module Performance).
6. Stray inductance per phase measured per IEC 60747−15.
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5
NFVA23512NP2T
ELECTRICAL CHARACTERISTICS − INVERTER PART (T as specified)
J
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
Collector − Emitter Saturation Voltage
V
C
= V = 15 V, V = 5 V,
−
1.90
2.50
V
CE(SAT)
DD
BS
IN
I
= 35 A, T = 25°C
J
V
C
= V = 15 V, V = 5 V,
2.35
2.95
V
DD
BS
IN
I
= 35 A, T = 150°C
J
V
FWDi Forward Voltage
V
V
V
= 0 V, I = 35 A, T = 25°C
−
2.10
2.05
1.20
0.40
1.20
0.15
0.20
1.00
0.40
1.40
0.20
0.25
−
2.70
2.65
1.80
0.85
1.80
0.55
−
V
V
F
IN
F
J
= 0 V, I = 35 A, T = 150°C
IN
F
J
HS
LS
t
High Side Switching Times
= 600 V, V = 15 V, I = 35 A,
0.70
−
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
mA
ON
PN
DD
C
T = 25°C
J
t
C(ON)
V
IN
= 0 V ⇔ 5 V, Inductive Load
See Figure 4
(Note 7)
t
−
OFF
t
−
C(OFF)
t
rr
−
t
Low Side Switching Times
V
PN
= 600 V, V = 15 V, I = 35 A,
0.50
−
1.60
0.85
2.00
0.60
−
ON
DD
C
T = 25°C
J
t
C(ON)
V
IN
= 0 V ⇔ 5 V, Inductive Load
See Figure 4
(Note 7)
t
−
OFF
t
−
C(OFF)
t
rr
−
I
Collector−Emitter Leakage Current
T = 25°C, V = V
J CES
−
3
CES
CE
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. t and t
include the propagation delay time of the internal drive IC. t
and t
are the switching time of IGBT itself under the
ON
OFF
C(ON)
C(OFF)
given gate driving condition internally. For the detailed information see Figure 3.
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Shipping
NFVA23512NP2T
NFVA23512NP2T
ASPM34−CAA
(Pb−Free)
6 Units/Tube
100% I
100% I
C
C
t
rr
I
C
I
C
V
CE
V
CE
V
IN
V
IN
t
ON
t
OFF
t
t
c(OFF)
c(ON)
10% I
C
V
IN(ON)
V
IN(OFF)
10% V
10% I
CE
C
90% I 10% V
C
CE
(a) turn − on
(b) turn − off
Figure 3. Switching Time Definition
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6
NFVA23512NP2T
One−Leg Diagram of ASPM34
IC
RBS
P
CBS
VDD
VB
OUT
VS
COM
LS Switching
IN
VPN
HS Switching
LS Switching
U,V,W
Inductor
V
600V
IN
VDD
V
VIN
FO
HS Switching
OUT
5 V
0 V
C
FOD
VDD
4.7 kΩ
C
SC
V
COM
NU,V,W
15 V
V
RSC
5 V
Figure 4. Example Circuit for Switching Test
Inductive Load, V = 600 V, V = 15 V, T = 255C
Inductive Load, V = 600 V, V = 15 V, T = 1505C
PN
DD
J
PN
DD
J
8000
7200
8000
7200
IGBT Turn−ON, E
IGBT Turn−ON, E
on
on
IGBT Turn−OFF, E
FRD Turn−OFF, E
IGBT Turn−OFF, E
FRD Turn−OFF, E
off
rec
off
rec
6400
5600
6400
5600
4800
4100
4800
4100
3200
2400
3200
2400
1600
1600
800
0
800
0
0
4
8
12
16
20
24
28
32
36
40
0
4
8
12
16
20
24
28
32
36
40
COLLECTOR CURRENT, I [Amperes]
COLLECTOR CURRENT, I [Amperes]
C
C
Figure 5. Switching Loss Characteristics
600
550
R−T CURVE IN 505C ꢀ 1255C
20
500
16
450
400
12
8
350
300
250
4
0
200
150
100
50
50
60
70
80
90
100 110 120
Temperature [5C]
0
−20 −10
0
10
20
30 40
50 60
70 80
90 100 110 120
Temperature, T [5C]
TH
Figure 6. R−T Curve of Built−in Thermistor
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NFVA23512NP2T
BOOTSTRAP DIODE PART (T as specified)
J
Symbol
Parameter
Forward Voltage
Reverse−Recovery Time
Conditions
Min.
−
Typ.
2.2
80
Max.
Unit
V
V
F
I = 1.0 A, T = 25°C
−
−
F
J
t
rr
I = 1.0 A, dI /dt = 50 A/ms, T = 25°C
−
ns
F
F
J
CONTROL PART (T = 25°C)
J
Symbol
Parameter
Quiescent V Supply Current
Conditions
Min.
Typ.
Max.
Unit
I
V
= 15 V,
(UH,VH.WH)
V
V
V
− COM
− COM
−
−
0.15
mA
QDDH
DD
DD(H)
DD(UH)
DD(VH)
DD(WH)
(H),
(H),
(H)
IN
= 0 V
− COM
I
V
= 15 V,
(UL,VL.WL)
V
− COM
(L)
−
−
−
−
4.80
0.30
mA
mA
QDDL
DD(L)
DD(L)
IN
= 0 V
I
Operating V Supply Current
V
DD(H)
= 15 V, f
= 20
V
V
V
− COM
PDDH
DD
PWM
DD(UH)
DD(VH)
DD(WH)
(H),
(H),
kHz, duty = 50%, applied
to one PWM signal input
for High−Side
− COM
− COM
(H)
I
V
= 15 V, f
= 20
V
DD(L)
− COM
(L)
−
−
15.5
mA
PDDL
DD(L)
PWM
kHz, duty = 50%, applied
to one PWM signal input
for Low−Side
I
Quiescent V Supply Current
V
= 15 V,
(UH,VH.WH)
V
V
V
− V
S(V)
− V
,
−
−
−
−
0.30
12.0
mA
mA
QBS
BS
BS
IN
B(U)
B(V)
B(W)
S(U)
= 0 V
− V
,
S(W)
I
Operating V Supply Current
V
PWM
= V = 15 V,
V
B(U)
V
B(V)
V
B(W)
− V
− V
,
,
PBS
BS
DD
BS
S(U)
S(V)
− V
f
= 20 kHz, duty =
50%, applied to one PWM
signal input for High−Side
S(W)
V
Fault Output Voltage
V
= 15 V, V = 0 V, V Circuit: 4.7 kW to 5 V
4.5
−
−
−
−
0.50
−
V
V
FOH
DD
SC
FO
Pull−up
V = 15 V, V = 1 V, V Circuit: 4.7 kW to 5 V
DD
V
FOL
SEN
SC
FO
Pull−up
I
Sensing Current of Each
Sense IGBT
V
= 15 V, V = 5 V,
I = 35 A
C
−
36.0
mA
DD
IN
R
= 0 W, No Connection
SC
of Shunt Resistor at
terminal
N
U,V.W
V
Short Circuit Trip Level
V
= 15 V (Note 8)
C
− COM
(L)
0.43
0.50
70
0.57
V
A
SC(ref)
DD
SC
I
Short Circuit Current Level
for Trip
R
= 16 W ( 1%), No Connection of Shunt Re-
SC
−
−
SC
sistor at N
Terminal (Note 8)
U,V,W
UV
UV
UV
UV
t
Supply Circuit Under−Voltage
Detection Level
Reset Level
10.3
10.8
9.5
10.0
50
−
−
12.8
13.3
12.0
12.5
−
V
V
DDD
DDR
BSD
BSR
Protection
Detection Level
Reset Level
−
V
−
V
Fault−Out Pulse Width
C
C
= Open
(Note 9)
−
ms
ms
V
FOD
FOD
FOD
= 2.2 nF
1.7
−
−
−
V
IN(ON)
ON Threshold Voltage
OFF Threshold Voltage
Resistance of Thermistor
Applied between IN
− COM
(H)
−
2.6
−
(UH,VH.WH)
− COM
(L)
IN
(UL,VL.WL)
V
0.8
−
−
V
IN(OFF)
R
TH
at T = 25°C
See Figure 6
(Note 10)
47
2.9
−
kW
kW
TH
at T = 100°C
−
−
TH
8. Short−circuit current protection functions only at the low−sides because the sense current is divided from main current at low−side IGBTs.
Inserting the shunt resistor for monitoring the phase current at N , N , N terminal, the trip level of the short−circuit current is changed.
U
V
W
FOD
9. The fault−out pulse width t
depends on the capacitance value of C
according to the following approximate equation :
FOD
6
t
= 0.8 × 10 × C
FOD
FOD
10.T is the temperature of thermistor itself. To know case temperature (T ), conduct experiments considering the application.
TH
C
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8
NFVA23512NP2T
RECOMMENDED OPERATING CONDITIONS
Value
Typ.
600
Min.
300
Max.
800
Symbol
Parameter
Supply Voltage
Conditions
Unit
V
V
Applied between P − N , N , N
U V W
PN
DD
V
Control Supply Voltage
High−Side Bias Voltage
Control Supply Variation
Applied between V
− COM
,
14.0
15
16.5
V
DD(UH, VH, WH)
(H)
V
− COM
DD(L)
(L)
V
BS
Applied between V
− V , V
S(U) B(V)
− V ,
S(V)
13.0
−1
15
−
18.5
1
V
V/ms
ms
B(U)
V
B(W)
− V
S(W)
dV /dt,
DD
dV /dt,
BS
t
Blanking Time for Preventing
Arm−Short
For Each Input Signal
−40°C ≤ T ≤ 125°C, −40°C ≤ T ≤ 150°C
2.0
−
−
dead
f
PWM Input Signal
−
−
−
20
5
kHz
V
PWM
C
J
V
SEN
Voltage for Current Sensing
Applied between N , N , N − COM
(H, L)
−5
U
V
W
(Including Surge Voltage)
PW
PW
Minimum Input Pulse Width
Junction Temperature
V
= V = 15 V, I ≤ 70 A, Wiring Inductance
2.0
2.0
−40
−
−
−
−
−
ms
IN(ON)
DD
BS
C
between N , , and DC Link N < 10 nH
U V W
(Note 11)
IN(OFF)
T
150
°C
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
11. This product might not make response if input pulse width is less than the recommended value.
MECHANICAL CHARACTERISTICS AND RATINGS
Value
Min.
0
Typ.
−
Max.
+200
1.5
15.1
−
Parameter
Device Flatness
Conditions
Unit
mm
See Figure 7
Mounting Torque
Mounting Screw: M4
See Figure 8
Recommended 1.0 N•m
Recommended 10.1 kg•cm
0.9
9.1
10
2
1.0
10.1
−
N•m
kg•cm
s
Terminal Pulling Strength
Terminal Bending Strength
Weight
Load 19.6 N
Load 9.8 N, 90 degrees Bend
−
−
times
g
−
50
−
(＋)
(＋)
Figure 7. Flatness Measurement Position
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9
NFVA23512NP2T
2
1
NOTES:
12.Do not make over torque when mounting screws. Much mounting torque may cause DBC cracks, as well as bolts and Al heat−sink
destruction.
13.Avoid one−sided tightening stress. Figure 8 shows the recommended torque order for mounting screws. Uneven mounting can cause
the DBC substrate of package to be damaged. The pre−screwing torque is set to 20∼30% of maximum torque rating.
Figure 8. Mounting Screws Torque Order
Input signal
Protection
RESET
a1
SET
RESET
Circuit State
UV
DDR
a6
Control
Supply Voltage
UV
DDD
a3
a4
a2
a7
Output Current
a5
Fault Output Signal
a1: Control supply voltage rises: After the voltage rises UV
a2: Normal operation: IGBT ON and carrying current.
, the circuits start to operate when next input is applied.
DDR
a3: Under voltage detection (UV
).
DDD
a4: IGBT OFF in spite of control input condition.
a5: Fault output operation starts with a fixed pulse width according to the condition of the external capacitor C
.
FOD
a6: Under voltage reset (UV
).
DDR
a7: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 9. Under−Voltage Protection (Low−Side)
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10
NFVA23512NP2T
Input signal
Protection
Circuit State
RESET
SET
RESET
UV
BSR
b1
b5
Control
Supply Voltage
UV
BSD
b3
b4
b6
b2
Output Current
High−level (no fault output)
Fault Output Signal
b1: Control supply voltage rises: After the voltage rises UV
b2: Normal operation: IGBT ON and carrying current.
, the circuits start to operate when next input is applied.
BSR
b3: Under voltage detection (UV
).
BSD
b4: IGBT OFF in spite of control input condition, but there is no fault output signal.
b5: Under−voltage reset (UV ).
BSR
b6: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 10. Under−Voltage Protection (High−Side)
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11
NFVA23512NP2T
Lower Arms
Control Input
c6
c7
Protection
Circuit State
SET
c3
RESET
c4
Internal IGBT
Gate−Emitter Voltage
c2
Internal delay
at protection circuit
SC current trip level
c8
c1
Output Current
SC reference voltage
Sensing Voltage
of Sense Resistor
RC filter circuit
time constant
delay
Fault Output Signal
c5
(with the external sense resistance and RC filter connection)
c1: Normal operation: IGBT ON and carrying current.
c2: Short−circuit current detection (SC trigger).
c3: All low−side IGBT’s gate are hard interrupted.
c4: All low−side IGBTs turn OFF.
c5: Fault output operation starts with a fixed pulse width according to the condition of the external capacitor C
c6: Input HIGH: IGBT ON state, but during the active period of fault output the IGBT doesn’t turn ON.
c7: Fault output operation finishes, but IGBT doesn’t turn on until triggering next signal from LOW to HIGH.
c8: Normal operation: IGBT ON and carrying current.
.
FOD
Figure 11. Short−Circuit Current Protection (Low−Side Operation Only)
INPUT/OUTPUT INTERFACE CIRCUIT
+5V (MCU or Control power)
4.7 kΩ
ASPM
IN
IN
, IN
, IN
(UH)
(VH)
(WH)
, IN
(VL)
, IN
(WL)
(UL)
MCU
VFO
COM
NOTE:
14.RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance
of the application’s printed circuit board. The input signal section of the Motion SPM 2 product integrates 5 kW (typ.) pull−down resistor.
Therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input terminal.
Figure 12. Recommended CPU I/O Interface Circuit
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12
NFVA23512NP2T
P (1)
R1
R1
R1
(30) IN(WH)
(31) VDD(WH)
IN
VDD
COM
Gating WH
Gating VH
Gating UH
C4
C4
R2
OUT
VS
(32) VBD(W)
HVIC
HVIC
HVIC
(33) VB(W)
(34) VS(W)
VB
W (2)
C3
(25) IN (VH)
(26) VDD(VH)
IN
VDD
COM
C4
C4
R2
OUT
VS
(27) VBD(V)
(28) VB(V)
(29) VS(V)
VB
V (3)
C3
M
(19) IN (UH)
(21) VDD(UH)
VDC
IN
VDD
COM
C7
(20) COM
C4
C4
(H)
OUT
VS
R2
(22) VBD(U)
(23) VB(U)
(24) VS(U)
C1 C1 C1
M
C
U
VB
U (4)
C3
5V line
R1
R3
C5
(16) CFOD
(15) VFO
OUT
Fault
CFOD
VFO
A
R4
NW (5)
C1
C1
(14) IN(WL)
R1
R1
R1
IN
Gating WL
Gating VL
Gating UL
(13) IN (VL)
(12) IN (UL)
(10) VDD(L)
IN
OUT
OUT
LVIC
R4
IN
N
V (6)
E
15V line
VDD
Shunt
Resistor
C1 C1
5V line
C1
Power
GND Line
C2
(11) COM(L)
C4
COM
(9) VTH
(8) RTH
R4
CSC
NU (7)
Temp.
Monitoring
Thermistor
RSC (18)
R5
R7
(17) C
Sense
SC
Resistor
D
B
C
R6
Control
GND Line
C6
W−Phase Current
V−Phase Current
U−Phase Current
NOTES:
15.To avoid malfunction, the wiring of each input should be as short as possible. (less than 2 − 3 cm)
16.V output is open−drain type. The signal line should be pulled up to the positive side of the MCU or control power supply with a resistor that makes I
FO
FO
up to 2 mA. Refer to Figure 13.
17.Fault out pulse width can be adjust by capacitor C connected to the C
terminal.
5
FOD
18.Input signal is active−HIGH type. There is a 5 kW resistor inside the IC to pull−down each input signal line to GND. RC coupling circuits should be adopted
for the prevention of input signal oscillation. R C time constant should be selected in the range 50∼150 ns. (Recommended R = 100 W, C = 1 nF)
1
1
1
1
19.Each wiring pattern inductance of A point should be minimized (Recommended less than 10 nH). Use the shunt resistor R of surface mounted (SMD) type
4
to reduce wiring inductance. To prevent malfunction, wiring of point E should be connected to the terminal of the shunt resistor R as close as possible.
4
20.To insert the shunt resistor to measure each phase current at N , N , N terminal, it makes to change the trip level I about the short−circuit current.
U
V
W
SC
21.To prevent errors of the protection function, the wiring of B, C and D point should be as short as possible. The wiring of B between C filter and R terminal
SC
SC
should be divided at the point that is close to the terminal of sense resistor R .
5
22.For stable protection function, use the sense resistor R with resistance variation within 1% and low inductance value.
5
23.In the short−circuit protection circuit, please select the R C time constant in the range 1.0∼1.5 ms. R should be selected with minimum of 10 times larger
6
6
6
resistance than sense resistor R . Do enough evaluation on the real system because short−circuit protection time may vary wiring pattern layout and value
5
of the R C time constant.
6
6
24.Each capacitor should be mounted as close to the pins of the ASPM34 product as possible.
25.To prevent surge destruction, the wiring between the smoothing capacitor C and the P & GND pins should be as short as possible. The use of a high−frequen-
7
cy non−inductive capacitor between the P & GND pins is recommended.
26.Relays are used at almost every systems of electrical equipment at industrial application. In these cases, there should be sufficient
distance between the MCU and the relays.
27.The Zener diode or transient voltage suppressor should be adopted for the protection of ICs from the surge destruction between each pair of control supply
terminals (Recommended Zener diode is 22 V/1 W, which has the lower Zener impedance characteristic than about 15 W).
28.C of around seven times larger than bootstrap capacitor C is recommended.
2
3
29.Choose the electrolytic capacitor with good temperature characteristic in C . Choose 0.1∼0.2 mF R−category ceramic capacitors with good temperature and
3
frequency characteristics in C .
4
Figure 13. Typical Application Circuit
SPM is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DIP34 80x33, AUTOMOTIVE MODULE
CASE MODGL
ISSUE O
DATE 19 OCT 2018
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Lot ID
*This information is generic. Please refer to
AT
Y
W
= Assembly & Test Location
= Year
= Work Week
XXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
NNN = Serial Number
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON97156G
DIP34 80x33, AUTOMOTIVE MODULE
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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