NCV8165ML330TCG [ONSEMI]
LDO Regulator for RF and Analog Circuits - Ultra-Low Noise and High PSRR 500 mA;
| 型号： | NCV8165ML330TCG |
| 厂家： | 
ONSEMI |
| 描述： | LDO Regulator for RF and Analog Circuits - Ultra-Low Noise and High PSRR 500 mA PC 光电二极管 输出元件 调节器 |
| 文件： | 总10页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV8165
LDO Regulator for RF and
Analog Circuits - Ultra-Low
Noise and High PSRR
500 mA
www.onsemi.com
The NCV8165 is a linear regulator capable of supplying 500 mA
output current. Designed to meet the requirements of RF and analog
circuits, the NCV8165 device provides low noise, high PSRR, low
quiescent current, and very good load/line transients. The device is
designed to work with a 1 mF input and a 1 mF output ceramic capacitor.
It is available in DFNW8 3 mm x 3 mm package with wettable flanks.
MARKING
DIAGRAM
1
8165L
330
DFNW8, 3x3
CASE 507AD
Features
ALYWG
1
G
• Operating Input Voltage Range: 1.9 V to 5.5 V
• Available in Fixed Voltage Option: 1.8 V to 5.2 V
A
L
Y
W
G
= Assembly Location
= Wafer Lot
•
2% Accuracy Over Load/Temperature
= Year
• Ultra Low Quiescent Current Typ. 12 mA
• Standby Current: Typ. 0.1 mA
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
• Very Low Dropout: 190 mV at 500 mA
• Ultra High PSRR: Typ. 85 dB at 20 mA, f = 1 kHz
• Ultra Low Noise: 8.5 mV
RMS
PIN CONNECTIONS
• Stable with a 1 mF Small Case Size Ceramic Capacitors
• Available in −DFNW8 0.65P, 3 mm x 3 mm x 0.9 mm Package
OUT
N/C
1
2
3
4
8
7
6
5
IN
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
N/C
N/C
EN
EXP
N/C
GND
DFNW8 3x3 mm
(Top View)
Typical Applications
• Battery−powered Equipment
• Wireless LAN Devices
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
• Smartphones, Tablets
• Cameras, DVRs, STB and Camcorders
V
V
OUT
IN
IN
OUT
NCV8165
C
1 mF
Ceramic
EN
IN
C
OUT
1 mF
Ceramic
ON
GND
OFF
Figure 1. Typical Application Schematics
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
September, 2019 − Rev. 1
NCV8165/D
NCV8165
IN
ENABLE
LOGIC
THERMAL
EN
SHUTDOWN
BANDGAP
MOSFET
REFERENCE
INTEGRATED
DRIVER WITH
CURRENT LIMIT
SOFT−START
OUT
* ACTIVE DISCHARGE
Version A only
EN
GND
Figure 2. Simplified Schematic Block Diagram
Description
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
IN
8
Input voltage supply pin
Regulated output voltage. The output should be bypassed with small 1 mF ceramic capacitor.
1
5
OUT
EN
Chip enable: Applying V < 0.4 V disables the regulator, Pulling V > 1.2 V enables the LDO.
EN
EN
4
GND
EPAD
Common ground connection
EPAD
Expose pad should be tied to ground plane for better power dissipation
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Input Voltage (Note 1)
V
IN
−0.3 V to 6
Output Voltage
V
OUT
−0.3 to V + 0.3, max. 6 V
V
IN
Chip Enable Input
V
CE
−0.3 to V + 0.3, max. 6 V
V
IN
Output Short Circuit Duration
Maximum Junction Temperature
Storage Temperature
t
unlimited
150
s
SC
T
°C
°C
V
J
T
STG
−55 to 150
2000
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
ESD
HBM
ESD
200
V
MM
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
1.9
Max
5.5
Unit
V
Input Voltage
V
IN
Junction Temperature
T
J
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
NCV8165
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, DFNW8 (Note 3)
R
100
°C/W
q
JA
Thermal Resistance, Junction−to−Air
3. Measured according to JEDEC board specification. Detailed description of the board can be found in JESD51−7.
ELECTRICAL CHARACTERISTICS −40°C ≤ T ≤ 125°C; V = V
+ 1 V; I
= 1 mA, C = C
= 1 mF, unless otherwise
J
IN
OUT(NOM)
OUT
IN
OUT
noted. V = 1.2 V. Typical values are at T = +25°C (Note 4).
EN
J
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Operating Input Voltage
V
IN
1.9
5.5
V
Output Voltage Accuracy (Note 5)
V
IN
= V
+ 1 V to 5.5 V
≤ 500 mA
OUT(NOM)
V
OUT
−2
+2
%
0 mA ≤ I
OUT
Line Regulation
V
+ 1 V ≤ V ≤ 5.5 V
Line
Reg
0.09
0.01
315
mV/V
OUT(NOM)
IN
Load Regulation
I
= 1 mA to 500 mA
Load
mV/mA
OUT
Reg
Dropout Voltage (Note 6)
I
= 500 mA
V
V
= 1.8 V
= 3.3 V
450
290
OUT
OUT(NOM)
OUT(NOM)
V
DO
mV
mA
190
Output Current Limit
Short Circuit Current
Quiescent Current
V
OUT
= 90% V
I
CL
800
1.2
1000
1050
9.7
OUT(NOM)
V
= 0 V
I
OUT
SC
I
= 0 mA
I
Q
18
1
mA
mA
OUT
Shutdown Current
V
EN
≤ 0.4 V, V = 4.8 V
I
0.01
IN
DIS
EN Pin Threshold Voltage
EN Input Voltage “H”
EN Input Voltage “L”
V
ENH
V
V
ENL
0.4
0.5
EN Pull Down Current
V
= 4.8 V
I
0.2
mA
ms
EN
EN
Turn−On Time
C
= 1 mF, From assertion of V to
OUT EN
120
V
OUT
= 95% V
OUT(NOM)
Power Supply Rejection Ratio
V
= 3.3 V,
f = 100 Hz
83
85
80
63
OUT(NOM)
OUT
I
= 20 mA
f = 1 kHz
f = 10 kHz
f = 100 kHz
PSRR
dB
Output Voltage Noise
f = 10 Hz to 100 kHz
I
= 20 mA
V
8.5
160
140
280
mV
RMS
OUT
N
Thermal Shutdown Threshold
Temperature rising
Temperature falling
T
SDH
°C
°C
W
T
SDL
Active output discharge resistance
V
EN
< 0.4 V, Version A only
R
DIS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T = 25°C.
A
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
5. Respect SOA.
6. Dropout voltage is characterized when V
falls 100 mV below V
.
OUT
OUT(NOM)
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3
NCV8165
TYPICAL CHARACTERISTICS
2.90
2.89
16
14
12
10
8
2.88
2.87
2.86
T = 25°C
J
T = 125°C
J
T = −40°C
J
I
= 10 mA
OUT
2.85
2.84
2.83
6
V
= 3.85 V
= 2.85 V
= 1 mF
IN
V
C
C
= 2.85 V
= 1 mF
= 1 mF
4
OUT
V
OUT
2.82
2.81
2.80
IN
OUT
C
C
IN
2
0
= 1 mF
OUT
−40 −20
0
20
40
60
80
100 120
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
, INPUT VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
J
V
IN
Figure 3. Output Voltage vs. Temperature −
OUT = 2.85 V
Figure 4. Quiescent Current vs. Input Voltage
V
1800
1600
1400
1200
1000
800
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
V
C
C
= 1.8 V
= 1 mF
= 1 mF
OUT
T = 125°C
J
V
V
C
C
= 3.85 V
IN
IN
= 2.85 V
OUT
OUT
= 1 mF
T = 25°C
J
IN
= 1 mF
OUT
T = 125°C
J
T = −40°C
J
T = 25°C
J
600
400
T = −40°C
200
0
J
0.05
0
0.001 0.01
0.1
1
10
100
1000
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7 0.8
I , OUTPUT CURRENT (mA)
OUT
I , OUTPUT CURRENT (A)
OUT
Figure 5. Ground Current vs. Output Current
Figure 6. Dropout Voltage vs. Output Current −
OUT = 1.8 V
V
0.30
0.27
0.24
0.21
0.18
0.15
0.12
0.09
0.06
0.30
0.27
0.24
0.21
0.18
0.15
0.12
0.09
0.06
T = 125°C
T = 125°C
J
J
V
C
C
= 3.3 V
= 1 mF
= 1 mF
V
C
C
= 2.85 V
= 1 mF
= 1 mF
OUT
OUT
IN
IN
OUT
OUT
T = 25°C
J
T = 25°C
J
T = −40°C
J
T = −40°C
J
0.03
0
0.03
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7 0.8
I , OUTPUT CURRENT (A)
OUT
I , OUTPUT CURRENT (A)
OUT
Figure 7. Dropout Voltage vs. Output Current −
OUT = 2.85 V
Figure 8. Dropout Voltage vs. Output Current −
V
VOUT = 3.3 V
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4
NCV8165
TYPICAL CHARACTERISTICS
1050
1000
950
900
850
800
750
700
1050
1000
950
900
850
800
750
V
V
C
C
= 3.85 V
V
V
C
C
= 3.85 V
700
650
IN
IN
= 2.85 V
= 2.85 V
OUT
OUT
650
= 1 mF
= 1 mF
IN
IN
= 1 mF
600
550
= 1 mF
600
550
OUT
OUT
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Current Limit vs. Temperature
Figure 10. Short Circuit Current vs.
Temperature
1000
900
800
700
600
500
400
300
200
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
T = 125°C
J
C
C
= 1 mF
T = −40°C
IN
J
= 1 mF
OUT
T = 25°C
J
V
IN
= 5.5 V
V
IN
= 3.85 V
C
C
= 1 mF
= 1 mF
IN
OUT
100
0
0.05
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
, INPUT VOLTAGE (V)
−40 −20
0
20
40
60
80
100 120
V
IN
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Short Circuit Current vs. Input
Voltage
Figure 12. Disable Current vs. Temperature
400
360
320
280
240
200
160
120
80
800
750
700
650
600
550
500
450
400
V
V
I
C
C
= 5.5 V
IN
= 2.85 V
OUT
= 10 mA
OUT
OFF −> ON
ON −> OFF
= 1 mF
IN
= 1 mF
OUT
V
= 5.5 V
EN
V
V
I
C
C
= 5.5 V
IN
= 2.85 V
OUT
= 1 mA
OUT
= 1 mF
IN
350
300
40
0
−40 −20
= 1 mF
OUT
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. Current to Enable Pin vs.
Temperature
Figure 14. Enable Voltage Threshold vs.
Temperature
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5
NCV8165
TYPICAL CHARACTERISTICS
100
90
100
90
1 mA
1 mA
80
70
60
50
40
30
20
80
70
60
50
20 mA
20 mA
40
30
20
V
V
C
C
= 3.6 V
V
V
C
C
= 3.8 V
IN
IN
= 3.3 V
= 1 mF
= 3.3 V
= 1 mF
OUT
OUT
IN
IN
100 mA
100 mA
1M
= 1 mF
= 1 mF
OUT
OUT
MLCC, X7R, 0805
MLCC, X7R, 0805
10
0
10
0
100 1K
10K
100K
1M
10M
100 1K
10K
100K
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. Power Supply Rejection Ratio vs.
Figure 16. Power Supply Rejection Ratio vs.
Current, VDROP = 0.5 V, COUT = 1 mF
Current, VDROP = 0.3 V, COUT = 1 mF
100
90
80
70
60
50
40
30
20
100
90
4.3 V
4.3 V
80
70
60
50
40
30
20
3.6 V
3.6 V
3.8 V
3.8 V
V
OUT
= 3.3 V
V
I
C
C
= 3.3 V
= 100 mA
OUT
I
= 20 mA
OUT
OUT
C
C
= 1 mF
IN
= 1 mF
IN
= 1 mF
OUT
= 1 mF
MLCC, X7R, 0805
OUT
MLCC, X7R, 0805
10
0
10
0
100 1K
10K
100K
1M
10M
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Power Supply Rejection Ratio vs.
Figure 18. Power Supply Rejection Ratio vs.
Input Voltage, IOUT = 100 mA, COUT = 1 mF
Input Voltage, IOUT = 20 mA, COUT = 1 mF
100K
10K
100K
10K
1K
V
V
= 3.6 V
IN
V
V
= 3.8 V
IN
= 3.3 V
OUT
= 3.3 V
OUT
I
= 20 mA
= 1 mF
OUT
I
= 250 mA
= 1 mF
OUT
C
C
IN
C
C
IN
= 1 mF
OUT
= 1 mF
OUT
MLCC, X7R, 0805
MLCC, X7R, 0805
1K
100
10
100
10
10
100
1K
10K
100K
1M
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Output Voltage Noise Spectral Density
Figure 20. Output Voltage Noise Spectral Density
for VOUT = 3.3 V, IOUT = 20 mA, COUT = 1 mF
for VOUT = 3.3 V, IOUT = 250 mA, COUT = 1 mF
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6
NCV8165
APPLICATIONS INFORMATION
General
output capacitors and lower ESR could improve the load
The NCV8165 is an ultra−low noise 500 mA low dropout
transient response or high frequency PSRR. It is not
recommended to use tantalum capacitors on the output due
to their large ESR. The equivalent series resistance of
tantalum capacitors is also strongly dependent on the
temperature, increasing at low temperature.
regulator designed to meet the requirements of RF
applications and high performance analog circuits. The
NCV8165 device provides very high PSRR and excellent
dynamic response. In connection with low quiescent current
this device is well suitable for battery powered application
such as cell phones, tablets and other. The NCV8165 is fully
protected in case of current overload, output short circuit and
overheating.
Enable Operation
The NCV8165 uses the EN pin to enable/disable its device
and to deactivate/activate the active discharge function. If
the EN pin voltage is <0.4 V the device is guaranteed to be
disabled. The pass transistor is turned−off so that there is
virtually no current flow between the IN and OUT. The
active discharge transistor is active so that the output voltage
Input Capacitor Selection (CIN)
Input capacitor connected as close as possible is necessary
for ensure device stability. The X7R or X5R capacitor
should be used for reliable performance over temperature
range. The value of the input capacitor should be 1 mF or
greater to ensure the best dynamic performance. This
capacitor will provide a low impedance path for unwanted
AC signals or noise modulated onto constant input voltage.
There is no requirement for the ESR of the input capacitor
but it is recommended to use ceramic capacitors for their low
ESR and ESL. A good input capacitor will limit the
influence of input trace inductance and source resistance
during sudden load current changes.
V
OUT
is pulled to GND through a 280 W resistor. In the
disable state the device consumes as low as typ. 10 nA from
the V . If the EN pin voltage >1.2 V the device is
IN
guaranteed to be enabled. The NCV8165 regulates the
output voltage and the active discharge transistor is
turned−off. The EN pin has internal pull−down current
source with typ. value of 200 nA which assures that the
device is turned−off when the EN pin is not connected. In the
case where the EN function isn’t required the EN should be
tied directly to IN.
Output Decoupling (COUT
)
Output Current Limit
The NCV8165 requires an output capacitor connected as
close as possible to the output pin of the regulator. The
recommended capacitor value is 1 mF and X7R or X5R
dielectric due to its low capacitance variations over the
specified temperature range. The NCV8165 is designed to
remain stable with minimum effective capacitance of 0.7 mF
to account for changes with temperature, DC bias and
package size. Especially for small package size capacitors
such as 0201 the effective capacitance drops rapidly with the
applied DC bias. Please refer Figure 21.
Output Current is internally limited within the IC to a
typical 1000 mA. The NCV8165 will source this amount of
current measured with a voltage drops on the 90% of the
nominal V
. If the Output Voltage is directly shorted to
= 0 V), the short circuit protection will limit
OUT
ground (V
OUT
the output current to 1050 mA (typ.). The current limit and
short circuit protection will work properly over whole
temperature range and also input voltage range. There is no
limitation for the short circuit duration.
Thermal Shutdown
When the die temperature exceeds the Thermal Shutdown
threshold (T = 160°C typical), Thermal Shutdown event
SD
is detected and the device is disabled. The IC will remain in
this state until the die temperature decreases below the
Thermal Shutdown Reset threshold (T
= 140°C typical).
SDU
Once the IC temperature falls below the 140°C the LDO is
enabled again. The thermal shutdown feature provides the
protection from a catastrophic device failure due to
accidental overheating. This protection is not intended to be
used as a substitute for proper heat sinking.
Reverse Current
The PMOS pass transistor has an inherent body diode
which will be forward biased in the case that V
> V .
OUT
IN
Figure 21. Capacity vs DC Bias Voltage
Due to this fact in cases, where the extended reverse current
condition can be anticipated the device may require
additional external protection.
There is no requirement for the minimum value of
Equivalent Series Resistance (ESR) for the C
but the
OUT
maximum value of ESR should be less than 1.7 W. Larger
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NCV8165
Power Supply Rejection Ratio
maximum power dissipation supported by the device is
dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. For reliable operation junction temperature
should be limited to +125°C. The maximum power
The NCV8165 features very high Power Supply
Rejection ratio. If desired the PSRR at higher frequencies in
the range 100 kHz – 10 MHz can be tuned by the selection
of C
capacitor and proper PCB layout.
OUT
Turn−On Time
The turn−on time is defined as the time period from EN
assertion to the point in which V
nominal value. This time is dependent on various
dissipation the NCV8165 can handle is given by:
o
ƪ
ƫ
125 C * TA
will reach 98% of its
OUT
PD(MAX)
+
(eq. 1)
qJA
application conditions such as V
, C
, T .
OUT(NOM) OUT A
The power dissipated by the NCV8165 for given application
conditions can be calculated from the following equations:
Power Dissipation
ǒV
Ǔ
(eq. 2)
As power dissipated in the NCV8165 increases, it might
become necessary to provide some thermal relief. The
P
D [ VIN @ IGND ) IOUT IN * VOUT
300
250
200
150
100
50
1.8
P
, T = 25°C, 2 oz Cu
A
D(MAX)
1.5
1.2
0.9
0.6
0.3
0
P
, T = 25°C, 1 oz Cu
D(MAX) A
q
, 1 oz Cu
JA
q
, 2 oz Cu
JA
0
0
100
200
300
400
500
600
2
700
COPPER HEAT SPREADER AREA (mm )
Figure 22. qJA and PD(MAX) vs. Copper Area (DFNW8)
PCB Layout Recommendations
To obtain good transient performance and good regulation
pins will also improve the device thermal resistance. The
actual power dissipation can be calculated from the equation
above (Equation 2). Expose pad can be tied to the GND pin
for improvement power dissipation and lower device
temperature.
characteristics place C and C
capacitors close to the
IN
OUT
device pins and make the PCB traces wide. In order to
minimize the solution size, use 0402 or 0201 capacitors with
appropriate capacity. Larger copper area connected to the
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8
NCV8165
ORDERING INFORMATION
†
Device
Nominal Output Voltage
Description
Marking
Package
Shipping
8165L
330
NCV8165ML330TBG
3.3 V
3.3 V
500 mA, Active Discharge
DFNW8
(Pb−Free)
3000 / Tape
& Reel
8165L
330
NCV8165ML330TCG
500 mA, Active Discharge
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NCV8165
PACKAGE DIMENSIONS
DFNW8 3x3, 0.65P
CASE 507AD
ISSUE A
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L3
L3
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. THIS DEVICE CONTAINS WETTABLE FLANK
DESIGN FEATURE TO AID IN FILLET FORMA-
TION ON THE LEADS DURING MOUNTING.
L
L
ALTERNATE
CONSTRUCTION
DETAIL A
E
A
PIN ONE
REFERENCE
EXPOSED
COPPER
MILLIMETERS
DIM MIN
NOM
0.90
−−−
MAX
1.00
0.05
A4
A1
A
A1
A3
A4
b
0.80
−−−
0.20 REF
−−−
0.30
3.00
2.40
3.00
1.65
TOP VIEW
0.10
0.25
2.90
2.30
2.90
1.55
−−−
0.35
3.10
2.50
3.10
1.75
PLATING
A1
A4
ALTERNATE
CONSTRUCTION
DETAIL B
D
D2
E
E2
e
K
0.05
0.05
C
C
DETAIL B
A3
C
C
C
A4
0.65 BSC
0.28 REF
0.40
L
L3
0.30
0.50
SEATING
PLANE
NOTE 4
SIDE VIEW
0.05 REF
L3
PLATED
SURFACES
D2
DETAIL A
SECTION C−C
RECOMMENDED
1
4
5
SOLDERING FOOTPRINT*
2.50
8X
L
8X
0.58
2.35
E2
8
5
K
3.30 1.75
8
8X b
e/2
e
0.10
0.05
C
C
A B
PACKAGE
OUTLINE
NOTE 3
1
4
BOTTOM VIEW
8X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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