NCV78343DQ0R2G_技术文档

DATA SHEET

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Series String Pixel

Controller for Automotive

(Front) Lighting

MARKING

DIAGRAM

NV78343−0

FAWLYYWWG

NCV78343

SSOP36 EP

CASE 940AB

Introduction

The NCV78343 is a single−chip pixel controller with embedded

switches to control individual LEDs in a series LED string, designed

for automotive dynamic lighting applications and in particular for high

current LEDs. In order to create a pixel lighting solution, the LEDs

need to be powered by current sources such as NCV78763 or

NCV78723. The NCV78343 pixel controller devices receive the pixel

control parameters from the pixel light ECU which translates the

required light pattern or light image into individual pixel dimming

data.

One pixel controller device can control up−to 12 pixels of 1× or 2×

1.4 A LEDs per pixel. The maximum LED string voltage has to be

limited to 60 V.

When more than 12 pixels are to be controlled, multiple pixel

controllers can be combined in a single system.

NV78343 = Specific Device Code

F

A

WL

= Fab Indicator

= Assembly Location

= Wafer Lot

YYWW = Year / Work Week

= Pb−Free Designator

G

SAFETY DESIGN − ASIL B

ASIL B Product developed in compliance with

ISO 26262 for which a complete safety package

is available.

ORDERING INFORMATION

†

Device

NCV78343DQ0R2G SSOP36 EP 1500 / Tape &

(P−Free) Reel

Package

Shipping

The NCV78343 uses two communication interfaces for connection

with a microcontroller. A universal asynchronous receiver transmitter

(UART), which supports the use of CAN transceiver and multipoint

low voltage differential signaling (M−LVDS) for either local

connection or connection with the MCU.

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Features

• Single Chip Compatible with IMS Board (Single Layer)

• 12 Integrated Switches with Multiple Configuration Options

• Minimum of External Components

Typical Applications

• Dynamic Adaptive Driving Beam Functions

♦ Glare−free High Beam

♦ Static Swiveling

• Communication Interfaces to the Pixel Light ECU via

♦ Integrated M−LVDS

♦ UART over CAN Interface

♦ Beam Shaping

♦ Light Power Adjustment

• Animated Welcome Functions on Signal

Lights

• Wiping Blinker

♦ Integrated Bridge between M−LVDS and UART

♦ Supports up to 32 Devices, 1Mbaud

• No Need for Local MCU and Precise Clock

♦ Interface to External I2C EEPROM

♦ Integrated 8 bit Analog to Digital Converter

• Dimming Controller

♦ PWM + Phase Shift Unit per Channel

• Over Temp Protection

• Individual Open/Short/OV LED Diagnostic Feedback

• Open LED Failure Automatic Bypass

• This is a Pb−Free Device

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

1

Publication Order Number:

June, 2023 − Rev. 3

NCV78343/D

NCV78343

PACKAGE AND PIN DESCRIPTION

1

2

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

C2P

C2N

NC

TST1

TST

3

SW10

SW11

SW12

SW13

SW20

SW21

SW22

SW23

NC

4

SW30

SW31

SW32

SW33

SW40

SW41

SW42

SW43

NC

5

6

7

8

9

10

11

12

13

14

15

16

17

18

ADC0/SDA

ADC1/SCL

ADC2/ADR

VDD

RX

TX

A

B

GND

NC

A

VBB

B

Figure 1. Pin Connections – SSOP36−EP (Top View)

Table 1. PIN DESCRIPTION

Pin No.

SSOP36−EP

Pin Name

Description

Switch control capacitor connection

Not used (to be left floating)

I/O Type

HV in/out

NC

1

C2P

2

C2N

3, 12, 17, 26

NC

31, 32, 33, 34

SW1y

SW2y

SW3y

SW4y

RX

Power switch to short LED

HV in/out

HV60 in

27, 28, 29, 30

Power switch to short LED

4, 5, 6, 7

Power switch to short LED

8, 9, 10, 11

Power switch to short LED

13

14

Receive data input (To be tied to GND when not used)

Transmit data output (To be tied to GND or left floating when not used)

M−LVDS IO pins (internally connected; to be shorted to B when not used)

M−LVDS IO pins (internally connected; to be shorted to A when not used)

Battery supply

TX

MV out

15, 20

16, 19

18

A

MV in/out

HV60 supply

Ground

B

VBB

21

GND

Ground

22

VDD

3V analog and logic supply

LV supply

LV in

23

ADC2/ADR

ADC1/SCL

ADC0/SDA

TST

ADC input 2 / Address

24

ADC input 1 / I2C clock

LV in/out

HV70 in

25

ADC input 0 / I2C data

35

Internal function. To be tied to GND or left floating

Internal function. To be tied to GND

To be tied to GND

36

TST1

EP

LV in/out

Exposed Pad

EP

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2

NCV78343

Matrix Beam Sub−module

I_BUCK

C2

C1

C_LED

L

VDD

C2N

C2P

VBB

C3

SW43

NCV78343

Series string pixel

controller

C_SW

SW12

R1

CAN PHY

RX

TX

UART

CAN_H

CAN_L

Integrated

bridge in

repeater−

slave mode

A

B

A

B

Local M−LVDS

bus to all

M−LVDS

R2

nodes

SW1

I²C

ADC0/SDA

ADC1/SCL

EEPROM

SW10

Resistors

(NTC,

binning )

ADC3/ADR

GND EP

Sig GND

PWR GND

Figure 2. Application Diagram

Table 2. EXTERNAL COMPONENTS

Component

Function

Typ. Value

470

Unit

nF

kW

W

C1

C2

Cap. for VDD regulator

Cap. for switch control

VBB decoupling cap.

VLED decoupling cap.

Tx pull−up resistor

220

C3

100

C_SW

C_LED

R1

22

100

R2

Terminating resistors (only for the first and last device)

CAN transceiver

100

CAN

M−LVDS

EEPROM

L

NCV7344

NBA3N206S

CAT24C02

M−LVDS transceiver

External EEPROM

Ferrite bead *

600 @ 100 MHz

W

* It is recommended to place a ferrite bead at VBB net close to a VBB decoupling capacitor for a better electromagnetic immunity.

NOTE: Unused switches to be shorted externally. The switches should be grounded If a full section is not used.

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3

NCV78343

Section 4

Section 3

Section 2

Section 1

SW control

ADC0 / SDA

ADC1 / SCL

EXT. ADDR

VALID DET

I2C

EEPROM CTRL

OPMODE

CTRL

SWx3

SWx2

EEPROM

TIMEOUT

TSD DET

SW STATUS

DET

NM DET

ADDR

via ADC

OSC DET

ADC2 / ADR

SW control

RX

REGs

BANK

SW STATUS

DET

UART

DIMM ERR

DET

TX

PXN CORE

SWx1

SWx0

OTP CRC

CHECK

M−LVDS

OTP

SHADOW

REGs

SW STATUS

DET

SW MATRIX

A

B

COMM FAIL

DET

ADC CTRL

OTP CTRL

VDD

VBB

CLK

OTP MEMORY

ARRAY

VBB

VDD

VBB

LOW

DET

LDR REG

BIAS

VLED

V_BG

VBB

VDD

VBG

ADC[7:0]

ADC

(8bit)

VLED

MUX

TEMP

MEAS

VBG OK

DET

POR

TEMP

ADCx

TST1

TST

C2P

C2N

CCH

CAP UV

DET

GND

LOSS

DET

CLK

CCH

OSC

NCV78343

Series string pixel controller

Figure 3. Block Diagram

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4

NCV78343

The NCV78343 supports two communication interfaces:

M−LVDS bus for local connection between submodules of

each functional lights such as high beam, low beam, turn

indicator, etc. The second example uses the M−LVDS bus

only.

UART and M−LVDS. It is possible to communicate over

both interfaces, where the first example uses the UART

interface over CAN physical layer as a master bus from the

LED Driver Module to the first NCV78343 chip and the

BOOST

MCU

BUCK

CAN

transceiver

HB

function

UART

over CAN

CAN

transceiver

UART

Rx/Tx

NCV78343

CAN

(repeater−slave)

A/B

Local M−LVDS bus to all

nodes

Address

resistor

divider

I2C

EEPROM

To BCM

LB

function

Rx/Tx

NCV78343

(slave)

A/B

Address

resistor

divider

I2C

EEPROM

TI

function

Rx/Tx

NCV78343

(slave)

A/B

Address

resistor

divider

I2C

EEPROM

Figure 4. System Architecture using CAN−FD and M−LVDS

BOOST

MCU

BUCK

Invertor +

M−LVDS

transceiver

HB

function

Rx/Tx

UART over

M−LVDS

NCV78343

(slave)

CAN

A/B

Address

I2C

resistor

EEPROM

divider

To BCM

LB

function

Rx/Tx

NCV78343

(slave)

A/B

Address

I2C

resistor

EEPROM

divider

TI

function

Rx/Tx

NCV78343

(slave)

A/B

Address

I2C

resistor

EEPROM

divider

Figure 5. System Architecture using M−LVDS only

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NCV78343

The advantage of sharing common heatsink for higher

currents can be reached by placement of the NCV78343

together with the LEDs on same PCB (IMS type of board

supported). This is not necessary for lower currents or

application where the LED string is connected over two

NCV78343 devices.

C2P

SUB

C2N

SUB

NC

TST1

TST

SW10

12 V

SUB

SW30

SW11

SW12

SW13

SW20

SW21

SW22

SW23

NC

12 V

SUB

SW31

SW32

SW33

SW40

SW41

SW42

SW43

NC

12 V

SUB

12 V

SUB

SDA

SCL

ADR

VDD

GND

A

RX

TX

SUB

A

B

NC

VBB

B

Figure 6. ESD Protection Schematic

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6

NCV78343

Typical Switch Resistance

350

300

250

200

150

100

50

T = −45°C

T = 25°C

T = 150°C

0

1

2

3

4

5

6

7

8

9

10

11

12

Switch

Figure 7. Typical Switch Resistance

Typical Switch Section Resistance

800

700

600

500

400

300

200

100

T = −45°C

T = 25°C

T = 150°C

0

1

2

3

4

Switch section

Figure 8. Typical Switch Section Resistance

SWx(y+3)

SW_IGND(z+3)

SW(z+2)

SWx(y+2)

SW_IGND(z+2)

SW(z+1)

SWz

SWx(y+1)

SWxy

SW_IGND(z+1)

SW_IGNDz

Figure 9. Pixel Switches

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NCV78343

Table 3. ABSOLUTE MAXIMUM RATINGS

Characteristic

Battery Supply voltage (Note 1)

Symbol

Min

−0.3

−1.8

−0.3

−50

Max

60

Unit

V

BB

DD

Low voltage supply (Note 2)

V

3.6

60

V

High voltage control IO pins (Note 3)

High voltage IO pins (Note 4)

I

V

OHV60

I

68

V

OHV

OMV

Medium voltage IO pins (Note 5)

Medium voltage IO pins: M−LVDS (Note 6)

Low voltage IO pins (Note 7)

I

6.5

4

V

I

V

OMV_MLVDS

I

3.6

12

V

OLV

Low voltage supply for switch control: V2 = C2P – C2N

Switch differential voltage (Note 8)

Storage Temperature (Note 9)

V

2

V

SWxx_DIFF

T

strg

150

+2

°C

kV

Electrostatic discharge on component level Human

Body Model (Note 10)

V

−2

ESD_HBM

Electrostatic discharge on component level Charge

Device Model (Note 10)

V

−500

+500

V

ESD_CDM

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Absolute maximum rating for pins: VBB

2. Absolute maximum rating for pins: VDD

3. Absolute maximum rating for pins: RX, TST

4. Absolute maximum rating for pins: C2P, C2N, SWxy for x={4÷1} & y={3÷0}

5. Absolute maximum rating for pins: TX

6. Absolute maximum rating for pins: A, B

7. Absolute maximum rating for pins: TST1, ADC0/SDA, ADC1/SCL, ADC2/ADR

8. Absolute maximum rating for pins: SWx_(y+1) – SWxy for x={4÷1} & y={2÷0}

9. For limited time up to 100 hours. Otherwise the max storage temperature is 85°C.

10.This device series incorporates ESD protection and is qualified per AEC−Q100:

ESD Human Body Model Classification level H1C in according to the AEC−Q100−002 Rev−E

ESD Charge Device Model Classification C2b in according to the AEC−Q100−011 Rev−D

Latch*up Current Maximum Rating: v100 mA in according to the AEC−Q100−004 Rev−D JEDEC−Class II

Operating ranges define the limits for functional

operation and parametric characteristics of the device. A

mission profile (Note 11) is a substantial part of the

operation conditions; hence the Customer must contact

onsemi in order to mutually agree in writing on the allowed

missions profile(s) in the application.

Table 4. RECOMMENDED OPERATING RANGES

Characteristic

Battery supply voltage

Symbol

Min

4.5

0

Typ

Max

40

Unit

V

BB

SW_DIFF

Switch differential voltage

LED string voltage

V

10

V

0

60

V

STRING

Buck switch output current

PXN communication speed

Ambient temperature

I

1.4

A

SW

S

125

−40

1000

125

150

kbit

°C

PXN

T

A

Junction temperature range (Note 12)

T

J

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

11. The circuit functionality is not guaranteed outside the Operating junction temperature range. A mission profile describes the application

specific conditions such as, but not limited to, the cumulative operating conditions over life time, the system power dissipation, the system’s

environmental conditions, the thermal design of the customer’s system, the modes, in which the device is operated by the customer, etc.

12.The circuit functionality is not guaranteed outside the junction temperature range. Also please note that the device is verified on bench for

operation up to 170 °C but the production test guarantees 150 °C only.

Table 5. THERMAL RESISTANCE

Characteristic

Package

Symbol

Min

Typ

Max

Unit

Thermal resistance junction to exposed pad (Note 13)

SSOP36−EP

Rthjp

3.5

°C/W

13.Includes also typical solder thickness under the Exposed Pad (EP).

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NCV78343

ELECTRICAL CHARACTERISTICS

NOTE: All Min and Max parameters are guaranteed over full junction temperature (T ) range (−40 °C; 150 °C), unless

JP

otherwise specified.

Table 6. CURRENT CONSUMPTION

Characteristic

Symbol

Conditions

Min

Typ

19

Max

25

Unit

mA

The VBB current consumption

I_VBB

The VBB current consumption

UART only device

I_VBB_M−LVDS_

M−LVDS off; OTP bit M−LVDS_OFF = ‘1’

6.5

10

OFF

Table 7. OSC20M: SYSTEM OSCILLATOR CLOCK

Characteristic

Oscillator output frequency (trimmed)

Oscillator duty cycle

Symbol

OSC_CLK

OSC_DC

Conditions

Min

Typ

20

Max

21.8

70

Unit

MHz

%

18.2

30

50

Table 8. VDD: 3.45V LOW VOLTAGE ANALOG AND DIGITAL SUPPLY

Characteristic

Symbol

VDD

Conditions

VBB > 4.5 V

Min

3.15

40

Typ

Max

3.6

Unit

V

VDD regulator output voltage

VDD regulator current limitation

OUT_OFF_REG comparator voltage

VDD POR threshold, VDD rising

VDD POR threshold, VDD falling

VDD POR hysteresis

3.45

VDD_ILIM

300

3.45

2.95

2.75

0.3

mA

V

V_OUT_OF_REG

POR3V_H

2.7

2.5

0.1

3.8

3.7

0.05

12.5

15

V

POR3V_L

V

POR3V_HYST

POR_VBB_H

POR_VBB_L

POR_VBB_HST

OTP_UV

0.2

0.1

V

VBB POR threshold, VBB rising

VBB POR threshold, VBB falling

VBB POR hysteresis

4.3

V

4.2

V

0.25

15

V

OTP UV comparator threshold (VBB pin)

VBB supply during the OTP zapping

VBB current limitation for OTP zapping

V

VBB_ZAP

30

V

IBAT_ZAPP

85

mA

Table 9. SWITCH CONTROL

Characteristic

Symbol

CCH _UVH

CCH_UVL

Conditions

Min

2.65

2.6

2

Typ

2.75

2.72

Max

2.85

15

Unit

V

V(C2) under voltage threshold, V(C2) rising

V(C2) under voltage threshold, V(C2) falling

Current from VBB to charge C2 capacitor

Current limitation from VDD (during start−up)

Current limitation from VDD

V

CCH_IBB

mA

mV

V

CCH_ILIM_RST

CCH_ILIM

6

12

20

8

16

Voltage drop between VDD and V(C2)

CCH_VDROP

CCH_V2

120

3.33

270

V(C2) voltage after recharge

CCH_V2 = VDD – CCH_VDROP

Switch OFF time

SOF_TRISE

5 mA, without decoupling

capacitor

1.5

1.6

2.5

μs

Switch gate voltage detection threshold

Switch Short detection voltage threshold

Switch Overvoltage detection threshold

SOF_VTH_A

SOF_VTH_C

SOF_VTH_H

SSH_VTH

At ambient temperature

At cold temperature

At hot temperature

0.4

0.9

0.2

0.35

10

0.8

1.3

0.8

1.6

1.7

1.2

1

V

SOV_TH

13.5

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NCV78343

Table 10. PIXEL SWITCHES

Characteristic

Symbol

Conditions

At ambient

Min

Typ

0.43

0.2

Max

1.1

0.6

70

Unit

W

RON from SWx3 to SWx0 pin (3 switches)

RON from SWxy to SWx(y−1) pin (1 switch)

Current from SWxy pin to GND (see Figure 9)

SW_3R

SW_1R

W

SW_IGND

40

53

μA

Table 11. ADC FOR MEASURING VBB, VDD, VLED, TEMP, ADC_X

Characteristic

ADC Resolution

Symbol

ADC_RES

ADC_INL

Conditions

Min

Typ

Max

Unit

Bits

LSB

%

8

Integral Non−linearity (INL)

Differential Non−linearity (DNL)

Full path gain error

Best fitting straight line method

VBB, VDD measurements

−1.5

−2.0

−3.25

−2

+1.5

+2.0

3.25

2

ADC_DNL

ADC_GE

Offset at output of ADC

Time for 1 SAR conversion

ADC_OFFSET

ADC_CONV

ADC_VBB

LSB

μs

6.67

33.5

8

10

ADC full scale for VBB

measurement

35

36.5

V

ADC full scale for VDD

measurement

ADC_VDD

ADC_VLED

ADC_ADCx

3.87

63.6

4

4.13

68.6

V

ADC full scale for VLED

measurement

66.1

1.205

ADC full scale for ADCx

measurement

1.175

1.235

ADCx input current

TSD threshold level

I_ADCx

0.3

1

1.7

μA

°C

ADC_TSD

ADC measurement of junction

temperature

163

170

177

Accuracy of temperature meas at

hot

ADC_TEMP_ACC_HOT

ADC_TEMP_ACC_COLD

T = 155 °C

−7

7

°C

Accuracy of temperature meas at

cold

T = −40 °C

−15

15

Table 12. GND LOSS DETECTION

Characteristic

Symbol

Conditions

Min

Typ

120

800

Max

160

Unit

mV

ns

GND loss comparator threshold; both edges

GNDLOSS_THR

GNDLOSS_DEL

100

GND loss comparator delay; both falling and

rising edge

1200

Table 13. UART INTERFACE: RX, TX

Characteristic

High−level input voltage

Low−level input voltage

Input voltage hysteresis

Symbol

Conditions

Min

Typ

Max

Unit

V

RX_VIH

RX_VIL

2

0.8

400

160

V

RX_VIhyst

100

40

200

mV

kW

V

Input pull−down resistance

High−level output voltage

RX_RPULL

TX_VOH

I

= −3mA

2.1

VDD or external

LOAD

pull−up voltage

Low−level output voltage

TX pin leakage current in HiZ

TX pin capacitance

TX_VOL

TX_ILEAK

TX_C

I

= 3mA

0.4

1

V

LOAD

−1

μA

pF

ns

5

Propagation delay

TX_DL_50pF

TX_DL_200pF

C

up to 50 pF

40

LOAD

Propagation delay

C

up to 200 pF

150

LOAD

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NCV78343

Table 14. M−LVDS INTERFACE: A, B

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

Differential output voltage magnitude

M−LVDS_TX_VAB

Rload_A−B = 49.9 W 1%

Vtest = from −1 V to 3.4 V

480

650

mV

Change in Differential output voltage

magnitude between logic states

M−LVDS_TX _DVAB

Rload_A−B = 49.9 W 1%

Vtest = from −1 V to 3.4 V

−50

50

mV

Steady state common mode output

voltage

M−LVDS_TX _VOS

M−LVDS_TX _DVOS

Rload_A−B = 49.9 W 1%

1

1.2

1.4

50

V

Change in Steady state common

mode output voltage between logic

states

Rload_A−B = 49.9 W 1%

−50

mV

Peak−to−peak common−mode output

M−LVDS_TX _VOSPP

M−LVDS_TX _VOC

M−LVDS_TX _IOS

M−LVDS_TX _VPH

M−LVDS_TX _VPL

Rload_A−B = 49.9 W 1%

Rload w 1.62 kΩ

150

2.28

43

mV

V

voltage

Maximum steady−state open−circuit

output voltage

1.9

Short−circuit output current

magnitude

Vtest = from −1 V to 3.4 V

VSS = 2·VAB

mA

VSS

Voltage overshoot, low−to−high level

output

1.2

Voltage overshoot, high−to−low level

output

VSS = 2·VAB

−0.2

Differential Output rise and fall times

Transmitter Propagation delay

M−LVDS_TX _TE

M−LVDS_TX _TP

M−LVDS_RX_VITP

5

12

20

ns

5

10

Positive−going Differential Input

voltage Threshold for BUS common

mode <0; 3.8> V

150

mV

Positive−going Differential Input

voltage Threshold for BUS common

mode <−1.4; 0> V

M−LVDS_RX_VITP_NCMM

M−LVDS_RX _VITN

160

mV

Negative−going Differential Input

voltage Threshold for BUS common

mode <0; 3.8> V

50

60

Negative−going Differential Input

voltage Threshold for BUS common

mode <−1.4; 0> V

M−LVDS_RX

_VITN_NCMM

Receiver Propagation delay

A or B pin capacitance

M−LVDS_RX _TP

M−LVDS_C

20

40

5

60

20

ns

pF

μA

Transceiver input current in high

impedance state (range 1)

M−LVDS_IOZ_1

0 V v (VA or VB) v 2.4 V,

other output at 1.2 V,

transmitter in HiZ

−20

Transceiver input current in high

impedance state (range 2)

M−LVDS_IOZ_2

−1.4 V v (VA or VB) v 0 V

−32

32

μA

or

2.4 V v (VA or VB) v 3.8 V,

other output at 1.2V,

transmitter in HiZ

Table 15. I2C INTERFACE: SDA, SCL

Characteristic

High−level input voltage

Low−level input voltage

Input voltage hysteresis

Low−level output voltage

High−level output voltage

SDA or SCL pin capacitance

Symbol

I2C_VIH

I2C_VIL

I2C_VIhyst

I2C_VOL

I2C_VOH

I2C_C

Conditions

Min

Typ

Max

Unit

VDD

mV

V

0.7

0.3

700

0.4

300

5

I

= −3 mA

VDD−0.1

V

LOAD

I

= 3 mA

5

pF

LOAD

SCL to SDA and SDA to SCL propagation

delay, both edges

I2C_DL

60

ns

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11

NCV78343

DETAILED OPERATING AND PIN DESCRIPTION

SUPPLY CONCEPT IN GENERAL

INTERNAL CLOCK GENERATION

Low operating voltages become more and more required

due to the growing use of start stop systems. In order to

respond to this necessity, the NCV78343 is designed to

support power−up starting from VBB = 4.5 V.

The clocks are fully internally generated without the need

for any trimming by the user. The accuracy is guaranteed

under all operating conditions and independent of external

component selection.

OSC20M Clock

The OSC20M clock is the system clock. All the internal

timings as well as the internal PWM unit depend on

OSC20M accuracy.

VBB

VDD

Communication Clock

The internal clock is also used for oversampling of UART

incoming frame and I2C EEPROM, so there is no need for

any external clock.

POR

DIMMING CONTROLLER

Internal (built−in) dimming controller allows change of

light intensity of individual LEDs in LED string by means

of digital (PWM) dimming.

VLED

Dimming Control Parameters

time

The dimming for all switches is controlled from 1

common 10−bit counter. The ON and OFF events are

programmable per channel, each with a 10 bit counter value.

100% duty cycle is generated when ON time is set to min.

value (0) and OFF time is set to max value (1023).

0% duty cycle is generated when ON time is equal to OFF

time. When more than one 0% or 100% duty cycle is

required, the TR (transition) slots must be used.

≥300μs

Figure 10. Power−up Sequence

A specific power−up and power−down sequences are

shown in the Figure 20 and Figure 21.

There is no special circuit to disable switches in case of

VBB power supply disconnection. The gate of the switch is

discharged by SW−OFF circuit in case the VBB−LOW

threshold is crossed. The gate of the switch is discharged by

leakage currents when the supply is suddenly lost. Because

of low leakage currents, the switch may stay enabled for a

few seconds after power lost. Possible temperature rise

speeds up opening the switch by higher leakage current.

The dimming frequency is the DIMCLK frequency

divided by 1024. The T

is the duration of one PWM

DIMCLK

tick. The duration of one PWM period is T

required time for one switch ON sequence is T

. The

PWM

SW_SEQ

ratio of T

and T

results in number of PWM

SW_SEQ

DIMCLK

ticks required for one switch ON sequence. The number of

slots available for each DIMCLK is 1024 divided by the

ratio. The recommended time for TR slots and

recommended step between each switch ON request is

shown in Table 43. When the TR slot technique is used, the

ON values should not be set within this period.

VDD Supply

The VDD supply is the low voltage digital and analog

supply for the chip, which is powered from VBB. VDD is

supplying the internal analog and digital circuits as well as

external components like I2C EEPROM and resistor divider

on ADC inputs. The POR−circuit is monitoring both the

VBB and VDD voltages.

Dimming Mode

The NCV78343 incorporates two modes of operation –

ON/OFF dimming mode and direct mode.

VLED Supply

• ON/OFF mode – the NCV78343 controls the dimming

duty cycle and phase shift for each switch individually.

The time of ON event is set by means of <ONx[9:0]>

register and the time of OFF event is set by means of

<OFFx[9:0]> register.

• Direct mode – in addition to ON/OFF dimming mode,

the state of the switches can be controlled directly by

means of <SWx> register.

If the device is running but the LED current source is

disconnected, the LEDs can light up because of the bias

currents flowing through pins of the switches. Up to 180 mA

(typical) from switch current source may cause the

bottom−most LED to shine. If needed, resistors can be

connected in parallel to the switches to avoid undesired LED

lighting (typically 10 kW).

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12

NCV78343

Common

Counter

OFF(1) [10]

ON(2) [10]

ON(1) [10]

OFF(2) [10]

OUT1

OUT2

Figure 11. Dimming Operation (dimming ON/OFF event)

Dimming Transition Vector Insertion

PWM dimming clock

Transition vectors are required in case of pattern changes

(update of dimming settings) for avoiding multiple

switching events at the same time and minimizing

brightness error.

Selection of internal dimming clock is done by means of

<DIMFREQ[4:0]> register, which shall be used to select

dimming frequencies in range of 125 kHz to 1 MHz (see

Table 43. PWM Frequency Settings).

Fully closed switch (100% duty cycle) requires ON event

equal to 0. It can happen that such switch ON event is

required on more switches at the same time, which is not

allowed. Therefore a transition slot technique is used for

consecutive activation of those switches (which need to be

changed to 100% duty cycle). When overlapping multiple

switch ON events are invoked despite this, the <DIMERR>

error is raised. When overlapping switch OFF events occur,

the <DIMWARN> status bit is set and processing of this

pattern continues. However, multiple switch OFF events

may cause large LED string voltage changes.

Transition vector inserts additional transition either ON or

OFF event at the beginning of next PWM period (in

transition slots space). This helps to reduce brightness error

significantly and the duty cycle is affected only in one

period. The error is proportionate to duration of transition

slot.

SWITCH CONFIGURATIONS

The 12 integrated switches are typically organized as

12 × 1 switch of 1.4 A, but can be organized in 6 × 2 switches

in parallel to offer 6 × 1 switch of 2.8 A. Examples of switch

configurations are shown in Figure 12.

Selection of the switch configuration is done by

<CONF_SEL[2:0]> register. Detailed information about

switch configuration is available in Table 16.

Table 16. SWITCH CONFIGURATIONS

Conf.

CONF_SEL

Code

Name

[2:0]

Description

000

001

010

1, 2, 3, 4

1+2, 3, 4

1+2, 3+4

12 × PWM channels

9 × PWM channels (PWM 1=2)

6 × PWM channels (PWM 1=2 &

3=4)

Pattern is updated when common PWM counter

overflows and <MAPENA> = ‘1’ (see Table 64) is set.

The NCV78343 contains 12 channels, so with unique

settings of <TRx[3:0]> for each switch 12 different

Transient Vector values are needed in the worst case (“0x0”

to “0xB”). When <TRx[3:0]> = ‘0xC’, ‘0xD’, ‘0xE’ or

‘0xF’, the <TRx[3:0]> is ignored and transition vectors are

not applied. In this case the switch status from previous

PWM period is kept unchanged until next ON or OFF event

into opposite direction.

011

100

101

1, 2+3, 4

1, 2, 3+4

1+4, 2+3

9 × PWM channels (PWM 2=3)

9 × PWM channels (PWM 3=4)

6 × PWM channels (PWM 1=4 &

2=3)

110

111

1+4, 2, 3

1, 2, 3, 4.

9 × PWM channels (PWM 1=4)

Same as 0000, 12 × PWM

channels

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13

NCV78343

In case of configurations with 2× current, PWM signals of

sections with higher index are controlled with PWM signals

from lower index section. For example in case of

configuration “101”, the PWM signals of section 1 is

controlling section 4; control signals of section 2 is

controlling section 3.

I_DR

SW43

SW42

SW41

SW40

I_DR

4

3

4

3

4

3

4

3

4

3

SW32

SW31

SW30

2

1

2

1

2

1

2

1

2

1

SW22

SW21

SW20

SW12

SW11

SW10

Config 1+2, 3+4

2x current

2 strings of 3 Pixels

Config 1+2,3+4

Config 1,2,3,4

1 string of 12 Pixels

1 LED per Pixel

Config 1,2,3,4

2 strings of 6 Pixels

Max 2 LED per Pixel

Config 1,2,3,4

4 strings of 3 Pixels

Max 2 LED per Pixel

2x current

1 string of 6 Pixels

Max 2 LED per Pixel

Figure 12. Example of Switch Configurations

Analog Input

Parallel combination is used where the I

current

DR

The analog input AIN is an input channel that can be used

for different types of measurements, like e.g. LED

temperature or battery voltage. The converted voltage is

calculated with the following formula:

exceeds maximum switch current 1.4 A. This is not for use

in redundant applications.

The following consequence must be taken into account

when using parallel switches:

The OTP safe−state bits should be zapped to “0” to avoid

sequentially switching ON which might cause that the

higher current will flow through one switch.

1.205

V_ADC+ ADC_RES_X

@

[V]

x

[7:0]

(eq. 1)

255

where

ADC_RES is saved in register 0x11

X

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14

NCV78343

OPEN, SHORT and FAIL Status Detection

OPEN det.

NOK

SHORT det.

det

.

Switch state

PWM clock

SW_OFF

SW_ON

SW_OFF

Figure 13. OPEN, SHORT and FAIL Status Detection Timing

Following the figure above, the OPEN and SHORT flags

are detected only during the switch OFF state. The On/Off

Failed flag detection is triggered by the transition between

the switch ON and the switch OFF event. The SHORT and

On/Off Failed status flags are cleared upon a successful read

out of register 0x0F. Due to this behavior and the diagram

above, the read status might alternate between the SHORT

and On/Off Failed, following the duty cycle of the specific

switch. When the buck current is disabled, the device reports

SHORT status for all switches.

Init

SW_DIR:

NORMAL DIRECT

NO_CRC DIRECT

Event: MAPENA PWM

Event: MAPENA DIRECT

SW_ON_OFF:

NORMAL PWM

NO_CRC PWM

Event: FAIL_SAFE_STATE

Event: MAPENA DIRECT

Event: MAPENA PWM

Event: FAIL_SAFE_STATE

SW_FAIL_SAFE:

Fail-safe OTP

Fail-safe OPEN

NOTE: MAPENA DIRECT means writing into REG 0x00. MAPENA PWM means either writing into REG 0x0D or sending CF15.

Figure 14. Normal Mode State Machine

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15

NCV78343

Pixel Light Network

The LED matrix head light system can be integrated into

a superior system through an optional physical interface, e.g.

differential low speed CAN. The choice of the external

physical interface is application specific.

The PXN is a proprietary network technology developed

primarily for communication with and within the LED

matrix head light system (see Figure 15).

The LED matrix head light system may incorporate a

various number of sub−systems interconnected using PXN

technology. The connection of such sub−system to a local

network is realized using M−LVDS physical interface and a

twisted−pair cable. Termination is required at both ends of

the twisted−pair cable. Nominally, it is 100 W across the pair.

Transmitter on the bus sees both termination resistors in

parallel, thus the nominal bus load is actually 50 W.

The PXN protocol for communication over PXN is based

on UART communication standard, i.e. one start bit, 8 data

bits (LSB first), one stop bit, no parity bit.

Rx pin is 5 V tolerant and has CMOS compatible threshold

levels. External pull−up resistor is required on Tx pin.

Figure 15. PXN Topology Inside LED Matrix Head Light System

Table 17. THE UART SIGNAL LEVELS TRANSFERRED TO M−LVDS BUS

UART RX Input Pin

M−LVDS Differential Voltage A−B

POSITIVE (A−B > 150 mV)

UART TX Output Pin

LOW

HIGH

LOW

HIGH

NEGATIVE

(A−B < 50 mV; in M−LVDS push−pull mode;

valid for repeater−slave)

PXN Frame

The table above must be taken into account when using

only M−LVDS slaves cluster. The master MCU generates

UART signal, which is connected to the M−LVDS

transceiver, where the A and B pins are connected to the A

and B pins on the devices. Since the M−LVDS signal is

inverted to the UART signal, there must be placed an

invertor on the Tx pin from the MCU to M−LVDS

transceiver and another invertor on the Rx pin from the

M−LVDS transceiver to the MCU.

A message is transferred over PXN bus in a form of PXN

frame, which is depicted in Figure 16. The PXN protocol for

communication over PXN is based on UART

communication standard, i.e. one start bit, 8 data bits (LSB

first), one stop bit, no parity bit.

The PXN frame consists of a header and a response. The

header is always transmitted by PXN master while the

response can either be transmitted by master, in case of write

frames or by slave, in case of read frames. The header and

the response are separated by in−frame response space.

The header consists of a BREAK field (logic 0 for a

certain time), a SYNC field (0x55 byte) and two protected

identifiers PID1 and PID2. The response consists of an

arbitrary number of DATA bytes within a range from 1 to 12

followed by CRC. The particular bytes are separated by

inter−byte space. Minimal delay of 1 Tbit is required before

starting new PXN frame. The minimum length for the

BREAK field is 13 Tbits (52 ms for the default

PXN Switch

The PXN switch is responsible for PXN frame routing

within a particular PXN node connected to network.

PXN Media Access Layer

The MAC layer is responsible for a PXN frame

composition on a transmitting side, the PXN frame

decomposition on a receiving side, a transmission of

composed PXN frames, a reception of PXN frames and PXN

network error detection and confinement.

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16

NCV78343

communication speed 250 kbps). The BREAK field stop bit

slave cluster, the DE pin on the M−LVDS transceiver (e.g.

NBA3N206S) must be set LOW within 1 Tbit after the

Header part to allow device response.

(BREAK field delimiter) is minimum 1 Tbit and maximum

according to the selected watchdog time. If the device is not

responding through the repeater−slave, the extended break

(26 Tbits) can be required to recover communication to

slave devices. Such case can occur when Read frame is

addressed non assigned address. In case of only M−LVDS

The PXN protocol supports two frame types:

− configuration frame

− register bank frame

– PXN write frame – TX by master

– PXN read frame – TX by slave

≥ 1

RESPONSE

HEADER – always transmiꢀtted by master

Tbit

PID1

PID2

DATA 1

DATA N

CRC

Break Field

Sync Field

PID1 Byte

PID2 Byte

Data byte 1

Data byte N

CRC byte

Figure 16. PXN Frame

PXN Configuration Frame

The configuration PXN frame allows activation and

monitoring of selected configuration service.

FT [1:0]

2−bit frame type:

“00” – read frame

“01” – write frame to address node only

“10” – write frame to all nodes (broadcast)

Table 18. PXN CONFIGURATION FRAME

SA [4:0]

5−bit slave node address

Contents

Bit Bit Bit Bit Bit Bit Bit Bit

PID2:

7

P

6

1

0

5

1

0

4

3

2

1

0

Byte

Name

P

odd parity bit

0

PID1

SA[4:0]

CSID[4:0]

BC[1:0]

RBA[4:0]

DATAx[7:0]

CRC[7:0]

2−bit byte count

1

PID2

5−bit register bank address

8−bit data, from 1 up to 12 data bytes supported

8−bit CRC

2..13 DATAx

DATA[7:0] 0 ..11

CRC[7:0]

3

CRC

PID1:

P

odd parity bit

PXN Register Bank Frame Matched by Length

The PXN network supports devices with different logical

organization of internal register bank. The following logical

organizations of register bank are supported:

SA [4:0]

5−bit slave node address

PID2:

P

TYPE1

TYPE2

TYPE3

− up to 32x24 bits

− up to 32x16 bits

− up to 32x8 bits

odd parity bit

CSID[4:0]

DATAx[7:0]

CRC[7:0]

5−bit configuration service identifier

8−bit data, from 1 up to 12 data bytes supported

8−bit CRC

Each of types above has predefined number of data bytes

for given PID2.BC parameter in case PID1.FT=”10”

(broadcast frame).

PXN Register Bank Frame

The register bank PXN frame provides an access, both

read or write to selected register(s) of internal register bank.

Table 20. BROADCAST PXN FRAME DATA BYTE

COUNT

Data Byte Count

Table 19. PXN REGISTER BANK FRAME

TYPE1

TYPE2

TYPE3

PID2.BC[1:0]

Contents

0x0

3

6

2

4

1

5

Bit Bit Bit Bit Bit Bit Bit Bit

0x1

0x2

0x3

7

P

6

5

4

3

2

1

0

Byte

Name

9

8

7

0

PID1

FT[1:0]

BC[1:0]

SA[4:0]

RBA[4:0]

12

10

11

1

PID2

2..13 DATAx

DATA[7:0] 0 ..11

CRC[7:0]

The NCV78343 supports only the TYPE1 register bank

organization, since each register bank consists of 3 bytes.

This means that it is possible to read/write up to 4 registers

in one frame, which can be for example used to write

ON/OFF times for all 12 switches in only 3 PXN frames.

3

CRC

PID1:

P

odd parity bit

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17

NCV78343

PXN Error Detection

and M−LVDS bus. It forwards frames from UART to

The PXN network supports detection of these errors:

− frame error

− timeout error

− synchronization error

− local communication error

− global communication error

M−LVDS and back from M−LVDS to UART when reading

from a slave device.

Addressing Options

It is possible to set a device address in 3 different ways:

− Multi−level address pin

− Auto−addressing procedure

− OTP node address bits

PXN Application Layer

Addressing using OTP memory is recommended for final

application. Some of the other device parameters are saved

in memory as well, which speeds up device setup after each

power−on.

List of supported configuration services:

Table 21. CONFIGURATION SERVICES

Configuration

Service

Configuration Frame

Multi−level Address Pin

Name

Code Name CSID Type Description

The PXN node address can be determined by connecting

ADC2/ADR input to a voltage divider. The voltage divider,

represented by resistors R1 and R2 are supplied from

regulated 3.3 V VDD supply. The voltage space is divided

into 10 ranges where only 8 of them are associated with valid

address. The corresponding thresholds are calculated as

follows:

Identification

0

1

CF0

CF1

0x00

0x01

R

Slave Identification

Write data to ext. I2C

EEPROM

W

Request data from ext.

I2C EEPROM

Ext.

EEPROM

CF2

CF3

CF4

0x02

0x03

0x04

W

R

Read Data from ext.

I2C EEPROM

Enable/disable auto−

addressing mode

W

Table 23. MULTI−LEVEL ADDRESS PIN

Auto−addres

2

3

CF5

CF6

0x05

0x06

W

R

Assign address

OP mode status

sing

PXN

Resistor Divider

R1 (kΩ) R2 (kΩ)

91 27

ADC2/VDD

min. (−)

Addr

max. (−)

0.79

0.63

0.49

0.38

0.29

0.21

0.15

0.09

Slave/repeater−slave

PXN mode selection

7

6

5

4

3

2

1

0

0.75

0.59

0.46

0.35

0.27

0.20

0.14

0.08

CF7

0x07

W

PXN mode

68

91

82

91

51

82

51

15

CF8

CF9

0x08

0x09

R

Read PXN mode status

Write data to OTP

W

10

Request data from

OTP

CF10 0x0A

CF11 0x0B

CF12 0x0C

W

R

OTP

4

5

8.2

3.3

3.6

1.3

Read data from OTP

Set UART

communication speed

UART

W

CF13 0x0D

CF14 0x0E

W

Switch to normal mode

Reset system

In case of valid address the node can process both the

addressed and the broadcast frames. In case of invalid

address the node can process the broadcast frames only.

System

6

Trigger MAPENA and/

or CNTRST

CF15 0x0F

W

List of supported register bank access:

VDD

R1

Table 22. REGISTER BANK ACCESS

Configuration

Service

Configuration Frame

Name

Code Name Access Type Description

WF1

RF1

Read

Write

Write register bank

Read register bank

Read/Write

0

ADC2/ ADDR

R2

PXN Communication Modes

The PXN node can operate in one of the two

communication modes:

− slave mode

Figure 17. Voltage divided connected to

ADC2/ADR Pin

− repeater−slave mode

The Multi−level addressing procedure requires stable

voltage level at ADC2/ADR pin in 200 ms after POR. If the

application cannot ensure this time, please follow the

Depending on the mode selected, the PXN switch is

configured to route the PXN frames the respective way. The

repeater−slave device works as a bridge between UART bus

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18

NCV78343

Multi−level addressing procedure with long time delay

8

Fail safe state of LEDs in string 1

Fail safe state of LEDs in string 2

Fail safe state of LEDs in string 3

Fail safe state of LEDs in string 4

PXN lock bit

recommendation in Application notes. If the Multi−level

addressing is successful, a device stays in the OTP config

mode (see Figure 23).

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

Auto−addressing Procedure

Regardless the node address assigned after the

measurement of ADC2/ADR multi−level input, the

auto−addressing procedure can still be invoked using the

auto−address enable PXN frame. The auto−addressing is

enabled/disabled on the PXN node upon receiving CF4 PXN

configuration frame. The CF4 frame is accepted in the

OTP_CONFIG mode only (see Table 53).

The PXN node address, when auto−addressing is enabled

is assigned upon receiving CF5 PXN configuration frame.

The CF5 frame is accepted in AUTO_ADDR mode only

(see Table 54).

Mode (slave/repeater−slave)

Communication speed bit 0

Communication speed bit 1

Global bit error detection disable

M−LVDS OFF

UART OFF

EEPROM lock bit (write protect)

CRC bit0

CRC bit1

CRC bit2

The auto−addressing procedure is described in the

APPLICATION RELATED INFORMATION section.

CRC bit3

CRC bit4

OTP Node Address

CRC bit5

The OTP node address can be zapped by customer at EoL

(End of Line) after the PXN node address was determined

either by means of multi−level address pin measurement or

by means of auto−addressing procedure. The value of OTP

node address and OTP bank lock bit is obtained each time

the PXN node is powered up and the custom OTP bank is

read out. Loading of other device settings from OTP

memory speeds up device setup after power−on. OTP

memory zapping is necessary to fulfil ASIL B safety

requirements.

CRC bit6

<OTP_LOCK_BIT> − custom OTP bank general lock bit.

When zapped, any further zapping attempt of custom OTP

bank is declined.

<OTP_NODE_ADDR_LOCK_BIT> − PXN node address

lock bit. When zapped, any further zapping attempt of

<OTP_NODE_ADDR> bits of custom OTP bank is

declined.

<OTP_NODE_ADDR [4:0]> − 5−bit PXN node address.

This address is taken into account only when the

<OTP_NODE_ADDR_LOCK_BIT> is zapped.

PXN Communication Speed

The PXN node can communicate at following speed:

− 125 kb/s

− 250 kb/s (default)

− 500 kb/s

− 1 Mb/s

Communication speed is changed upon receiving CF12

PXN communication frame in OTP_CONFIG,

AUTO_ADDR and NORMAL modes only (see Table 61).

<FAIL_SAFE_STATE_LOCK_BIT> − fail safe state of

LED string lock bit. When zapped, any further zapping

attempt of <FAIL_SAFE_STATE_LED_STRINGx> bits of

custom OTP bank is declined.

<FAIL_SAFE_STATE_LED_STRINGx> − state of the

LED string x, x={1,2,3,4}, in case one of the following

conditions is detected:

• NORMAL mode is entered or

• Timeout error occurred

OTP Bank – Custom Data

The custom OTP bank is typically zapped by customer at

EOL and stored values are used for system operation

customization.

The bits set directly the switch state. The fail safe state is

taken into account only when

Table 24. OTP BANK

<FAIL_SAFE_STATE_LOCK_BIT> is zapped.

OTP#

OTP Name

0

1

2

3

4

5

6

7

OTP lock bit

<PXN_LOCK_BIT> − PXN settings lock bit. When

zapped, any further zapping attempt of PXN settings related

bits of custom OTP bank is declined.

OTP node address lock bit

OTP node address bit 0

OTP node address bit 1

OTP node address bit 2

OTP node address bit 3

OTP node address bit 4

Fail safe state lock bit

<PXN_MODE> − PXN communication mode selection bit.

Set ‘0’ for slave mode and ‘1’ for repeater−slave mode. The

mode selection is taken into account only when the

<PXN_LOCK_BIT> is set and the CRC is correct.

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NCV78343

OTP Memory Zapping

<PXN_COMMUNICATION_SPEED [1:0]> − 2−bit PXN

communication speed selection bit. The communication

speed selection is taken into account only when the

<PXN_LOCK_BIT> is set and the CRC is correct.

The OTP zapping process is one−time programming

process during which the OTP memory is written. This

process cannot be undone. The OTP zapping is possible only

in the OTP config mode. To ensure correct OTP zapping, the

VBB voltage must be in range of 16 to 30 V with the current

capability at least 85 mA during the OTP zapping process.

The OTP memory zapping should be done at the EoL to

fulfil the ASIL B requirements.

External MCU can read content of OTP memory. To do

this, device must first receive CF10 PXN configuration

frame followed by CF11 PXN configuration frame. This

process is similar to reading from external I2C EEPROM.

Table 25. PXN COMMUNICATION SPEED

COMMUNICATION_SPEED[1:0]

OTP Setting

PXN Communication

Speed [kb/s]

0x0

0x1

0x2

0x3

125

250

500

1000

The default communication speed, when the

<PXN_LOCK_BIT> is not zapped is 250 kbps.

Operating Modes

The PXN node can operate in following modes:

− OTP Config mode

<GLOBAL_BIT_ERR_DTC_DIS> − global bit error

detection disable. In case the global bit error detection is

enabled (<GLOBAL_BIT_ERR_DTC_DIS> is not zapped)

the data transmitted on chip’s TX output must be echoed

back into chip’s RX input. There are two ways to generate

the TX echo. Either it can be ensured by a CAN transceiver

connected between a chip and an MCU on UART bus or it

can be generated by the MCU itself. When the echo is not

present, chip stops transmitting and will wait for new

incoming frame. When more than one device is present on

the UART bus, the repeater−slave will always report

<PXN_GLOBAL_COMM_ERR> bit when reading from

another device on the UART bus. In case the global bit error

detection is disabled, the reading from an address not

assigned to a physical device will block the further operation

of the repeater−slave device. Such device must be

unplugged from a battery voltage in order to make it

operational again. The global bit error detection is enabled

by default.

The device configured to act as a PXN repeater−slave

shall always have the global bit error detection enabled, i.e.

<GLOBAL_BIT_ERR_DTC_DIS> shall be not zapped.

The setting of <GLOBAL_BIT_ERR_DTC_DIS> bit does

not affect the communication over M−LVDS bus. The

<GLOBAL_BIT_ERR_DTC_DIS> bit is taken into

account only when the <PXN_LOCK_BIT> is set and the

CRC is correct.

− Auto−addressing mode

− Normal Direct mode

− Normal PWM mode

− Normal Fail−safe OTP mode

− Normal Fail−safe OPEN mode

− NO_CRC Direct mode

− NO_CRC PWM mode

− Fail−safe OTP mode

− Fail−safe OPEN mode

OTP Config mode – the chip enters this mode under the

following circumstances: when the OTPs are not zapped and

the voltage divider at ADR pin is in a valid range, or the

OTPs are zapped but the OTP CRC BANK2 is wrong, or

after successful auto−addressing process. Please see the

following flow diagram ‘Flow chart after POR’ in the

Application notes.

Chip with non−zapped OTP memory starts with both UART

and M−LVDS interfaces enabled. To determine which one

will be used, there is a 60 ms timer (typical) that starts once

device enters OTP Config mode. After timer elapses, chip

reads state of UART RX pin to determine if UART bus

should remain enabled (RX pulled high) or disabled (RX

pulled low). During this period, M−LVDS devices might be

unable to communicate if their UART RX pin is pulled low.

Timer can be stopped before elapsing by leaving OTP

Config mode, typically by receiving CF13.

<UART_OFF>

−

UART interface disable. The

Auto−addressing mode – when the chip receives CF4 (see

<UART_OFF> selection is taken into account only when the

<PXN_LOCK_BIT> is set and the CRC is correct.

Table 53) configuration frame.

Normal Direct/PWM mode – this is the normal working

mode, the chip enters this mode after the POR when the

OTPs are zapped and the CRC is correct. Direct means that

the switches are controlled directly by writing to the register

0x00. The PWM means that the switches are controlled by

the PWM by writing ON and OFF values and sending CF15

(see Table 64).

<M−LVDS_OFF> − M−LVDS interface disable. The

<M−LVDS_OFF> selection is taken into account only when

the <PXN_LOCK_BIT> is set and the CRC is correct.

Unused M−LVDS transceiver can be disabled to reduce

current consumption by 12.5 mA (typical).

<EEPROM_LOCK_BIT> − external EEPROM lock bit.

The EEPROM lock bit acts as an EEPROM write protection.

When zapped, any further write attempts to external

EEPROM is declined.

NO_CRC Direct/PWM mode – the device enters the

NO_CRC mode after receiving CF13 (see Table 62) in the

OTP Config mode. The functionality of NO_CRC Direct

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20

NCV78343

and PWM modes is same as Normal Direct and Normal

node reads data from EEPROM upon receiving CF2 PXN

configuration frame (see Table 51). The EEPROM data are

stored in the internal buffer.

The PXN node provides the data, previously read from the

EEPROM and stored in the internal buffer upon receiving

CF3 configuration frame (see table 52). The EEPROM

address is valid for “1010” + <EESA> .

PWM modes. NO_CRC prefix means that the device

detected invalid CRC in OTP memory bank 2 during power

on, most likely because OTP memory is not written.

Please note that only device with written OTP memory

achieves ASIL B safety rating.

Fail−safe OTP mode – when this fail−safe state is entered

after watchdog timeout, OTP fail−safe data are loaded and

applied on switches. Chip also enters this mode after

DIMERR. To leave this mode, clear TIMEOUT or

DIMERR flags set in register 0x10.

The write and read operations are shown in the application

notes chapter (EEPROM write and read operations).

Cyclic Redundancy Check

All PXN frames are covered by an 8−bit CRC, where the

8

2

1

Fail−safe OPEN mode – this is the fail−safe state when the

switches are automatically open under the following

circumstances: TSD or CAP_UV or VBB_LOW appears.

To leave this mode, please read out the register 0x10.

polynomial is 0x83 (Koopman’s notation; x +x +x +1)

with 0xFF seed. The input bytes are bit swapped and LSB

first. The CRC is calculated over PID1, PID2 and DATAx

bytes.

The OTP bank 2 is covered by a 7−bit CRC, where the

EEPROM

polynomial

is

0x5B

(Koopman’s

notation;

The external I2C EEPROM can be connected to SDO and

SCL pins and supplied from the VDD net.

The PXN node writes data to EEPROM upon receiving

CF1 PXN configuration frame (see Table 50). The PXN

7

5

4

2

1

x +x +x +x +x +1) with 0x7F seed. The input is MSB first.

The CRC is calculated over bits 0−19.

The code examples for both CRCs are shown in the

APPLICATION RELATED INFORMATION chapter.

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21

REGISTER DESCRIPTION

Table 27. REGISTER 0x00

Register 0x00

Address

Bit 11

SW12

0

Bit 10

SW11

0

Bit 9

SW10

0

Bit 8

SW9

0

Bit 7

SW8

0

Bit 6

SW7

0

Bit 5

SW6

0

Bit 4

SW5

0

Bit 3

SW4

0

Bit 2

SW3

0

Bit 1

SW2

0

Bit 0

SW1

0

Name

Reset

0x00

Access

RW

Bit 21

−

RW

Bit 20

−

RW

Bit 19

−

RW

Bit 16

−

RW

Bit 15

−

RW

Bit 14

−

RW

Bit 13

−

RW

Bit 12

−

Address

Bit 23

Bit 22

Bit 18 Bit 17

Name

Reset

SERVICE[23:22]

−

0

−

0

0x00

Access

RW

SERVICE[1:0] – specify the behavior of the last [21:0] bits:

“00” – Direct control – Direct control of all switches all together

“01” – OPEN clear request – De−activation of selected switch in on state due to OPEN fault previously detected

“10” – Reserved

“11” – Reserved

SW[11:0] – Direct control of the switches ON/OFF or OPEN clear request:

SERVICE = “00”: direct control of the switches ON/OFF; valid SW[11:0], others are “0”.

SERVICE = “01”: OPEN clear request; Switch is chosen by valid SW_SEL[3:0] from “0001” to “1100” (Switch 1 to

12), others are “0”.

Table 28. REGISTER 0x01

Register 0x01

Bit 8 Bit 7 Bit 6

Address

0x01

Bit 11

Bit 10

Bit 9

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF1[11:4]

0

TR1[3:0]

0

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON1[23:14]

OFF1[13:12]

0

0x01

Access

RW

ON1[9:0] – 10−bit switch ON threshold.

OFF1[9:0] – 10−bit switch OFF threshold.

TR1[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

Table 29. REGISTER 0x02

Register 0x02

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF2[11:4]

0

TR2[3:0]

0

0x02

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON2[23:14]

OFF2[13:12]

0

0x02

Access

RW

ON2[9:0] – 10−bit switch ON threshold.

OFF2[9:0] – 10−bit switch OFF threshold.

TR2[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

23

Table 30. REGISTER 0x03

Register 0x03

Bit 8 Bit 7 Bit 6

Address

Bit 11

Bit 10

Bit 9

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF3[11:4]

0

TR3[3:0]

0

0x03

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON3[23:14]

OFF3[13:12]

0

0x03

Access

RW

ON3[9:0] – 10−bit switch ON threshold.

OFF3[9:0] – 10−bit switch OFF threshold.

TR3[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

Table 31. REGISTER 0x04

Register 0x04

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF4[11:4]

0

TR4[3:0]

0

0x04

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON4[23:14]

OFF4[13:12]

0

0x04

Access

RW

ON4[9:0] – 10−bit switch ON threshold.

OFF4[9:0] – 10−bit switch OFF threshold.

TR4[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

Table 32. REGISTER 0x05

Register 0x05

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF5[11:4]

0

TR5[3:0]

0

0x05

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON5[23:14]

OFF5[13:12]

0

0x05

Access

RW

ON5[9:0] – 10−bit switch ON threshold.

OFF5[9:0] – 10−bit switch OFF threshold.

TR5[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

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24

Table 33. REGISTER 0x06

Register 0x06

Bit 8 Bit 7 Bit 6

Address

Bit 11

Bit 10

Bit 9

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF6[11:4]

0

TR6[3:0]

0

0x06

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON6[23:14]

OFF6[13:12]

0

0x06

Access

RW

ON6[9:0] – 10−bit switch ON threshold.

OFF6[9:0] – 10−bit switch OFF threshold.

TR6[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

Table 34. REGISTER 0x07

Register 0x07

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF7[11:4]

0

TR7[3:0]

0

0x07

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON7[23:14]

OFF7[13:12]

0

0x07

Access

RW

ON7[9:0] – 10−bit switch ON threshold.

OFF7[9:0] – 10−bit switch OFF threshold.

TR7[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

Table 35. REGISTER 0x08

Register 0x08

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF8[11:4]

0

TR8[3:0]

0

0x08

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON8[23:14]

OFF8[13:12]

0

0x08

Access

RW

ON8[9:0] – 10−bit switch ON threshold.

OFF8[9:0] – 10−bit switch OFF threshold.

TR8[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

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25

Table 36. REGISTER 0x09

Register 0x09

Bit 8 Bit 7 Bit 6

Address

Bit 11

Bit 10

Bit 9

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF9[11:4]

0

TR9[3:0]

0

0x09

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON9[23:14]

OFF9[13:12]

0

0x09

Access

RW

ON9[9:0] – 10−bit switch ON threshold.

OFF9[9:0] – 10−bit switch OFF threshold.

TR9[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

Table 37. REGISTER 0x0A

Register 0x0A

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF10[11:4]

TR10[3:0]

0

0x0A

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON10[23:14]

OFF10[13:12]

0

0x0A

Access

RW

ON10[9:0] – 10−bit switch ON threshold.

OFF10[9:0] – 10−bit switch OFF threshold.

TR10[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

Table 38. REGISTER 0x0B

Register 0x0B

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OFF11[11:4]

0

TR11[3:0]

0

0x0B

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON11[23:14]

OFF11[13:12]

0

0x0B

Access

RW

ON11[9:0] – 10−bit switch ON threshold.

OFF11[9:0] – 10−bit switch OFF threshold.

TR11[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

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26

Table 39. REGISTER 0x0C

Register 0x0C

Bit 8 Bit 7 Bit 6

OFF12[11:4]

Address

Bit 11

Bit 10

Bit 9

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

TR12[3:0]

0

0x0C

Access

RW

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ON12[23:14]

OFF12[13:12]

0

0x0C

Access

RW

ON12[9:0] – 10−bit switch ON threshold.

OFF12[9:0] – 10−bit switch OFF threshold.

TR12[3:0] – Transition vector duration, it is prolonging the duration of ON resp. OFF value at the end of PWM period by

<TRx[3:0]> × Time slot between switch activations.

Table 40. REGISTER 0x0D

Register 0x0D

Address

Bit 11 Bit 10

Bit 9

Bit 8

Bit 7

−

Bit 6

−

Bit 5

−

Bit 4

−

Bit 3

Bit 2

Bit 1

CRC_CLR

0

Bit 0

MAPENA

0

Name

Reset

TW_CODE[11:8]

ADC_SEL[3:2]

0

0x0D

Access

RW

Address

Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14

Bit 13

Bit 12

Name

Reset

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

TW_CODE[15:12]

0

0x0D

Access

RW

MAPENA – Register bank map enable request. When MAPENA request is written ‘1’ the internal mapena register bit is set.

It remains set until PWM counter overflows. The internal mapena is cleared upon the PWM counter overflows.

The <MAPENA> is always read as ‘0’.

CRC_CLR – <PXN_CRC_ERR_CNT[3:0]> clear request. When <CRC_CLR> bit is set to ‘1’ the

<PXN_CRC_ERR_CNT[3:0]> bits are cleared immediately. The <CRC_CLR> bit is always read as ‘0’.

ADC_SEL[1:0] – 2−bit ADC measurement channel selection for ADCx A/D conversion (see Table 11. ADC for measuring

VBB, VDD, VLED, TEMP, ADCx). The measurement channel is selected according to the following table:

Table 41. ADC MEASUREMENT CHANNEL SELECTION

ADC_SEL[1:0]

Measurement Channel

0x0

0x1

0x2

0x3

ADC0

ADC1

ADC2

Reserved

NOTE: The ADCx measurement result can be obtained by reading <ADCx_RES[7:0]> status bits.

In case the <ADC_SEL[1:0]> bits are set to “11”, the returned measured value is always “00000000”.

TW_CODE – 8−bit thermal warning threshold. The default value is calculated as follows:

TW_CODE[7:0] = TSD_CODE[7:0] − 9

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27

Table 42. REGISTER 0x0E

Register 0x0E

Address

0x0E

Bit 11

−

Bit 10

−

Bit 9

−

Bit 8

−

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

DIMFREQ[7:3]

0

CONF_SEL[2:0]

0 0

0

Access

RW

Bit 12

T1_CONF

0

Address

0x0E

Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13

Name

Reset

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

Access

RW

CONF_SEL[2:0] – Selects the switch configuration. NCV78343 supports the switch configurations listed in Table 16.

DIMFREQ[4:0] – Defines the DIMCLK frequency register, which shall be used to select dimming frequencies in range of

125 kHz to 1 MHz.

Table 43. PWM FREQUENCY SETTING

f

T

PWM

T

SW_SEQ

DIMCLK

[kHz]

[ms]

8.19

7.68

7.17

6.70

6.14

5.63

5.12

4.61

4.10

3.84

3.58

3.33

3.07

2.82

2.56

2.30

2.05

1.79

1.54

1.28

1.02

8.19

[ms]

DIMFREQ [4:0]

f

[Hz]

TR

24

48

96

192

24

SW SLOT

T

/T

PWM

SW_SEQ DIMCLK

0

1

125.00

133.33

142.86

152.85

166.67

181.82

200.00

222.22

250.00

266.67

285.71

307.69

333.33

363.64

400.00

444.44

500.00

571.43

666.67

800.00

1000.00

125.00

8.00

7.50

7.00

6.50

6.00

5.50

5.00

4.50

4.00

3.75

3.50

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

8.00

122.07

130.21

139.51

149.27

162.76

177.56

195.31

217.01

244.14

260.42

279.01

300.48

325.52

355.12

390.63

434.02

488.28

558.04

651.04

781.25

976.56

122.07

16

15

14

13

12

11

10

9

41

20

9

2

4

8

16

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

10

11

12

13

14

15

16

17

18

19

20

21 .. 31

16

14

12

10

16

9

4

41

T

– the duration of one dimming clock tick.

– the duration of 1024 dimming ticks.

DIMCLK

PWM

– the duration of one switch ON event.

SW_SEQ

/T

– the number of clocks required for one switch ON event.

SW_SEQ DIMCLK

TR – the number of ticks for all transient vectors. This space should be reserved for TR when this technique is used. Calculated as

(T /T )*12.

SW_SEQ DIMCLK

SW SLOT – recommended distance (in ticks of dimming clock) between two switch ON events.

T1_CONF − The bit defines the switch ON time (switching slope), where the “1” means steeper slope. For better EMC results

it is recommended to set this value to “0”.

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28

Table 44. REGISTER 0x0F

Register 0x0F

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SW6.STATUS

[11:10]

SW5.STATUS

[9:8]

SW4.STATUS

[7:6]

SW3.STATUS

[5:4]

SW2.STATUS

[3:2]

SW1.STATUS

[1:0]

Name

0x0F

Reset

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

Access

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

SW12.STATUS

[23:22]

SW11.STATUS

[21:20]

SW10.STATUS

[19:18]

SW9.STATUS

[17:16]

SW1.STATUS

[1:0]

SW7.STATUS

[13:12]

Name

0x0F

Reset

0

Access

R

SWx.STATUS[2] − Reflects status of internal SWx flags:

“00” – On/Off OK

“01” – On/Off Failed

“10” – Open

“11” – Short

The bit is cleared upon a successful readout over PXN (clear by read bit).

Table 45. REGISTER 0x10

Register 0x10

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

TSD

Bit 0

TW

PWM_

CNT_

OVF

OTP_

ZAP_

UV

GND_

LOSS

VBB_

LOW

DIMW

ARN

Name

CAP_UV

HWR

−

DIMERR

GSWERR

0x10

Reset

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

Access

R

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

OTP_CR

C_FAIL_

BANK_0

OTP_CR

C_FAIL_

BANK_2

PXN_F

RAME_

ERR

PXN_LOC

AL_COM

M_ERR

PXN_GLO

BAL_COM

M_ERR

MAPEN

A_STAT

US

TIME

OUT

PXN_SY

NC_ERR

Name

PXN_CRC_ERR_CNT[23:20]

0x10

Reset

0

Access

R

TW − Thermal warning flag. <TW> flag is set when Tj above Thermal Warning Threshold is detected. The bit is cleared upon

a successful readout over PXN.

TSD − Thermal shutdown flag. <TSD> flag is set when Tj above Thermal Shutdown Threshold is detected. When the flag is

set, the device enters FAIL status mode and the switches are switched OFF.

The bit is cleared upon a successful readout over PXN.

GSWERR − Global switch error indicator. The bit is set high under the following conditions:

• at least one switch is shorted or

• at least one switch is open or

• ext. capacitor charging has failed

The bit is cleared upon a successful readout over PXN.

DIMWARN − Dimming warning indicator. The bit is set high in case of an overlapping switch OFF sequences are detected.

The bit is cleared upon a successful readout over PXN (clear by read bit).

DIMERR - Dimming error indicator. The bit is set high in case an overlapping switch ON sequences are detected. When the

flag is set, the device enters the FAIL status mode. The bit is cleared upon a successful readout over PXN (clear

by read bit).

HWR − HWR flag is set after POR. The bit is cleared upon a successful readout over PXN (clear by read bit).

CAP_UV − Status bit indicating that charging process of external capacitor failed. When this bit is set, the <GSWERR> flag

is set to ‘1’ and the device enters the FAIL status mode and the switches are switched ON. The bit is cleared upon

a successful readout over PXN (clear by read bit).

OTP_ZAP_UV − The bit is set if the battery voltage during OTP zapping is lower than 15 V. The bit is cleared upon a successful

readout over PXN (clear by read bit).

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29

VBB_LOW − The bit is set if the battery voltage is lower than 4.5 V. The bit is cleared upon a successful readout over PXN

(clear by read bit).

GND_LOSS − The GND loss comparator detects Ground connection loss. The TST1 pin is used as reference ground. The TST1

pin is connected to ground on application PCB level (see Table 12. GND Loss Detection). The bit is

cleared upon a successful readout over PXN (clear by read bit).

PWM_CNT_OVF − When PWM counter overflows, flag is set to ‘1’. It should be used to detect that PWM control (PWM

counter) is running/functional. The bit is cleared upon a successful readout over PXN (clear by read bit).

MAPENA_STATUS - MAPENA request status. It corresponds to the state of internal MAPENA register bit.

PXN_GLOBAL_COMM_ERR − PXN global communication error. The flag is set in case of global communication error is

detected and not disabled by “Global bit error detection DIS” in OTP bank (see Table 24. OTP Bank). For

correct functionality it is mandatory to ensure an automatic echo from Tx to Rx. The PXN global

communication error is detected under the following circumstance: REPEATER−SLAVE node, where the

TX’’ differs from RX’’. The TX’’ is monitored by PXN node in REPEATER−SLAVE mode through

TX_ECHO_UART input.

The bit is cleared upon a successful readout over PXN (clear by read bit).

PXN_LOCAL_COMM_ERR − PXN local communication error. The flag is set in case of local communication error detected.

The PXN local communication error is detected under the following circumstance: SLAVE node, where the

TX’ differs from RX’. The bit is cleared upon a successful readout over PXN (clear by read bit).

PXN_FRAME_ ERR − PXN frame error. The flag is set whenever one of the following errors is detected:

•Parity error – the parity calculated over bits 0 .. 6 of either PID1 or PID2 is not matching the corresponding

parity bit P

• CRC error – the CRC calculated over PID1, PID2 and all data bytes do not match the received CRC

• STOP BIT error – ‘0’ received at the expected stop bit position

The bit is cleared upon a successful readout over PXN (clear by read bit).

PXN_SYNC_ERR − The PXN synchronization error is detected in case the duration of eight synchronization field Tbits, when

counted in 20 MHz domain is outside the following limits:

Table 46. PXN SYNCHRONIZATION ERROR LIMITS

PXN Communication Speed [kb/s]

Eight_Tbits_min

Eight_Tbits_max

125

250

1098

549

274

140

1484

742

371

181

500

1000

The bit is cleared upon a successful readout over PXN (clear by read bit).

TIMEOUT − The PXN timeout error is detected in case neither MAPENA nor MAPENA_DIR is activated within a TIMEOUT

period. The timeout error detection starts when the NORMAL mode is entered and either MAPENA or

MAPENA_DIR is activated for the first time. When the flag is set, the device enters the FAIL status mode and

LED’s are switched ON/OFF following the OTP memory bits 8−11 in Table 24. OTP Bank. The reported

OPMODE status is NORMAL_DIRECT mode. The bit is cleared upon a successful readout over PXN (clear by

read bit).

OTP_CRC_FAIL_BANK2 – CRC over mirrored OTP BANK2 bit failure. The bit is cleared upon a successful readout over

PXN (clear by read bit).

OTP_CRC_FAIL_BANK0 – CRC over mirrored OTP BANK0 bit failure. The device should not operate when this bit is set.

The bit is cleared upon a successful readout over PXN (clear by read bit).

PXN_CRC_ERR_CNT[3:0] – 4−bit PXN frame CRC error counter. The counter is incremented each time a CRC error is

detected on incoming PXN frame. Once a maximum number of errors is reached, the counter remains

clamped at value of 15. The bit is cleared upon a successful write ‘1’ to register < CRC_CLR>.

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30

Table 47. REGISTER 0x11

Register 0x11

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

VDD_RES[11:8]

TEMP_RES[7:0]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0x11

Access

R

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

ADCX_RES[23:16]

VDD_RES[15:12]

0

0x11

Access

R

TEMP_RES[7:0] – the TEMP measured value (read only bits).

VDD_RES[7:0] – the last VDD measured value (read only bits).

ADCX_RES[7:0] – the last value measured at selected ADC measurement channel (read only bits). In case the

<ADC_SEL[1:0]> bits are set to “11” the returned measured value is always “00000000”.

Table 48. REGISTER 0x12

Register 0x12

Address

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

VLED_RES[11:8]

VBB_RES[7:0]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0x12

Access

R

Address

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18 Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Name

Reset

TSD_CODE[23:16]

VLED_RES[15:12]

0

0x12

Access

R

VBB_RES[7:0] – the last VBB measured value (read only bits).

VLED_RES[7:0] – the last VLED measured value (read only bits). Because of the internal ESD structure, the minimum

measured VLED voltage is VDD minus forward diode voltage Vf.

TSD_CODE[7:0] – thermal shutdown threshold (read only bits).

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31

CONFIGURATION FRAMES

Table 49. CF0 − SLAVE IDENTIFICATION

Contents

Bit 7

P

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

4

5

6

7

8

1

0

1

0

PID2

P

CSID[4:0] = 0x00

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

CRC

DEV_ID[7:0]

ANA_ID[7:0]

DIG_ID[7:0]

0

DLT_W[4:0]

DLT_X_AXS[7:0]

DLT_Y_AXS[7:0]

CRC[7:0]

DATA1

DEV_ID[7:0]

device ID, L343 = 1

analog version ID, 35

digital version ID, 1

DATA2

ANA_ID[7:0]

DATA3

DIG_ID[7:0]

DATA4

DLT_W[4:0]

DATA5

DLT_X_AXS[7:0]

DATA6

DLT_Y_AXS[7:0]

The DLT_W, DLT_X_AXS and DLT_Y_AXS parameters describe the wafer specifications.

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32

Table 50. CF1 − EEPROM WRITE DATA

Contents

Bit 7

P

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

0

Name

PID1

1

0

1

0

1

PID2

P

CSID[4:0] = 0x01

2

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

CRC

B

0

EESA[2:0]

3

EEBA[7:0]

4

BYTE0 @(EEBA+0)[7:0]

BYTE1 @(EEBA+1)[7:0]

BYTE2 @(EEBA+2)[7:0]

BYTE3 @(EEBA+3)[7:0]

BYTE4 @(EEBA+4)[7:0]

BYTE5 @(EEBA+5)[7:0]

BYTE6 @(EEBA+6)[7:0]

BYTE7 @(EEBA+7)[7:0]

CRC[7:0]

5

6

7

8

9

10

11

12

DATA1

B

broadcast bit:

1 − broadcast frame

0 – addressed frame

EESA[2:0]

EEPROM slave address

EEPROM byte address

bytes to be written

DATA2

EEBA[7:0]

DATA3 – DATA10

BYTEx[7:0]

Table 51. CF2 − EEPROM REQUEST DATA

Contents

Bit 7

P

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

4

1

0

1

0

PID2

P

CSID[4:0] = 0x02

DATA1

DATA2

CRC

B

0

EESA[2:0]

EEBA[7:0]

CRC[7:0]

DATA1

B

broadcast bit:

1 − broadcast frame

0 – addressed frame

EESA[2:0]

EEPROM slave address

EEPROM byte address

DATA2

EEBA[7:0]

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Table 52. CF3 − EEPROM READ DATA

Contents

Bit 7

P

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

0

Name

PID1

1

0

1

0

1

PID2

P

CSID[4:0] = 0x03

2

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

CRC

WP

EES[1:0]

0

EESA[2:0]

3

EEBA[7:0]

4

BYTE0 @(EEBA+0)[7:0]

BYTE1 @(EEBA+1)[7:0]

BYTE2 @(EEBA+2)[7:0]

BYTE3 @(EEBA+3)[7:0]

BYTE4 @(EEBA+4)[7:0]

BYTE5 @(EEBA+5)[7:0]

BYTE6 @(EEBA+6)[7:0]

BYTE7 @(EEBA+7)[7:0]

CRC[7:0]

5

6

7

8

9

10

11

12

DATA1

EESA[2:0]

EEPROM slave address

EEPROM status:

EES[1:0]

0x0 – EEPROM busy, access denied

0x1 – EEPROM busy, data transfer ongoing

0x2 – EEPROM ready, data transfer completed

0x3 – EEPROM ready, data transfer failed

WP

EEPROM write protect status

DATA2

EEBA[7:0]

EEPROM byte address

read bytes

DATA3 – DATA10

BYTEx[7:0]

Table 53. CF4 – ENABLE/DISABLE AUTO−ADDRESSING MODE

Contents

Bit 7

P

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

1

0

1

0

PID2

P

CSID[4:0] = 0x04

0

DATA1

CRC

B

0

AAC

CRC[7:0]

DATA1

B

broadcast bit:

1 − broadcast frame

0 – addressed frame

AAC

auto−addressing control bit: 1 − enable

0 − disable

The CF4 frame is accepted in the OTP_CONFIG mode only.

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Table 54. CF5 − ASSIGN ADDRESS

Contents

Bit 4 Bit 3

Bit 7

P

Bit 6

Bit 5

Bit 2

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

4

1

0

1

0

SA[4:0]

PID2

P

CSID[4:0] = 0x05

AA_ADR[4:0]

DATA1

DATA2

CRC

B

AA_THR[7:0]

CRC[7:0]

DATA1

B

broadcast bit:

1 – broadcast frame

0 – addressed frame

AA_ADR[4:0]

5−bit address to assign

DATA2

AA_THR[7:0]

8−bit auto−address threshold value

The CF5 frame is accepted in AUTO_ADDR mode only.

Table 55. CF6 − OP MODE STATUS

Contents

Bit 7

P

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

1

0

1

0

PID2

P

CSID[4:0] = 0x06

DATA1

CRC

PXN_FRAME_CNT[3:0]

OPMODE[3:0]

CRC[7:0]

DATA1

PXN_FRAME_CNT[4:0]

OPMODE[3:0]

PXN frame counter – 4−bit counter which is incremented each time any valid PXN frame

is processed. The counter overflows to 0 upon the increment.

OP mode status:

0x0 − not valid

0x7 − normal fail−safe open mode

0xC − NO_CRC direct mode

0xD − NO_CRC pwm mode

0xE − fail safe OTP mode

0x1 − OTP config mode

0x2 − auto−addressing mode

0x4 − normal direct mode

0x5 − normal pwm mode

0x6 − normal fail−safe otp mode

0xF − fail safe OPEN mode

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Table 56. CF7 − SLAVE/REPEATER−SLAVE PXN MODE SELECTION

Contents

Bit 7

P

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

1

0

1

0

PID2

P

CSID[4:0] = 0x07

0

DATA1

CRC

B

0

PMC

CRC[7:0]

DATA1

B

broadcast bit:

1 – broadcast frame

0 – addressed frame

PMC

PXN mode control bit:

1 − repeater−slave mode

0 − slave mode

Overwrites device mode loaded from the OTP memory.

Table 57. CF8 − READ PXN MODE STATUS

Contents

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

P

0

1

0

1

0

PID2

CSID[4:0] = 0x08

0

DATA1

CRC

0

PMS

CRC[7:0]

DATA1

PMS

PXN mode status bit:

1 − repeater−slave mode

0 − slave mode

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Table 58. CF9 − WRITE DATA TO OTP

Contents

Bit 4

Bit 7

P

Bit 6

Bit 5

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

4

5

6

7

8

1

0

1

0

PID2

P

CSID[4:0] = 0x09

0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

B

0

OTPBS[1:0]

BYTE0 @(OTPBA+0)

BYTE1 @(OTPBA+1)

BYTE2 @(OTPBA+2)

BYTE3 @(OTPBA+3)

0x00

CRC[7:0]

DATA1

B

broadcast bit:

1 – broadcast frame

0 – addressed frame

OTPBS[1:0]

2−bit OTP bank selection

0x2 – custom OTP bank

0x0, 0x1, 0x3 – no bank selected

DATA2 – DATA6

BYTEx[7:0]

bytes to be written

The CF9 frame is accepted in OTP_CONFIG mode only.

Table 59. CF10 − REQUEST DATA FROM OTP

Contents

Bit 7

P

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

1

0

1

0

PID2

P

CSID[4:0] = 0x0A

0

DATA1

CRC

B

0

OTPBS[1:0]

CRC[7:0]

DATA1

B

broadcast bit:

1 – broadcast frame

0 – addressed frame

OTPBS[1:0]

2−bit OTP bank selection:

0x2 − custom OTP bank

0x0, 0x1, 0x3 − no bank selected

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Table 60. CF11 − READ DATA FROM OTP

Contents

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

4

5

6

7

8

P

1

0

1

0

PID2

CSID[4:0] = 0x0B

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

CRC

LOCKB

OTPS[1:0]

0

OTPBS[2:0]

BYTE0 @(OTPBA+0)

BYTE1 @(OTPBA+1)

BYTE2 @(OTPBA+2)

BYTE3 @(OTPBA+3)

BYTE4 @(OTPBA+4)

CRC

DATA1

LOCKB

custom OTP bank general lock status bit:

1 – locked

0 – unlocked, further OTP programming possible

OTPS[1:0]

2−bit OTP status:

0x0 − idle, no data transfer ongoing

0x1 − busy, data transfer ongoing

0x2 − ready, data transfer OK

0x3 − ready, data transfer failed

OTPBS[1:0]

2−bit OTP bank selection:

0x2 − custom OTP bank

0x0 or

0x1 or

0x3 − no bank selected

DATA2 – DATA6

BYTEx[7:0]

read bytes

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Table 61. CF12 − COMMUNICATION SPEED

Contents

Bit 4

Bit 7

P

Bit 6

Bit 5

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

1

0

1

0

PID2

P

CSID[4:0] = 0x0C

0

DATA1

CRC

B

0

CSPEED[1:0]

CRC[7:0]

DATA1

B

broadcast bit:

1 − broadcast frame

0 − addressed frame

CSPEED[1:0]

communication speed:

0x0 – 125 kbps

0x1 – 250 kbps (default)

0x2 – 500 kbps

0x3 – 1000 kbps

Overwrites device communication speed loaded from the OTP memory.

Table 62. CF13 − SWITCH TO NORMAL MODE

Contents

Bit 7

P

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

1

0

1

0

PID2

P

CSID[4:0] = 0x0D

0

DATA1

CRC

B

0

NMD

CRC[7:0]

DATA1

B

broadcast bit:

1 − broadcast frame

0 – addressed frame

NMD

request to enter NORMAL mode from OTP_CONFIG mode:

1 – go to NO_CRC or normal mode; according to the OTP bank 2 lock bit

0 – no effect

The CF13 frame is accepted in OTP_CONFIG mode only.

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Table 63. CF14 − RESET SYSTEM

Contents

Bit 4

Bit 7

P

Bit 6

Bit 5

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

1

0

1

0

PID2

P

CSID[4:0] = 0x0E

0

DATA1

CRC

B

0

SWRST

CRC

DATA1

B

broadcast bit:

1 − broadcast frame

0 – addressed frame

SWRST

software reset bit:

1 − perform software reset

0 – no effect

The CF14 frame is accepted in NORMAL mode only.

Table 64. CF15 − TRIGGER MAPENA

Contents

Bit 7

P

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SA[4:0]

Bit 1

Bit 0

Byte

Name

PID1

0

1

2

3

1

0

1

0

PID2

P

CSID[4:0] = 0x0F

DATA1

CRC

B

0

WDT_SEL[1:0]

0

MAPENA

CRC[7:0]

DATA1

B

broadcast bit:

1 − broadcast frame

0 – addressed frame

MAPENA

trigger MAPENA

1 – perform MAPENA

0 – no effect

WDT_SEL[1:0]

watchdog timeout selector; valid only with <MAPENA> = ‘1’

0x0 – 250 ms

0x1 – 150 ms

0x2 – 100 ms

0x3 – 60 ms

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40

THERMAL WARNING, ERROR DETECTION AND DIAGNOSTICS FEEDBACK

The NCV78343 offers a wide range of device−integrated

diagnostic features. Their description follows.

Overall status of switches errors are indicated by the

Global Switch Error <GSWERR> status flag. Status of

individual switches (whether a switch is ON or OFF) can be

read in the Switch Status <SWx.STATUS> flag. The failure

state of the individual switches (Short, Open) is indicated by

corresponding status in <SW.STATUS[2:0]> register.

When the device operates in the PWM mode and a short

is present, the device reports alternating On/Off Failed and

SHORT status according to set ON/OFF dimming duration

(see details in Figure 13).

Thermal Warning and Shutdown

The junction temperature can be calculated from ADC

code as follows:

ADC

TSD

) 184

CODE

_@ǒ_TSD

_) 273Ǔ _* 273

TEMPERATURE

T +

j

(eq. 2)

The <TSD_CODE> is trimmed in production to 170°C

(TSD ). Typical value of <TSD_CODE> is

TEMPERATURE

186 and exact trimmed value can be read from Register

0x12. The <TW> status bit is set high in case the

measurement result is greater than or equal to

TW_CODE[7:0] value. The <TSD> status bit is set high in

case the measurement result is greater than or equal to

TSD_CODE[7:0].

The TW and TSD status bits are cleared in case the

<TEMP_RES> register value is smaller than both

TSD_CODE and TW_CODE values and TW and TSD

status bits are successfully read out over PXN.

Dedicated OPEN clear request

When the OPEN state or overvoltage is detected, the

switch is automatically closed and the status is shown in the

SWx.STATUS register 0x0F. Further attempts to control this

switch using PWM or DIRECT mode don’t have any effect.

The switch is released upon a successful OPEN clear request

frame.

In direct mode, the released switch is updated upon a

successful write to register 0x00 with service “00”. In PWM

mode, the released switch is updated according to the

ON/OFF values.

Overlapping switch ON/OFF events

Overlapping switch ON events is forbidden, the

NCV78343 needs time slot between two switch ON events

(see Table 43). Superior system has to ensure that

overlapping switch ON events do not appear in patterns.

When overlapping switch ON events are despite this

invoked, the NCV78343 incorporates protective feature, in

which the <DIMERR> error is raised.

PWM_CNT_OVF

When PWM Counter overflows, <PWM_CNT_OVF>

flag is set to ‘1’. It is clear by read flag. It should be used to

detect that PWM control (PWM counter) is

running/functional.

CAP_UV

When overlapping switch OFF events occur, the

<DIMWARN> status bit is set and processing of this pattern

continues. However, it has to be taken into account, that

overlapping switch OFF events can lead to large fluctuations

of LED string voltage.

The <CAP_UV> status bit indicates that charging process

of external capacitor failed. When this bit is set, the

<GSWERR> flag is set to ‘1’ and all switches are switched

OFF. It is clear by read flag and the switches are set

according to last successful write to the register 0x00.

Pixel Switches diagnostic

VBB_LOW

Embedded diagnostic covers a wide range of possible

failure situations on switches. Each switch contains two

comparators – short comparator and over voltage

comparator. With the help of these two comparators a

several fail situations can be detected and distinguished on

each switch individually.

The <VBB_LOW> status bit indicates low battery

voltage < 4.5 V (see Table 4). The bit is not detected when

the battery voltage level is lower than 4.5 V during the

start−up sequence.

Power−on Reset

After a power−on a flag <HWR> in the register is set.

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41

APPLICATION RELATED INFORMATION

PXN CRC Code Example

// Byte reverse

uint8_t l343_byte_reverse(uint8_t b)

{

b = (b & 0xF0) >> 4 | (b & 0x0F) << 4;

b = (b & 0xCC) >> 2 | (b & 0x33) << 2;

b = (b & 0xAA) >> 1 | (b & 0x55) << 1;

return b;

}

// Calculate the PXN CRC

uint8_t l343_pxn_crc(uint8_t *data_bits, uint8_t length)

{

uint8_t CRC8 = 0;

for (uint8_t a=0; a<length; ++a)

{

CRC8 = CRC8 ^ data_bits[a];

for (uint8_t i=0; i<8; ++i)

{

if (CRC8 & 0x80)

{

CRC8 = ((0x7F & CRC8) * 2) ^ 0x07;

}

else

{

CRC8 = CRC8 * 2;

}

return CRC8;

}

Function call example:

int main(void)

{

// MAPENA as broadcast; SEED, PID1, PID2, DATA0; CRC = 0x28

uint8_t data_bits[] = {0xFF, 0x61, 0x8F, 0x81};

// Write to REG00; SEED, PID1, PID2, DATA0, DATA1, DATA2; CRC = 0x14

// uint8_t data_bits[] = {0xFF, 0xA1, 0x80, 0x55, 0x05, 0x00};

// Get the number of bytes

int length = sizeof(data_bits)/sizeof(data_bits[0]);

// Invert the input

for (uint8_t a = 0; a<length; ++a) data_bits[a] = l343_byte_reverse(data_bits[a]);

// Get the result

uint8_t result = l343_pxn_crc(data_bits, length);

}

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42

Parity Bit Calculation

uint8_t l343_parity(uint8_t val)

{

bool Par;

Par = ((val>>0)&1) ^ ((val>>1)&1) ^ ((val>>2)&1) ^ ((val>>3)&1) ^ ((val>>4)&1) ^

((val>>5)&1) ^ ((val>>6)&1);

Par = (Par ^ 1) & 1;

return (uint8_t)Par;

}

Go to NMD Frame (CF13)

int32_t l343_normal_mode(uint8_t addr)

{

uint8_t p;

uint8_t pdata[5];

// SYNC

pdata[0] = 0x55;

// PID1

uint8_t PID1 = 0;

PID1 = 3<<5 | addr;

p = l343_parity(PID1);

pdata[1] = (p << 7) | PID1;

// PID2

uint8_t PID2 = 0;

PID2 = 0x0D;

p = l343_parity(PID2);

pdata[2] = (p << 7) | PID2;

// DATA bytes

pdata[3] = 1;

// NMD

uint8_t pdata_crc[4];

// Invert the input

for (uint8_t a = 0; a<4; ++a) pdata_crc[a] = l343_byte_reverse(pdata[a]);

// Calculate the CRC

pdata_crc[0] = 0xFF;

uint8_t crc = l343_pxn_crc(pdata_crc, 4);

pdata[4] = crc;

// Send data

return serial_pxn_set_data(pdata, 5);

}

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43

OTP Write Code Example

typedef struct OTP_t

{

unsigned lb: 1;

// Lock bit

unsigned na_lb: 1;

unsigned na: 5;

// Node Address Lock bit

// Note Address

unsigned fss_lb: 1;

unsigned fss: 4;

// Fail Safe State Lock bit

// Fail Safe State of LEDs

// PXN Lock bit

unsigned pxn_lb: 1;

unsigned mode: 1;

unsigned cs: 2;

// Mode

// Communication speed

// Global bit error detection

// M−LVDS off

unsigned gbed: 1;

unsigned m_lvds_off: 1;

unsigned uart_off: 1;

unsigned ee_lb: 1;

unsigned crc: 7;

// UART off

// EEPROM lock bit

// CRC

} OTP_t;

// Calculate the OTP CRC

uint8_t l343_otp_crc(uint8_t *data_bits, char length)

{

uint8_t CRC7 = 0;

for (uint8_t a = 0; a<length; ++a)

{

CRC7 = CRC7 ^ data_bits[a];

for (uint8_t i = 0; i < 8; ++i)

{

if (CRC7 & 0x80)

{

CRC7 = ((0x7F & CRC7) * 2) ^ (0x37 * 2);

}

else

{

CRC7 = (CRC7 * 2);

}

return (CRC7 / 2);

}

int32_t l343_otp_zapping(OTP_t otp)

{

uint8_t data_bits[4];

data_bits[0] = 0x07;

data_bits[1] = 0x0F<<4 | otp.ee_lb<<3 | otp.uart_off<<2 | otp.m_lvds_off<<1 | otp.gbed<<0;

data_bits[2] = otp.cs<<6 | otp.mode<<5 | otp.pxn_lb<<4 | otp.fss<<0;

data_bits[3] = otp.fss_lb<<7 | otp.na<<2 | otp.na_lb<<1 | otp.lb<<0;

// Get the number of bytes

int length = sizeof(data_bits)/sizeof(data_bits[0]);

// Get the result

otp.crc = l343_otp_crc(data_bits, length);

// PXN OTP write frame

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44

uint8_t p;

uint8_t pdata[10];

// SYNC

pdata[0] = 0x55;

// PID1

uint8_t PID1 = 0;

PID1 = 3<<5 | otp.na;

p = l343_parity(PID1);

pdata[1] = (p << 7) | PID1;

// PID2

uint8_t PID2 = 0;

PID2 = 0x09;

p = l343_parity(PID2);

pdata[2] = (p << 7) | PID2;

// DATA bytes

const uint32_t data = otp.lb |

otp.na_lb << 1 |

otp.na << 2 |

otp.fss_lb << 7 |

otp.fss << 8 |

otp.pxn_lb << 12 |

otp.mode << 13 |

otp.cs << 14 |

otp.gbed << 16 |

otp.m_lvds_off << 17 |

otp.uart_off << 18 |

otp.ee_lb << 19 |

otp.crc << 20;

pdata[3] = 0x02;

pdata[4] = ((data >> 0 ) & 0xFF);

pdata[5] = ((data >> 8 ) & 0xFF);

pdata[6] = ((data >> 16) & 0xFF);

pdata[7] = ((data >> 24) & 0xFF);

pdata[8] = 0x00;

uint8_t pdata_crc[9];

// Invert the input

for (uint8_t a = 0; a<9; ++a) pdata_crc[a] = l343_byte_reverse(pdata[a]);

// Calculate the CRC

pdata_crc[0] = 0xFF;

uint8_t crc = l343_pxn_crc(pdata_crc, 9);

pdata[9] = crc;

// Send data

return serial_pxn_set_data(pdata, 10);

}

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45

Function call example:

int main(void)

{

// Zap the OTP

//

lb

nalb

na

fss_lb fss pxn_lb mode CS

GBED lOff uOff eeLb crc

OTP_t otp = {0x01, 0x01, 0x01, 0x01, 0x0F, 0x01, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00};

l343_otp_zapping(otp);

}

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46

Auto−addressing (AA) Process

This example is valid for two devices, where the first one

is in repeater−slave mode and the second one is in slave

mode. The first device is connected to the MCU via UART

and the second device is connected to the first device via

M−LVDS.

4. Assign the address for the device 1 by sending

CF5 as broadcast (B=1; ADR=1; THR=80); see

Table 54.

5. Disable buck output 1, so the LED string for the

device 1 is not shining.

The slave address (SA) for the first device will be set to ‘1’

and the SA for the second device will be set to ‘7’.

The AA process combines benefits of current source and

connected LED string. The application does not need any

additional wires. When the device is connected to the LED

string and the current source for this LED string is enabled,

the voltage drop across the LED string will occur. The LED

string voltage VLED is measured by the device. Thus the

address may be assigned to specific device.

In general, the MCU sends a broadcast frame CF4 (see

Table 53) to all node devices and the second broadcast frame

CF5 (see Table 54) with the VLED threshold and new device

address as parameters. Doing this, all devices on the node

will be in AA mode and only the device with VLED higher

than set threshold will assign new address.

6. Disable the AA mode for the first device SA=1 by

sending CF4 (B=0; AAC=0); see Table 53.

7. Force the normal mode for the first device SA=1

by sending CF13 (NMD=1); see Table 62.

8. Set the first device as repeater−slave SA=1 by

sending CF7 (PMC=1); see Table 56.

9. Enable buck output 2, so the LED string for the

device 2 is shining.

10. Enable AA mode by sending CF4 as broadcast

(B=1; AAC=1); see Table 53.

11. Assign the address for the device 2 by sending

CF5 as broadcast (B=1; ADR=7; THR=80); see

Table 54.

12. Disable buck output 2, so the LED string for the

device 2 is not shining.

For this example, the LED string voltage is 33 V (127

ADC code). The auto−addressing threshold will be set to 80.

1. Disable all buck outputs, thus the LEDs are not

shining.

13. Disable the AA mode for the second device SA=7

by sending CF4 (B=0; AAC=0); see Table 53.

14. Force the normal mode for the second device

SA=7 by sending CF13 (NMD=1); see Table 62.

2. Enable buck output 1, so the LED string for the

device 1 is shining.

3. Enable AA mode by sending CF4 as broadcast

(B=1; AAC=1); see Table 53.

For multiple devices connected to the first one via

M−LVDS, please repeat steps 9−14 with different ADR,

THR, SA values.

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47

1024*TR_SLOT

T_SW_ON_SEQ

12

Dimming Control Patterns

The simplest way to set ON, OFF and TR values is to keep

the ON time at fixed value and calculate the OFF value

according to the required duty. The following table (see

Table 65) shows an example of fixed ON values. It is

calculated for each switch 0−11 and for each DIMFREQ

value 0−20.

SW_SLOT +

(eq. 4)

(eq. 5)

ON_VALUE + TR_SLOT ) SWITCH SW_SLOT

T_SW_ON_SEQ

where

SWITCH goes from 0 to 11

T_SW_ON_SEQ is number of ticks required for one

switch ON sequence

The values are calculated as follows:

TR_SLOT + 12 T_SW_ON_SEQ

(eq. 3)

Table 65. DIMMING CONTROL PATTERN ON VALUES

0

1

2

3

4

5

6

7

8

9

4

10

4

11

4

12

4

13

4

14

4

15

4

16

8

17

8

18

8

19

8

20

16

DIMFREQ

T_SW_ON

_SEQ

2

4

24

41

24

41

24

41

24

41

24

41

24

41

24

41

24

41

48

20

48

20

48

20

48

20

48

20

48

20

48

20

48

20

96

9

96

9

96

9

96

9

192

4

TR_SLOT

SW_SLOT

SWITCH

ON values

48

24

48

96

192

256

320

384

448

512

576

640

704

768

832

896

0

1

106

188

270

352

434

516

598

680

762

844

926

106

188

270

352

434

516

598

680

762

844

926

106

188

270

352

434

516

598

680

762

844

926

106

188

270

352

434

516

598

680

762

844

926

106

188

270

352

434

516

598

680

762

844

926

106

188

270

352

434

516

598

680

762

844

926

106

188

270

352

434

516

598

680

762

844

926

106

188

270

352

434

516

598

680

762

844

926

128

208

288

368

448

528

608

688

768

848

928

128

208

288

368

448

528

608

688

768

848

928

128

208

288

368

448

528

608

688

768

848

928

128

208

288

368

448

528

608

688

768

848

928

128

208

288

368

448

528

608

688

768

848

928

128

208

288

368

448

528

608

688

768

848

928

128

208

288

368

448

528

608

688

768

848

928

168

240

312

384

456

528

600

672

744

816

888

168

240

312

384

456

528

600

672

744

816

888

168

240

312

384

456

528

600

672

744

816

888

168

240

312

384

456

528

600

672

744

816

888

208

2

288

3

368

4

448

5

528

6

608

7

688

8

768

9

848

10

11

928

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48

Dimming Algorithm Code

// Variables for dimming algorithm

static const uint8_t TR_SLOT[]

static const uint8_t SW_SLOT[]

=

{24, 24, 24, 24, 24, 24, 24, 24, 48, 48, 48, 48, 48, 48, 48, 48, 96, 96, 96, 96, 192};

{41, 41, 41, 41, 41, 41, 41, 41, 20, 20, 20, 20, 20, 20, 20, 20, 9, 9, 9, 9, 4};

static const uint8_t T_SW_SEQ_RATIO[]

= {2, 2, 2, 2, 2, 2, 2, 2, 4, 4, 4, 4, 4, 4, 4, 4, 8, 8, 8, 8, 16};

bool l343_dimming(uint8_t dimfreq, uint16_t *DCs, uint16_t *onRet, uint16_t *offRet, uint16_t *trRet)

{

const uint8_t LEDcount

= 12;

for (uint8_t

{

i

=

>

0; i<LEDcount; ++i)

if (DCs[i]

1023) DCs[i] = 1023;

// Input is brightness of LEDs, but the ON/OFF values are for switches, thus inverted

DCs[i] 1023 DCs[i];

trRet[i] i;

=

−

=

// set TR 0..11

if (DCs[i] == 1023)

{

// Fully ON 100% DUTY cycle, thus set dedicated values 0 and 1023

onRet[i]

=

0;

= 1023;

offRet[i]

}

else

{

onRet[i]

= TR_SLOT[dimfreq] + i*SW_SLOT[dimfreq]*T_SW_SEQ_RATIO[dimfreq];

if (DCs[i] == 0)

{

// Fully OFF 0% DUTY cycle, where OFF is equal to ON value

offRet[i]

=

onRet[i];

(onRet[i]

}

else

{

+

DCs[i]) % 1024;

}

DCs[i]

=

1023

−

DCs[i];

// Invert back to keep the values as they were

}

return true;

}

// Number of devices in

#define DEVICES

a cluster

X

// [1; 31]

#define REGISTERS 12

// number of registers to be written

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49

// LED brightness; the length should be DEVICES*REGISTERS; or two−dimensional array might be used

uint16_t DC[DEVICES*REGISTERS];

// values are in a range of [0; 1023]

// uint16_t DC[DEVICES][REGISTERS];

// Drimfreq for each device

uint8_t dimfreq[DEVICES]

// Function call example:

// Send ON, OFF, TR values to all devices

void l343_send(uint16_t *DC)

{

for (uint8_t dev

{

= 0; dev<DEVICES; ++dev)

uint16_t ON[REGISTERS];

uint16_t OFF[REGISTERS];

uint16_t TR[REGISTERS];

// Calculate the dimming values

l343_dimming(dimfreq[dev], DC+REGISTERS*dev, ON, OFF, TR);

l343_dimming(dimfreq[dev], DC[dev], ON, OFF, TR);

//

// when two−dimensional array is used

// Fill the registers values

uint32_t reg[REGISTERS];

for (uint8_t

{

r = 0; r<REGISTERS; ++r)

reg[r]

= (ON[r]<<14) | (OFF[r]<<4) | (TR[r]&0xF);

}

// 36 bytes need to be sent in

3 frames

uint8_t RBA[3]

=

{1, 5, 9};

for (uint8_t

{

r

=

0; r<3; ++r)

uint8_t p;

uint8_t pdata[16];

// SYNC

pdata[0]

// PID1

= 0x55;

uint8_t PID1

PID1 1<<5

=

0;

=

|

SA[dev];

p

= l343_parity(PID1);

pdata[1]

=

p<<7

|

1<<5 | PID1;

// PID2

uint8_t PID2

PID2 3<<5

l343_parity(PID2);

=

0;

=

| (RBA[r]);

p

=

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50

pdata[2]

= p<<7 | PID2;

// DATA bytes

pdata[3]

pdata[4]

pdata[5]

=

reg[r*4+0]&0xFF;

(reg[r*4+0]>>8)&0xFF;

(reg[r*4+0]>>16)&0xFF;

pdata[6]

pdata[7]

pdata[8]

=

reg[r*4+1]&0xFF;

(reg[r*4+1]>>8)&0xFF;

(reg[r*4+1]>>16)&0xFF;

pdata[9]

pdata[10]

pdata[11]

=

reg[r*4+2]&0xFF;

=

(reg[r*4+2]>>8)&0xFF;

(reg[r*4+2]>>16)&0xFF;

pdata[12]

pdata[13]

pdata[14]

=

reg[r*4+3]&0xFF;

(reg[r*4+3]>>8)&0xFF;

(reg[r*4+3]>>16)&0xFF;

uint8_t pdata_crc[16];

// Invert the input

for (unsigned char

a = 0; a<15; ++a) pdata_crc[a] = l343_byte_reverse(pdata[a]);

// Calculate the CRC

pdata_crc[0] 0xFF;

char crc l343_pxn_crc(pdata_crc, 15);

=

pdata[15] = crc;

// Send data

serial_pxn_set_data(2, pdata, 16, 11);

}

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51

OTP Read Data Interpretation

The table below shows an example of OTP read data and its interpretation in the OTP table (see Table 24).

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

xC2

x87

x70

x30

x3D

x00

11000010

10000111

01110000

00110000

00111101

00000000

OTPBS[2:0]=x02

OTPS[1:0]=x02

LOCKB=x01

0

lb

1

6

1

5

0

4

NA [4:0]

0

3

0

2

7

11

0

10

FSS [3:0]

9

0

8

0

12

PXN lb

1

13

Mode

1

15

1

14

0

16

17

18

19

26

1

25

1

24

0

23

CRC[6:0]

0

22

1

21

20

1

CS [1:0]

Addr lb

1

FSS lb

1

GBED DIS LVDS OFF UART OFF EEPR lb

0

DATA2

DATA3

DATA4

DATA5

Figure 18. Read OTP Data Interpretation

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52

Return to Normal Operation after Fail−Safe Mode

Once a device detects one of the following status bits:

TSD or CAP_UV or VBB_LOW or DIMERR or

TIMEOUT, the device enters the fail−safe mode (see

Operating Modes section). To leave this mode, the superior

system shall read out the REG 0x10 (see Table 45) and/or

handle the error if required.

The device enters FAIL−SAFE OTP mode when

DIMERR or TIMEOUT appears. When TIMEOUT is set

and this mode is entered, switches are set according to the

OTP memory values. If the OTP memory is not zapped, the

switches are switched OFF. Once the error status bit is

cleared, the switches remain unchanged. When DIMERR is

set and this mode is entered, switches operation is

unaffected.

The device enters FAIL−SAFE OPEN mode when TSD or

CAP_UV or VBB_LOW appears. In this mode, the switches

are automatically switched OFF. Once the error status bit is

cleared, the switches are set according to the values in REG

0x00 (see Table 27).

The TSD/CAP_UV/VBB_LOW group of bits (hardware

fail) have higher priority to the DIMERR/TIMEOUT group

of bits (application fail). When these two groups appear at

the same time, the device enters the FAIL−SAFE OPEN

mode.

NORMAL DIR/PWM

Read out CF6

NO_CRC or NORMAL

TSD or CAP_UV or

VBB_LOW

FAIL-SAFE OTP

FAIL-SAFE OPEN

DIMERR

TIMEOUT

switches

based on PWM values

switched OFF

Are OTPs

zapped?

No

Yes

NORMAL

NO_CRC

Read out REG 0x10

FAIL-SAFE OTP

switches

based on OTP values

switched OFF

Read out REG 0x10

NO_CRC or NORMAL

PWM

NO_CRC DIRECT

NORMAL DIRECT

DIRECT

switches

based on PWM values

switched OFF

based on OTP values

based on REG 0x00

Figure 19. FAIL−SAFE Modes

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53

Power Up and Down Sequences

Figure 20. Power−up Sequence with 10 nF at ADC2/ADR Pin

Figure 21. Power−down Sequence with 10 nF at ADC2/ADR Pin

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54

Example Flow Chart Diagram for the Normal Operational Mode

Normal Mode

Coming from a POR

(Optional)

Change CONF_SEL and

DIMFREQ if required

Write Register 14

Read all status

registers

(REG15−REG18)

No

Check the status bits

All correct ?

Handle errors

Yes

Calculate the

Write all devices 1.. n

dimming pattern and

write REG01−REG12

Written all devices 1.. n

Send CF 15 within

WDT timeout

MAPENA broadcast

command

Figure 22. Normal Operation Mode Flow Chart Diagram

The main loop should consist of checking all status bits

all ON/OFF/TR values within this time and send broadcast

MAPENA (see Table 64) frame once the values are sent into

devices.

and handling them if necessary. Set a refresh rate for

common headlamp lighting functions (e.g. High beam) as

well as fulfill watchdog timeout. The MCU should calculate

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55

Flow Chart after POR

Init

Check OTP global

lock bit

No

Yes

Is zapped

Check OTP node

address lock bit

Check OTP node

address lock bit

No

Yes

Is zapped

Yes

Is zapped

Check ADR pin for a

valid range

No

Is valid

Yes

Check OTP BANK2 CRC

Send CF13

with NMD=1

CONFIG

mode

Is correct

Yes

NORMAL

mode

NO_CRC

mode

Figure 23. Flow Chart Diagram after POR

The diagram above is an automatic flow after each POR.

A device might end up in either CONFIG or NORMAL or

NO_CRC mode according to zapped OTP bits.

Auto−addressing process or by Multi−level addressing

using a voltage divider or zapped in the OTP memory.

A new device will end up in CONFIG mode, because OTP

bits are not zapped. An address is set by either

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56

Multi−level Addressing Procedure with Long Time Delay at ADC2/ADR Pin

The following flow chart is valid for the repeater−slave

and slaves cluster, where the repeater−slave communicates

through CAN−PHY layer and slaves are connected via local

M−LVDS bus.

Init

Force the normal mode

for the first device

Send CF13 as

broadcast

Send CF14 as

broadcast

Reset the first device

from NMD

The device read the

ADC value again and set

correct address

Set the PMC for the

first device CF7

Set the first device to

repeater−slave mode

Force the normal mode

for other devices

Send CF13 as

broadcast

Reset the other devices

from NMD

Send CF14 as

broadcast

All devices have correct address

Figure 24. Multi−level Addressing Procedure with Long Time Delay at ADC2/ADR Pin

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57

EEPROM Write and Read Operations

Send CF1

Send CF3

CF3.EES == 0x2

CF3.EEBA ==

CF1.EEBA

CF3.EES == 0x0

CF3.EES == 0x1

Check CF3 EES

Complete

CF3.EES == 0x3

Handle error

Figure 25. EEPROM Write Operation

Send CF2

Send CF3

CF3.EES == 0x2

CF3.EEBA ==

CF1.EEBA

CF3.EES == 0x0

CF3.EES == 0x1

Check CF3 EES

Complete

CF3.EES == 0x3

Handle error

Figure 26. EEPROM Read Operation

www.onsemi.com

58

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SSOP36 EP

CASE 940AB

ISSUE A

DATE 19 JAN 2016

SCALE 1:1

NOTES:

0.20 C A-B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

D

4X

DETAIL B

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN

EXCESS OF THE b DIMENSION AT MMC.

4. DIMENSION b SHALL BE MEASURED BE-

TWEEN 0.10 AND 0.25 FROM THE TIP.

5. DIMENSIONS D AND E1 DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. DIMENSIONS D AND E1 SHALL BE

DETERMINED AT DATUM H.

A

X

36

19

X = A or B

e/2

E1

E

DETAIL B

6. THIS CHAMFER FEATURE IS OPTIONAL. IF

IT IS NOT PRESENT, A PIN ONE IDENTIFIER

MUST BE LOACATED WITHIN THE INDICAT-

ED AREA.

36X

0.25 C

PIN 1

REFERENCE

MILLIMETERS

1

18

DIM MIN

MAX

2.65

0.10

2.60

0.30

0.32

e

A

A1

A2

b

---

36X b

B

M

S

0.25

T A

B

2.15

0.18

0.23

NOTE 6

TOP VIEW

c

h _{DETAIL A}

A

A2

D

10.30 BSC

H

D2

E

5.70

5.90

10.30 BSC

7.50 BSC

3.90 4.10

0.50 BSC

0.25 0.75

0.90

c

E1

E2

e

h

0.10 C

h

A1

SEATING

PLANE

END VIEW

M1

36X

C

SIDE VIEW

D2

L

0.50

L2

M

0.25 BSC

0

8

_

M1

5

15

_

GENERIC

MARKING DIAGRAM*

GAUGE

PLANE

M

E2

XXXXXXXXXX

AWLYYWWG

L2

SEATING

PLANE

C

36X

L

DETAIL A

SOLDERING FOOTPRINT

BOTTOM VIEW

36X

1.06

5.90

XXXX = Specific Device Code

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

WL

YY

WW

G

4.10

10.76

*This information is generic. Please refer

to device data sheet for actual part

marking.

1

36X

0.36

0.50

PITCH

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON46215E

SSOP36 EXPOSED PAD

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

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


型号：	NCV78343DQ0R2G
厂家：	ONSEMI
描述：	Series String Pixel Controller for Automotive (Front) Lighting
文件：	总60页 (文件大小：685K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV78343DQ0R2G [ONSEMI]

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