NCV7750DPR2G_技术文档

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NCV7750

Quad Low-Side Relay Driver

The NCV7750 is an automotive four channel low−side driver

providing drive capability up to 600 mA per channel. Output control is

via a SPI port and offers convenient reporting of faults for open load

(or short to ground), overload, and overtemperature conditions.

Additionally, parallel control of the outputs is addressable (in pairs)

via the INx pins.

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A dedicated limp−home mode pin (LHI) enables OUT1−OUT4.

Each output driver is protected for overload current and includes an

output clamp for inductive loads.

MARKING

DIAGRAM

The NCV7750 is available in a SSOP−24 fused lead package.

Features

NCV7750

AWLYWWG

• 4 Low−Side Channels

• 600 mA Low−Side Drivers

SSOP−24

CASE 565AL

♦ R

1.1 W (Typ), 2.2 W (Max)

DS(on)

• 16−bit SPI Control

NCV7750 = Specific Device Code

♦ Frame Error Detection (8−bit)

♦ Daisy Chain Capable

A

= Assembly Location

WL

Y

= Wafer Lot

= Year

• Parallel Input Pins for PWM operation

• Power Up Without Open Circuit Detection Active (for LED

applications)

WW

G

= Work Week

= Pb−Free Package

• Low Quiescent Current in Sleep and Standby Modes

• Limp Home Functionality

ORDERING INFORMATION

See detailed ordering and shipping information on page 26 of

this data sheet.

• 3.3 V and 5 V compatible Digital Input Supply Range

• Fault Reporting

♦ Open Load Detection (selectable)

♦ Overload

♦ Overtemperature

• Power−on Reset (VDD, VDDA)

• SSOP−24 Package (internally fused leads)

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• These are Pb−Free Devices

Applications

• Automotive Body Control Unit

• Automotive Engine Control Unit

• Relay Drive

• LED Drive

• Stepper Motor Driver

1

Publication Order Number:

December, 2018 − Rev. 1

NCV7750/D

NCV7750

VDDA

VDD

Bias, Supply monitoring & POR

EN

OUT1

OUT2

OUT1

OUT2

CSB

SCLK

SI

SO

OUT3

OUT4

OUT3

OUT4

OUT1−OUT4

ON

SPI

Logic

Input

Control

LHI

OUT1

OUT2

OUT3

OUT4

IN1

IN2

IN3

IN4

Figure 1. Basic Block Diagram

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2

NCV7750

Vbat

14V

VDDA

VDD

10uF

OUT1

OUT2

OUT3

OUT4

0.1uF

5V

3.3V

or

0.1uF

5V

SO

CSB

SCLK

SI

GND

EN

GND

IN1

IN2

IN3

IN4

LHI

Figure 2. Application Diagram (relay loads)

1

GND

OUT1

OUT2

OUT3

OUT4

NC

VDDA

CSB

SI

EN

SCLK

SO

LHI

IN1

NC

IN2

NC

IN3

NC

IN4

GND

VDD

Figure 3. Pinout

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3

NCV7750

PACKAGE PIN DESCRIPTION

SSOP−24

Symbol

GND

OUT1

OUT2

OUT3

OUT4

NC

Description

1

2

Ground.

3

Channel 1 low−side drive output. Requires an external pull−up device for operation.

4

Channel 2 low−side drive output. Requires an external pull−up device for operation.

5

Channel 3 low−side drive output. Requires an external pull−up device for operation.

6

Channel 4 low−side drive output. Requires an external pull−up device for operation.

7

No Connection

8

NC

No Connection

9

NC

No Connection

10

11

12

13

14

NC

No Connection

GND

VDD

IN4

Ground.

Digital Power Supply for SO output (3.3 V or 5 V).

Parallel control of OUT4.

Ground if not used for best EMI performance.

Alternatively keep open and internal pull−down will hold the input low.

(120 kW pull down resistor).

15

16

17

18

IN3

IN2

IN1

LHI

Parallel control of OUT3.

Ground if not used for best EMI performance.

Alternatively keep open and internal pull−down will hold the input low.

(120 kW pull down resistor).

Parallel control of OUT2.

Ground if not used for best EMI performance.

Alternatively keep open and internal pull−down will hold the input low.

(120 kW pull down resistor).

Parallel control of OUT1.

Ground if not used for best EMI performance.

Alternatively keep open and internal pull−down will hold the input low.

(120 kW pull down resistor).

Limp Home Input. Active High.

A high on this pin powers up the device and activates the respective output drive INx designator.

Input SPI commands are ignored, but the output register reports faults.

(Read capability only. No write capability.)

All registers are reset coming out of LHI mode.

Ground if not used for best EMI performance.

Alternatively keep open and internal pull−down resistor (120 kW) will hold the input low.

19

20

21

22

23

24

SO

SCLK

EN

SPI serial data output. Output high voltage level referenced to pin VDD.

SPI clock (120 kW pull down resistor).

Global Enable (active high). (120 kW pull down resistor).

SPI serial data input (120 kW pull down resistor).

SPI Chip Select ”Bar” (120 kW pull up resistor to VDD).

Analog Power Supply Input voltage (5 V).

SI

CSB

VDDA

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4

NCV7750

MAXIMUM RATINGS

Parameter

Min

Max

5.5

Unit

Supply Input Voltage (VDDA, VDD)

DC

V

−0.3

Digital I/O pin voltage

V

−0.3

5.5

DD

(EN, LHI, INx, CSB, SCLK, SI)

(SO)

V

+ 0.3

High Voltage Pins (OUTx)

DC

−0.3

−1

36

Peak Transient

44 (Note 1)

Output Current (OUTx)

Clamping Energy

1.3

A

mJ

Maximum (single pulse) (Note 2)

Repetitive (multiple pulse) (Note 3)

−

75

−

Operating Junction Temperature Range

Storage Temperature Range

−40

−55

150

°C

V

ESD Capability,

Human body model (100 pF, 1.5 kW) (OUTx pins)

Human body model (100 pF, 1.5 kW) (all other pins)

−4000

−2000

4000

2000

AECQ10x−12−RevA

Short Circuit Reliability Characterization

Grade A

−

PACKAGE

Moisture Sensitivity Level

MSL2

−

Lead Temperature Soldering: SMD style only, Reflow (Note 4)

Pb−Free Part 60 − 150 sec above 217°C, 40 sec max at peak

265 peak

°C

Package Thermal Resistance (per JESD51)

°C/W

SSOP−24

2

Junction−to−Ambient (1s0p + 600 mm Cu) (Note 5)

Junction−to−Ambient (2s2p) (Notes 5 and 6)

Junction−to−Pin (pins 1, 2, 11, 12) (Note 7)

70

61

58

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Internally limited. Specification applies to unpowered and powered modes. (0 V to VDDA, 0 V to VDD)

2. Testing particulars, V = 14 V, 20 W, 640 mH, T = 150°C

bat

3. Testing particulars, 2M pulses, V = 15 V, 63 W, 390 mH, T = 25°C. (See Figure 4)

bat

A

4. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

and Application Note AND8083/D.

2

5. 76 mm x 76 mm x 1.5 mm FR4 PCB with additional heat spreading copper (2 oz) of 600 mm , LS1 to LS8 dissipating 100 mW each. No vias.

6. Include 2 inner 1 oz copper layers. No vias.

7. One output dissipating 100 mW.

Figure 4. Repetitive Clamping Energy Test

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5

NCV7750

ELECTRICAL CHARACTERISTICS (3.0 V < VDD ≤ VDDA, 4.5 V < VDDA (Note 8) < 5.5 V, −40°C v T v 150°C, EN = VDD, LHI

J

= 0 V unless otherwise specified).

Symbol

Characteristic

Conditions

Min

Typ

Max

Unit

GENERAL

I

Operating Current (VDDA)

ON Mode

mA

VDDA_ON

−

3

5

(All Channels On)

Quiescent Current (VDDA)

Global Standby Mode

(All Channels Off)

SI = SCLK = 0 V, CSB = VDD

mA

I

T = 25°C

−

32

35

40

VDDA_GS_25

VDDA_GS_85

J

T = 85°C

J

I

T = 150°C

VDDA_GS_150

J

Quiescent Current (VDDA)

Low Iq Mode

SI = SCLK = EN = 0 V, CSB = VDD

I

T = 25°C

−

10

20

VDDA_LO_25

VDDA_LO_85

J

T = 85°C

J

I

T = 150°C

VDDA_LO_150

J

I

Operating Current (VDD)

ON Mode

EN=high, SCLK = INx = 0 V,

CSB = VDD = VDDA

mA

VDD_ON

−

0.3

0.5

(All Channels On)

Quiescent Current (VDD)

Global Standby Mode

(All Channels Off)

CSB = VDD = VDDA, f

= 0 Hz

mA

SCLK

I

T = 25°C

−

20

40

VDD_GS_25

VDD_GS_85

J

T = 85°C

J

I

T = 150°C

VDD_GS_150

J

Quiescent Current (VDD)

Low Iq Mode

EN = 0 V

mA

I

T = 25°C

−

5

VDD_LO_25

VDD_LO_85

J

T = 85°C

J

I

T = 150°C

20

VDD_LO_150

POR_VDDA_rise

POR_VDDA_fall

POR_VDDA_hys

J

Power−on Reset threshold (VDDA)

VDDA rising

VDDA falling

−

3.60

3.30

200

3.85

3.50

350

V

3.00

150

Power−on Reset hysteresis (VD-

DA)

mV

Power−on Reset threshold (VDD)

Power−on Reset Hysteresis (VDD)

Thermal Shutdown (Note 9)

Thermal Hysteresis

VDD rising

−

2.4

100

175

25

2.7

240

200

−

V

POR_VDD_rise

75

mV

°C

POR_VDD_hys

TSD

Not ATE tested.

150

10

TSDhys

OUTPUT DRIVER

R

Output Transistor R

IOUTx = 180 mA

−

1.1

2.2

1.3

W

A

DS(on)

I

OL

Overload Detection Current

Output Leakage

0.6

0.95

I

OUTx = 13.5 V, 25°C

OUTx = 13.5 V

OUTx = 35 V

−

1

5

10

mA

leak_typ

I

leak_temp

I

leak_HV

CLAMP

Output Clamp Voltage

VDD = 0 V to 5.5 V

VDDA = 0 V to 5.5 V

IOUTx = 50 mA

36

40

44

V

BODY

Output Body Diode Voltage

IOUTx = −180mA

−

1.5

2.5

V

OPEN_V

OPEN_I

Open Load Detection Threshold

Voltage (Vol)

1.0

1.75

Open Load Diagnostic Sink Cur-

rent (Iol)

1 V < OUTx < 13.5 V, Output

Disabled

20

60

100

mA

OUTPUT TIMING SPECIFICATIONS

t

Enable (EN) wake−up time

CSB = 0 V

EN going high 80% to SO active

−

200

ms

WU

t

Enable (EN) and LHI (Note 10)

Signal Duration

50

−

Sig

8. Reduced performance down to 4 V provided VDDA Power−On Reset threshold has not been breached.

9. Each output driver is protected by its’ own individual thermal sensor.

10.Input signals H→L→H greater than 50usec are guaranteed to be detected.

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6

NCV7750

ELECTRICAL CHARACTERISTICS (3.0 V < VDD ≤ VDDA, 4.5 V < VDDA (Note 8) < 5.5 V, −40°C v T v 150°C, EN = VDD, LHI

J

= 0 V unless otherwise specified).

Symbol

Characteristic

Conditions

Min

Typ

Max

Unit

OUTPUT TIMING SPECIFICATIONS

t

Serial Control

Output turn−on time

All Channels

CSB going high 80% to OUTx going

−

30

50

ms

SPI_ON

low 20% V ,V = 13.5 V,

bat bat

I

= 180 mA resistive load

DS

t

Serial Control

Output turn−off time

All Channels

CSB going high 80% to OUTx going

high 80% V , V = 13.5 V,

−

30

50

ms

SPI_OFF

bat

I

= 180 mA resistive load

DS

t

Parallel Control

Output turn−on time

All Channels

INx going high 80% to OUTx going

low 20% V , V = 13.5 V,

Logic_ON

bat

I

= 180 mA resistive load

DS

t

Parallel Control

Output turn−off time

All Channels

INx going low 20% to OUTx going

high 80% V , V = 13.5 V,

Logic_OFF

bat

I

= 180 mA resistive load

DS

t

Overload Shut−Down Delay Time

3

15

50

ms

OVER

Open Load Detection Time

30

115

200

OPEN

DIGITAL INTERFACE CHARACTERISTICS

INPUT CHARACTERISTICS

LOGIC_V

LOGIC_H1

LOGIC_H2

RI_PD

Digital Input Threshold

0.8

50

1.4

175

400

120

2.0

300

800

190

V

(CSB, SI, SCLK, LHI, EN,INx)

Digital Input Hysteresis

(CSB, SI, SCLK, INx)

mV

kW

Digital Input Hysteresis

(LHI, EN)

150

50

Input Pulldown Resistance

(SI, SCLK, LHI, EN,INx)

INx = SI = SCLK = LHI = EN = VDD

RI_PU

Input Pullup Resistance (CSB)

CSB Leakage to VDD

CSB = 0 V

50

−

120

−

190

100

kW

uA

CSB = 5 V, VDD = 0 V

CSB = 5 V, VDDA = 0 V

CSB_leak_VDD

CSB_leak_VDDA

CSB Leakage to VDDA

−

OUTPUT CHARACTERISTICS

SO_HI

SO – Output High

I(out) = −1.5 mA

V

DD

0.4

−

V

SO_LO

SO – Output Low

I(out) = 2.0 mA

CSB = VDD

−

0.6

3

V

SO_TS_leak

SO Tri−state Leakage

−3

0

mA

SPI TIMING (all timing specifications measured at 20% and 80% voltage levels)

freq

I/f

SCLK Frequency

SCLK Clock Period

SCLK High Time

SCLK Low Time

SI Setup Time

−

200

85

50

100

1.5

85

−

5

−

MHz

ns

ms

t

Figure 5, #1

Figure 5, #2

−

SCLK_HI

t

−

SCLK_LO

t

Figure 5, #11

Figure 5, #12

Figure 5, #5, 6

Figure 5, #7

−

SI_SU

t

SI Hold Time

−

SI_hold

t

CSB Setup Time

CSB High Time

SCLK Setup Time

−

CSB_SU

t

−

CSB_HI

t

Figure 5, #3, 4

−

ns

SCLK_SU

t

SO Output Enable Time

(CSB falling to SO valid)

Figure 5, #8, C

= 50 pF

200

SO_EN

load

Not ATE tested

t

SO Output Disable Time

Figure 5, #9

−

200

100

ns

SO_DIS

(CSB rising to SO tri−state)

Not ATE tested

t

SO Output Data Valid Time with

capacitive load

Figure 5, #10, C

= 50 pF

SO_valid

load

Not ATE tested

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7

NCV7750

4

7

CSB

6

5

SCLK

1

2

3

CSB

SO

8

9

SI

12

SCLK

11

10

SO

Figure 5. Detailed SPI Timing (measured at 20% and 80% voltage levels)

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8

NCV7750

TYPICAL PERFORMANCE GRAPHS

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

6.0

5.0

4.0

3.0

2.0

1.0

150°C

−40°C

25°C

V

DD

= 5 V

0

−40 −20

0

20

40

60 80 100 120 140

3

3.5

4

4.5

5

5.5

TEMPERATURE (°C)

VDDA (V)

Figure 6. VDD Low I_qCurrent vs. Temperature

Figure 7. VDDA Low I_qQuiescent Current vs.

VDDA

4.5

4

1.4

1.2

3.5

3

1.0

0.8

0.6

0.4

0.2

0

2.5

2

150°C

1.5

1

25°C

V

= 5 V

0.5

DDA

−40°C

0

−40 −20

0

20

40

60 80 100 120 140

3

3.5

4

4.5

5

5.5

TEMPERATURE (°C)

VDD (V)

Figure 8. VDDA Low I_qCurrent vs.

Temperature

Figure 9. VDD Low I_qCurrent vs. VDD

44

43

42

41

40

39

38

37

36

44

43

42

41

40

39

38

37

36

180 mA

50 mA

50

70

90

110

130

150

170

−40 −20

0

20 40

60

80 100 120 140

OUTPUT CURRENT (mA)

TEMPERATURE (°C)

Figure 10. Output Clamp Voltage vs. Current

Figure 11. Output Clamp Voltage vs.

Temperature

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9

NCV7750

TYPICAL PERFORMANCE GRAPHS

1.3

1.2

1.1

3.0

2.5

2.0

1.5

1.0

0.9

0.8

0.7

0.6

I

= 600 mA

OUT

I

= 100 mA

OUT

0.5

0

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60 80 100 120 140

TEMPERATURE (°C)

Figure 12. Output R_DS(on)vs. Temperature

Figure 13. Overload Current vs. Temperature

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T = 150°C

OUTx = 13.5 V

13.5 14

14.5 15 15.5

16 16.5 17

17.5 18

−40 −20

0

20

40

60 80 100 120 140

OUTPUT VOLTAGE (V)

TEMPERATURE (°C)

Figure 14. Output Leakage vs. Voltage (1505C)

Figure 15. Output Leakage vs. Temperature

2.5

2.0

1.5

1.0

0.5

0

100

90

80

70

60

50

40

30

20

10

0

OUTx = 13.5 V

−40 −20

0

20

40

60 80 100 120 140

−40 −20

0

20

40

60 80 100 120 140

TEMPERATURE (°C)

Figure 16. Output Load Detection Current vs.

Temperature

Figure 17. Open Load Detection Voltage vs.

Temperature

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10

NCV7750

TYPICAL PERFORMANCE GRAPHS

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

I

= −180 mA

OUT

−40 −20

0

20

40

60 80 100 120 140

TEMPERATURE (°C)

Figure 18. Output Body Diode Voltage vs.

Temperature

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11

NCV7750

DETAILED OPERATING DESCRIPTION

Power Outputs

EN pin. The NCV7750 device will go through a power up

reset each time the EN pin is toggled low to high resulting

in a device setup of default values as described in the

Register Specifics section. Standby Mode, Input Mode, ON

Mode, and OFF Mode are all selectable via the SPI for each

channel independently.

The NCV7750 provides four independent 600mA power

transistors with their source connection referenced to the

ground pin and with their drain connection brought out to

individual pins resulting in 4 independent low−side drivers.

Output driver location on one side of the IC layout provides

for optimum pcb layout to the loads.

Internal clamping structures are provided to limit

transient voltages when switching inductive loads. Each

output has an overload detection current of 0.6 A (min)

where the drivers turn−off and stay latched off. An Overload

Current Shut−Down Delay Time of 3 ms (min) is designed

into the IC as a filter allowing for spikes in current which

may occur during normal operation and allowing for

protection from overload conditions.

Power up, Power−On Reset (UVLO mode)

Both VDD and VDDA supply an independent

power−on−reset function to the IC. Coming out of

power−on−reset all input bits are set to a 1 (OFF Mode) and

all output bits are set to a 0 except for the TER bit which is

set to a 1. The device cannot operate without both supplies

above their respective power−on reset thresholds with the

exception of LHI mode. During LHI mode, VDD POR is

ignored and the device is only affected by VDDA POR.

The NCV7750 powers up into the Global OFF Mode

without the open circuit diagnostic current enabled. This

allows the device to be turned on via EN = 0 to EN = 1 with

LED loads avoiding illumination of the LED loads

(reference Figure 21 State Diagram). All other paths to

Global OFF Mode enable open circuit diagnostic current.

Faults can be cleared with the SPI input register

(command 00), via a power−on−reset, or coming out of LHI

mode. Fault detection is provided in real time. Detection is

provided both during output turn−on and with output already

on. (See Page 17, Clearing the Fault Registers)

The NCV7750 is available in a SSOP−24 package.

Output Control (SPI)

Each output driver is controlled via a digital SPI port after

the device has powered up (out of POR) and enabled via the

Table 1. MODES OF OPERATION

Modes of

Operation

Conditions

Description

UVLO Mode

VDD or VDDA below their respective POR

thresholds

All outputs off in this mode.

Coming out of this mode

with EN = 1 sets all channels in the OFF mode

without open circuit diagnostic current enabled.

With LHI = 1 and EN = x, the part enters limp home mode.

OFF Mode

Global OFF Mode

ON Mode

SPI Control

Output off.

(Command 11)

Open circuit diagnostic current is disabled (powerup mode).

Open circuit diagnostic current is enabled (normal mode).

SPI Control

All Channels (Command 11)

Output off.

Open circuit diagnostic current is disabled (powerup mode).

Open circuit diagnostic current is enabled (normal mode).

SPI Control

(Command 10)

Output on.

Limp Home Mode

(LHI)

LHI = high, EN = x

Dedicated output turn on control of

OUT1−OUT4 using IN1−IN4.

Low Iq Mode

EN = LHI = low

Provides a state with the lowest quiescent current for V

and VDDA.

DD

Standby Mode

SPI Control

(Command 00)

Provides an OFF state with

Open circuit diagnostic current disabled.

Global

Standby Mode

SPI Control

All Channels (Command 00)

Provides a reduced quiescent current mode.

Provides an OFF state with

Open circuit diagnostic current disabled.

Input Mode

SPI Control

(Command 01)

Directs output channel to be driven from INx input pins.

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12

NCV7750

Figure 19. Basic State Diagram

Figure 20. Normal Operation State Diagram

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13

NCV7750

Figure 21. Detailed State Diagram

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14

NCV7750

Limp Home and PWM operation (INx control)

Pulse Width Modulation techniques are allowed utilizing the parallel inputs (INx).

Output pins (OUTx) are programmed for use in conjunction with the INx pins using the SPI command (command 01).

The LHI pin controls the operation of the INx pins.

LHI = Low and EN = High

With LHI=low, outputs are controlled by the INx pins (via SPI programming).

IN1 controls channels OUT1.

IN2 controls channels OUT2.

IN3 controls channels OUT3.

IN4 controls channels OUT4.

Alternatively, any of the four channels can be commanded off.

Output pins (OUTx) are programmed for use in conjunction with the INx pins

using the SPI command (command 01).

It’s important to note faults occurring during PWM operation (LHI=low) must be cleared via the SPI or POR.

LHI = High

To go into limp home mode, bring LHI=high, the corresponding outputs of IN1−IN4 will turn on or off.

During Limp Home Mode, overload and overtemperature sensing are functional, and are reported via the SPI

port. But, since input SPI commands are ignored with LHI = high, driver turn−off (overload or overtemperature)

occurring when LHI=high can only be re−initiated by toggling LHI or through a POR of VDDA.

All registers are reset coming out of LHI mode. The device enters OFF mode (EN = 1) or Low Iq Mode (EN

= 0) depending on the state of the EN pin. Open Load diagnostics are disabled in both cases.

UVLO (Under Voltage Lockout with LHI = High)

A breach of VDDA Power−On Reset thresholds will cause the outputs to turn off and enter the UVLO mode. In LHI mode

(LHI = 1), VDD POR is ignored. If VDD is below the operation of SO drive capability, fault information is preserved and can

be retrieved when SO drive capability is restored.

TER

A transmission error bit (TER) is set (”1”) when exiting the Limp Home Mode into Global Off Mode.

See Frame Detection Transmission Error Section for operation details.

Enable Input (EN)

The EN input pin is a logic controlled input with a voltage threshold between 0.8 V and 2.0 V. The device powers up when

EN goes from low to high, and exits Low Iq Mode (with LHI = 0 V) into global Off Mode. Device power up is also controlled

via the Limp Home Input (LHI) as an OR’d condition. The EN input is a don’t care when the LHI pin is driven from low to

high. In this situation, the device enters Limp Home Mode.

Output Drive Clamping

Internal zener diodes (Z1 & Z2, Figure 22) help to protect the output drive transistors from the expected fly back energy

generated from an inductive load turning off. Z1 provides the voltage setting of the clamp (along with V of the output

gs

transistor and Z2) while Z2 isolates Z1 from normal turn−on activity.

The output clamp voltage is specified between 36 V and 44 V. This includes clamping operation during unpowered input

supplies (VDD and VDDA). Device protection will be provided when the load is driven from an alternative driver source. This

is an important feature when considering protecting for load dump with an un−powered IC.

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15

NCV7750

VDD

OUTx

Vbat

VDDA

V_BAT

Z1

GND

drain

V_Clamp= 36V (min) to 44V (max) Powered

Z2

g

s

VDD

OUTx

VDDA

V_BAT

Alternative

Driver

Source

Vdrain =VZ 1+VZ 2+Vgs

GND

V_Clamp= 36V (min) to 44V (max) Un-pow

ered

Figure 22. Output Clamp

Overtemperature / Thermal Shutdown

The NCV7750 incorporates four individual thermal sensors located in proximity to each output driver. A channel is latched

off upon the detection of an overtemperature event. This allows operation of unaffected channels before, during, and after a

channel detection of overtemperature. The thermal shutdown detection threshold is typically 175°C with 25°C of hysteresis.

Open Load Detection

Open Load Detection is achieved for each output with the Open Load Detection Threshold Voltage reference voltage (Vol)

and its’ corresponding Open Load Diagnostic Sink Current (when the output driver (OUTx) is off). The output driver maintains

its’ functionality with and without the open fault bit set (Iol) (i.e. it can turn on and off).

During normal operation, the open circuit impedance (Roc) is 0 W. This sets the voltage on OUTx to V

volts. As long

and the voltage

BAT

as V

is above Vol no open circuit fault will be recognized. The voltage appearing on OUTx is a result of V

BAT

drop across Roc realized by the current flow created by Iol.

The NCV7750 voltage level trip points are referenced to ground. The threshold range is between 1.0 V and 2.5 V.

With a nominal battery voltage (V ) of 14 V, the resultant worst case thresholds of detection are as follows.

BAT

ǒ

Ǔ

V

_BAT* OpenLoadDetectionThresholdVoltage

+ OpenLoad Impedance

OpenLoadDiagnosticSinkCurrent

ǒ

Ǔ

ǒ

Ǔ

14 V * 2.5 V

100 mA

14 V * 1.0 V

20 mA

+ 115 kW

+ 650 kW

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16

NCV7750

V

BAT

Open

Load

Flag

Channel x

+

−

Open Load

detection

Vol

Roc

1.75V

Iol

OUTx

60uA

Output

Turn−on

Control

GND

Open Load Detection

is active when the driver is off,

in LHI mode,

Vol = Open Load Detection Threshold Voltage

Iol = Open Load Diagnostic Sink Current

or OFF mode (command 11).

Figure 23. Open Load Detection

NOTE: Detection of an open load condition is limited by the Parallel Control Output turn−off time and the Open Load

Detection Time specifications. The maximum allowable frequency of operation for PWM (pulse width

modulation) using the INx inputs is calculated from the maximum limits of these specifications. INx must be low

for longer than the sum of these maximum specifications (50 msec and 200 msec). Assuming a 50% duty cycle

yields a maximum frequency of operation of [1/(2*(50m + 200m))]=2 kHz.

LED Loads

The NCV7750 features a power up feature for the Global OFF Mode enabling the part to power up in a mode without the

open load diagnostic current enabled. This averts any unintended illumination of LED loads during power up.

Programming Features

The NCV7750 provides two registers.

1. Input Register. Input for IC mode state and output driver state control.

2. Output Register. Provides diagnostic information on the output driver condition.

Clearing the Fault Registers

Registers are reset with the following conditions.

1. Channel in Standby Mode. (corresponding addressed channel)

2. Power−on reset of VDD. (all channels)

3. Power−on reset of VDDA. (all channels)

4. EN low. (all channels)

5. Coming out of Limp Home Mode(LHI). (all channels)

SPI−Interface

The device provides a 16 bit SPI−interface for output drive control and fault reporting. Data is imported into the NCV7750

through the SI (serial input) pin. Data is exported out of the NCV7750 through the SO (serial output) pin.

The input−frame (SI) (2 bits / channel) is used to command the output stages.

The response frame (SO) provides channel−specific (2 bits / channel) status information fault reporting.

Words should be composed of 16 bits MSB (most significant bit) transmitted first.

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17

NCV7750

SO Output Driver

The digital power supply connection (VDD) to the SO output driver enables the system designer to interface the NCV7750

to both 3.3V and 5V logic systems. Figure 24 shows the internal connection of the SO pin.

VDD

3.3V or 5V

SO

Figure 24. SO Output Driver

Overload

Each output has an overload detection current of 0.6 A (min) where the drivers turn−off and stay latched off when an overload

condition is detected. A latched off condition must be cleared via the SPI port before it can be turned on. An Overload Current

Shut−Down Delay Time of 3 ms (min) is designed into the IC as a filter allowing for spikes in current which may occur during

normal operation and allowing for protection from overload conditions.

Overload is functional during Limp Home (LHI=high). Commands are ignored during Limp Home, but faults can still be

retrieved via the SPI.

Frame Detection Transmission Error (TER)

The NCV7750 detects the number of bits transmitted after CSB goes low. Bit counts not a multiple of 8 (16 bit minimum)

are reported as a fault on the TER bit. The transmission error information (TER) is available on SO after CSB goes low until

the first rising SCLK edge. Reference the Serial Peripheral Interface diagram (Figure 29).

In addition to unqualified bit counts setting TER = 1, the bit will also be set by

1. Coming out of UVLO.

2. Transitioning from Limp Home Mode to Global Off Mode.

3. Transitioning from Low Iq Mode to Global Off Mode.

The TER bit is cleared by sending a valid SPI command.

The TER bit is multiplexed with the SPI SO data and OR’d with the SI input (Figure 25) to allow for reporting in a serial

daisy chain configuration. A TER error bit as a “1” automatically propagates through the serial daisy chain circuitry from the

SO output of one device to the SI input of the next during the TER retrieval time when CSB goes low to the 1st rising edge

of the clock pulse. The SPI register controls the muxing of the output of the OR gate and the SO’ output of the SPI register

using the S mux select pin. This is shown in Figures 26 and 27 first as the daisy chained devices connected with no Transmission

Error (Figure 26) and subsequently with a Transmission Error in device 1 propagating through to device 2 (Figure 27).

TER False Reporting

st

SI should be in a low state during TER status retrieval (from CSB going low to the 1 rising edge of the clock pulse).

Figure 28 demonstrates what could happen if SI is a one during TER status retrieval. In this situation a “1” on SI propagates

to SO regardless of the state of TER. Hence a transmission error (TER) could be reported when it is not true.

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18

NCV7750

SO

SI

TER

SO

SI

SPI

S

Figure 25. TER SPI Link

SO SI

SI

SO

“0”

TER

“0”

TER

“0”

Device #1

NCV7750

Device #2

Figure 26. TER (no error)

SI

SO

SI

SO

“1”

“0”

“1”

TER

“1”

TER

“0”

Device #1

NCV7750

Device #2

Figure 27. TER Error Propagation

SI

“1”

SO

“don’t care”

TER

SO’

SI’

SPI

Mux Select

S

register

Figure 28. TER False Reporting

st

NOTE: TER is valid from CSB going low until the 1 low−to−high transition of SCLK to allow for propagation of the SI signal. Reference

Figure 29.

For proper TER status retrieval, SI should be in a low state.

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19

NCV7750

TER Information Retrieval

TER information retrieval is as simple as bringing CSB high−to−low. No clock signals are required.

CSB

MSB

B15

LSB

B0

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

SI

SCLK

SO

B8

B6

B5

B2

TER

B15

B0

Figure 29. Serial Peripheral Interface

The timing diagram highlighted in Figure 29 shows the SPI interface communication.

Note:

1. The MSB (most significant bit) is the first transmitted bit.

2. Data is sampled from SI on the falling edge of SCLK

3. Data is shifted out from SO on the rising edge of SCLK

4. SCLK should be in a low state when CSB makes a transition.

Frame Detection

Input word integrity (SI) is evaluated by the use of a frame consistency check. The word frame length is compared to an

n * 8 bit (where n is an integer) acceptable word length (16−bit minimum) before the data is latched into the input register. This

guarantees the proper word length has been imported and allows for daisy chain operation applications with 8−bit SPI devices.

The frame length detector is enabled with the CSB falling edge and the SCLK rising edge.

Reference the valid SPI frame shown below. (Figure 30)

Frame detection mode ends with

CSB rising edge.

Frame detection starts

after the CSB falling edge

and the SCLK rising edge.

CSB

SCLK

B15

B14

B13

B12

4

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

14

B1

B0

SI

Internal Counter

1

2

3

5

6

7

8

9

10

11

12

13

15

16

Valid 16 bits shown

Figure 30. Frame Detection

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20

NCV7750

DAISY CHAIN SETUP

Serial Connection

Daisy chain setups are possible with the NCV7750. The serial setup shown in Figure 31 highlights the NCV7750 along with

any 16 bit device using a similar SPI protocol. Particular attention should be focused on the fact that the first 16 bits which are

clocked out of the SO pin when the CSB pin transitions from a high to a low will be the Diagnostic Output Data from the Fault

Output Register. These are the bits representing the status of the IC. Additional programming bits should be clocked in which

follow the Diagnostic Output bits. The timing diagram shows a typical transfer of data from the microprocessor to the SPI

connected IC’s.

CSB SCLK

IC3

CSB SCLK

IC2

CSB SCLK

IC1

IC4

NCV7750

Any IC

using 16 Bit

SPI

Any IC

using 16 Bit

SPI

Any IC

using 16 Bit

SPI

protocol

SO

SI

Figure 31. Serial Daisy Chain

CSB

SCLK

SI

1

^stCMD

2nd CMD

3rd CMD

4th CMD

Figure 32. Serial Daisy Chain Timing Diagram

Table 2. SERIAL DAISY CHAIN DATA PATTERN

CLK = 16 bits

CLK = 32 bits

2nd CMD

1st CMD

CLK = 48 bits

3rd CMD

CLK = 64 bits

4th CMD

IC4

IC3

1st CMD

IC4 DIAG

IC3 DIAG

IC2 DIAG

IC1 DIAG

2nd CMD

1st CMD

3rd CMD

IC2

IC4 DIAG

IC3 DIAG

IC2 DIAG

2nd CMD

1st CMD

IC1

IC4 DIAG

IC3 DIAG

micro

IC4 DIAG

Table 2 refers to the transition of data over time of the Serial Daisy Chain setup of Figure 31 as word bits are shifted through

the system. 64 bits are needed for complete transport of data in the example system. Each column of the table displays the status

after transmittal of each word (in 16 bit increments) and the location of each word packet along the way.

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21

NCV7750

8−bit Devices

The NCV7750 is also compatible with 8 bit devices due to the features of the frame detection circuitry. The internal bit

counter of the NCV7750 starts counting clock pulses when CSB goes low. The 1st valid word consists of 16 bits and each

subsequent word must be comprised of just 8−bits (reference the Frame Detection Section).

Compatibility

Note the SCLK timing requirements of the NCV7750.

CSB SCLK

IC1

The NCV7750

is also

compatible with

8−bit devices

Data is sampled from SI on the falling edge of SCLK.

Data is shifted out of SO on the rising edge of SCLK.

Devices with similar characteristics are required for

operation in a daisy chain setup.

IC2

NCV7750

Any IC

using 8 Bit

SPI

protocol

SO

SI

Figure 33. Serial Daisy Chain with 8−bit Devices

Parallel Connection

A more efficient way (time focused) to control multiple SPI compatible devices is to connect them in a parallel fashion and

allow each device to be controlled in a multiplex mode. Figure 34 shows a typical connection between the microprocessor or

microcontroller and multiple SPI compatible devices. In a serial daisy chain configuration, the programming information for

the last device in the serial string must first pass through all the previous devices. The parallel control setup eliminates that

requirement, but at the cost of additional control pins from the microprocessor for each individual CSB (chip select bar) pin

for each controllable device. Serial data is only recognized by the device that is activated through its’ respective CSB pin.

Figure 35 shows the waveforms for typical operation when addressing IC1.

NCV7750

CSB1

CSB2

IC1

SI

SCLK

CSB

SO

OUT1

OUT2

OUT3

SO

CSB

chip1

NCV7750

IC2

SI

CSB

SCLK

CSB

SO

chip2

CSB3

SCLK

OUT1

OUT2

OUT3

CSB

chip3

NCV7750

IC3

SI

SCLK

CSB

SO

OUT1

OUT2

OUT3

SI

Figure 34. Parallel Connection

Figure 35. Parallel Connection Timing Diagram

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22

NCV7750

Stepper Motor Operation

The NCV7750 device is capable of driving stepper motors. Stepper motors require 4 low−side drive outputs. Figure 36 below

illustrates a Unipolar stepper motor setup. For proper operation, the code listed in Table 3 should be used (and repeated) for

one way operation (clockwise). For reverse direction, simply reverse the code and repeat (counterclockwise). Outputs 1−4 are

utilized for one stepper usage. During operation waveforms similar to Figure 37 can be expected on the OUTx pins.

V

BAT

STEPPER

MOTOR

OUT1

OUT2

OUT3

OUT4

V

= 12 V

BAT

Figure 37. Typical Stepper Motor Waveform

(Unipolar Portescap 35L048L32U)

NCV7750

Figure 36. Stepper Motor Operation Setup

Table 3. NCV7750 STEPPER MOTOR CODE

OUT 4

OFF

ON

OUT 3

ON

OUT 2

OFF

ON

OUT 1

ON

OFF

ON

OFF

ON

{Repeat}

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23

NCV7750

SPI

CSB

SCLK

SI

Input Register(via SI)

Command

00=Stand−by Mode

Output On / Off Control

01=Input Mode

10=ON Mode

11=OFF Mode

SO

Output Register(via SO)

Fault Output Register

Open Load / (Overload or

Overtemperature)

Transmission Error Bit – Only valid from CSB going low to

SCLK going high.

Figure 38. SPI Register Overview

Figure 38 displays the functions controlled and reported via the SPI port.

The input register (Table 4) controls the input source (parallel or SPI) and the SPI input data.

The output register (Table 5) transmits the output fault bits and the frame detection integrity.

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24

NCV7750

SI SPI Input Data (16-bit serial structure of input word)

The 16−bit data received (SI) is decoded into instructions for each channel per the table below.

After a power−on reset, all register bits are set to a 1.

Table 4. SPI INPUT DATA

Unused

MSB

Unused

Channel 4

Channel 3

Channel 2

Channel 1

LSB

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

INPUT DATA REGISTER

Field

Bits

Description

channel x

(x = 1−4)

7, 6

5, 4

3, 2

1, 0

Command

00

Channel Stand−by Mode

Fast channel turn off

Corresponding Channel Fault Register reset

Diagnostic Current

Disabled

01

Input Mode

Channel Input directed to INx.

(reference PWM operation section).

Diagnostic Current

Enabled in OFF State.

10

11

ON Mode

Channel turned on.

Diagnostic Current

Disabled

OFF Mode

Channel turned off.

Diagnostic Current

Enabled (Disabled after POR)*

*For proper LED load operation.

SO (fault diagnostic retrieval)

Output fault diagnostics from the output fault diagnostic register are shifted out on any 16 bit word clocked into Serial Input

(SI).

Only output fault diagnostics and frame detection errors are available through the serial output (SO).

Table 5. SPI OUTPUT DATA

TER

X

OL4

D4

OL3

D3

OL2

D2

OL1

D1

FAULT DIAGNOSTIC REGISTER

Field

Bits

Description

TER

CSB high−to−low

prior to 1st

SCLK low−to−high

Transmission Error.

0 Successful transmission in previous communication.

1 Frame detection error in previous transmission

or exiting Limp Home Mode, exiting UVLO Mode, or exiting Low Iq mode to Global Off Mode.

Oln

1, 3, 5, 7

0, 2, 4, 6

Open Load

0 Normal Operation

1 Fault detected

(n = 1 − 4)

Dn

(n = 1 − 4)

Overload or Overtemperature

0 Normal Operation

1 Fault detected

X = Unused

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25

NCV7750

Table 6. FAULT CONDITIONS

Output

Fault

Memory

Condition

Miscellaneous

Open Load

Latched

Detected in Driver Off State (1.75 V [Typ] threshold) when detection is enabled.

Reported in Output Fault Diagnostics Register until cleared via the SPI port.

Output will maintain turn−on capability.

Short to Ground

Latched

N/A

Detected as part of the Open Load circuitry described above.

Protected via Overload and Overtemperature functions.

Short to V

bat

Overload

Latched

Detected in Driver On State

0.6 A [min], 1.3 A [max].

A latched off condition must be cleared via the SPI port before it can be turned on.

Overtemperature

Latched

Detected in IC On State (T = 175°C [Typ])

J

A latched off condition must be cleared via the SPI port before it can be turned on.

DEVICE ORDERING INFORMATION

Part Number

†

Package Type

Shipping

NCV7750DPR2G

SSOP−24

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

26

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SSOP24 NB

CASE 565AL−01

ISSUE O

DATE 06 JUL 2010

SCALE 1:1

0.20 C D

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION.

2X

D

A

24

13

4. DIMENSION D DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE

BURRS SHALL NOT EXCEED 0.15 PER SIDE.

DIMENSION E1 DOES NOT INLCUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.15 PER SIDE. D AND E1 ARE

DETERMINED AT DATUM H.

0.20 C D

L2

GAUGE

PLANE

2X

E1

E

L

SEATING

PLANE

C

DETAIL A

PIN 1

REFERENCE

5. DATUMS A AND B ARE DETERMINED AT

DATUM H.

1

12

0.25 C D

e

MILLIMETERS

2X 12 TIPS

DIM MIN

MAX

1.75

0.25

1.50

0.30

0.25

24X b

B

A

A1

A2

b

1.35

0.10

1.25

0.20

0.19

M

0.25

C A-B D

TOP VIEW

c

D

8.65 BSC

A

A2

h

E

6.00 BSC

3.90 BSC

0.65 BSC

H

x 45°

0.10 C

E1

e

M

h

0.22

0.50

1.27

L

0.40

L2

M

0.25 BSC

c

A1

SEATING

PLANE

0

8

_

DETAIL A

24X

END VIEW

C

SIDE VIEW

GENERIC

MARKING DIAGRAM*

RECOMMENDED

SOLDERING FOOTPRINT

24X

0.42

24X

1.12

XXXXXXXXXG

AWLYYWW

24

13

XXXX = Specific Device Code

6.40

A

= Assembly Location

= Wafer Lot

WL

YY

WW

G

= Year

= Work Week

= Pb−Free Package

1

12

0.65

PITCH

(Note: Microdot may be in either location)

DIMENSIONS: MILLIMETERS

*This information is generic. Please refer

to device data sheet for actual part

marking.

98AON52092E

DOCUMENT NUMBER:

STATUS:

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

ON SEMICONDUCTOR STANDARD

1

NEW STANDARD:

Case Outline Number:

http://onsemi.com

1

October, 2002 − Rev. 0

DESCRIPTION: SSOP24 NB

PAGE 1 OFX2XX

DOCUMENT NUMBER:

98AON52092E

PAGE 2 OF 2

ISSUE

REVISION

DATE

06 JUL 2010

O

RELEASED FOR PRODUCTION. REQ. BY B. MARQUIS.

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Case Outline Number:

July, 2010 − Rev. 01O

565AL

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1


型号：	NCV7750DPR2G
厂家：	ONSEMI
描述：	4 沟道低压侧继电器驱动器驱动继电器驱动器
文件：	总30页 (文件大小：424K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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