NCV7342D13R2G [ONSEMI]
High Speed Low Power CAN Transceiver; 高速低功耗CAN收发器
| 型号： | NCV7342D13R2G |
| 厂家： | 
ONSEMI |
| 描述： | High Speed Low Power CAN Transceiver |
| 文件： | 总15页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7342
High Speed Low Power CAN
Transceiver
Description
The NCV7342 CAN transceiver is the interface between a
controller area network (CAN) protocol controller and the physical
bus and may be used in both 12 V and 24 V systems. The transceiver
provides differential transmit capability to the bus and differential
receive capability to the CAN controller.
The NCV7342 is an addition to the CAN high−speed transceiver
family complementing NCV734x CAN stand−alone transceivers and
previous generations such as AMIS42665, AMIS3066x, etc.
Due to the wide common−mode voltage range of the receiver inputs
and other design features, the NCV7342 is able to reach outstanding
levels of electromagnetic susceptibility (EMS). Similarly, extremely
low electromagnetic emission (EME) is achieved by the excellent
matching of the output signals.
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MARKING
DIAGRAM
8
8
NV7342−x
ALYW G
G
1
SOIC−8
CASE 751AZ
1
NV7342−x= Specific Device Code
x = 0 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
A
L
Y
W
G
• Compatible with the ISO 11898−2, ISO 11898−5 Standards
• High Speed (up to 1 Mbps)
• V Pin on NCV7342−3 Version Allowing Direct Interfacing with
IO
3 V to 5 V Microcontrollers
(Note: Microdot may be in either location)
• V
Pin on NCV7342−0 Version for Bus Common Mode
SPLIT
Stabilization
PIN ASSIGNMENT
• Very Low Current Consumption in Standby Mode with Wake−up via
the Bus
• Excellent Electromagnetic Susceptibility (EMS) Level Over Full
Frequency Range. Very Low Electromagnetic Emissions (EME) Low
EME Also Without Common Mode (CM) Choke
• Bus Pins Protected Against >15 kV System ESD Pulses
8
7
6
5
1
2
3
4
TxD
STB
GND
CANH
CANL
V
CC
• Transmit Data (TxD) Dominant Time−out Function
• Bus Dominant Time−out function in Standby Mode
• Under All Supply Condition the Chip Behaves Predictably
• No Disturbance of the Bus Lines with an Unpowered Node
• Thermal Protection
V
SPLIT
RxD
NCV7342D10R2G
(Top View)
8
7
6
5
1
2
3
4
• Bus Pins Protected Against Transients in an Automotive
TxD
STB
Environment
• Bus Pins Short Circuit Proof to Supply Voltage and Ground
• These are Pb−Free Devices
GND
CANH
CANL
V
CC
Quality
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
V
IO
RxD
NCV7342D13R2G
(Top View)
Typical Applications
• Automotive
• Industrial Networks
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
December, 2013 − Rev. 1
NCV7342/D
NCV7342
Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES
Symbol
Parameter
Power supply voltage
Undervoltage detection voltage on pin
Conditions
Min
4.5
3.5
Max
5.5
Unit
V
V
CC
UVDVCC
V
4.5
V
V
(NCV7342−3 only)
CC
I
Supply current
Dominant; V
= 0 V
TxD
75
10
mA
CC
TxD
Recessive; V
= V
IO
I
Supply current in standby mode
T v 100°C, (Note 1)
J
15
mA
CCS
including V current
IO
V
DC voltage at pin CANH
DC voltage at pin CANL
0 < V < 5.5 V; no time limit
−50
−50
−50
+50
+50
+50
V
V
V
CANH
CC
V
0 < V < 5.5 V; no time limit
CC
CANL
V
DC voltage between CANH and CANL
pin
0 < V < 5.5 V
CANH,L
CC
V
Electrostatic discharge voltage
IEC 61000−4−2 at pins CANH
−15
1.5
15
3
kV
V
ESD
and CANL
V
Differential bus output voltage in
dominant state
45 W < R < 65 W
O(dif)(bus_dom)
LT
CM−range
Input common−mode range for
comparator
Guaranteed differential receiver
threshold and leakage current
−35
+35
V
C
Load capacitance on IC outputs
15
pF
ns
load
t
Propagation delay TxD to RxD
(NCV7342−0 version)
See Figure 8
See Figure 8
50
50
230
pd0
t
Propagation delay TxD to RxD
(NCV7342−3 version)
230
150
ns
pd3
T
Junction temperature
−40
°C
J
1. Not tested in production. Guaranteed by design and prototype evaluation.
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2
NCV7342
BLOCK DIAGRAMS
V
CC
3
V
V
CC
NCV7342−0
7
5
Thermal
CANH
Shutdown
1
8
V
CC
TxD
STB
Timer
CC
V
SPLIT
V
SPLIT
Driver
Mode &
6
CANL
Control
Wake−up
Control
4
2
Wake−up
RxD
COMP
COMP
Filter
GND
RB 20121109
Figure 1. NCV7342−0 Block Diagram
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3
NCV7342
V
IO
V
CC
5
3
V
V
IO
NCV7342−3
7
Thermal
CANH
Shutdown
1
8
TxD
STB
Timer
IO
Driver
Mode &
6
CANL
Control
Wake−up
Control
4
2
Wake−up
RxD
COMP
COMP
Filter
GND
RB 20121109
Figure 2. NCV7342−3 Block Diagram
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4
NCV7342
TYPICAL APPLICATION
VBAT
5V−reg
3V−reg
V
V
V
IO
IO
CC
7
3
5
R
= 60 W
LT
CANH
CANL
STB
8
Micro
C
= 4.7 nF
CAN
BUS
LT
NCV7342−3
RxD
TxD
Controller
4
1
6
R
= 60 W
LT
2
GND
GND
RB20120816
Figure 3. Application Diagram NCV7342−3
VBAT
IN
OUT
5V−reg
V
V
CC
CC
3
STB
R
= 60 W
LT
8
4
1
7
5
6
CANH
C
= 4.7 nF
LT
RxD
TxD
V
SPLIT
Micro
Controller
CAN
BUS
CANL
R
= 60 W
LT
2
RB20120816
GND
GND
Figure 4. Application Diagram NCV7342−0
Table 2. PIN FUNCTION DESCRIPTION
Pin
1
Name
TxD
Description
Transmit data input; Low input Ù dominant driver; internal pull−up current
2
GND
Ground
3
V
CC
Supply voltage
4
RxD
Receive data output; dominant transmitter Ù Low output
Input/Output pins supply voltage. On NCV7342−3 only
Common−mode stabilization output. On NCV7342−0 only
5
5
V
IO
V
SPLIT
6
7
8
CANL
CANH
STB
Low−level CAN bus line (Low in dominant mode)
High−level CAN bus line (High in dominant mode)
Standby mode control input
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5
NCV7342
FUNCTIONAL DESCRIPTION
NCV7342 has two versions which differ from each other
only by function of pin 5.
monitors the bus lines for CAN bus activity. The bus lines
are terminated to ground and supply current is reduced to a
minimum, typically 10 mA. When a wake−up request is
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
NCV7342−0: Pin 5 is common mode stabilization output
V
. (see Figure 4) This version is full replacement of
SPLIT
NCV7340.
a time period of t
. The RxD pin is driven Low by the
dwakerd
NCV7342−3: Pin 5 is V pin, which is supply pin for
IO
transceiver to inform the controller of the wake−up request.
transceiver digital inputs/output (supplying pins TxD, RxD,
STB) The V pin should be connected to microcontroller
IO
VIO Supply Pin
supply pin. By using V
supply pin shared with
IO
The V pin (available only on NCV7342−3 version)
IO
microcontroller, the I/O levels between microcontroller and
transceiver are properly adjusted. This adjustment allows
communication between 3 V microcontroller and the
transceiver. (See Figure 3)
should be connected to microcontroller supply pin. By using
V
IO
supply pin shared with microcontroller the I/O levels
between microcontroller and transceiver are properly
adjusted. See Figure 3. Pin V also provides the internal
IO
supply voltage for low−power differential receiver of the
transceiver. This allows detection of wake−up request even
Operating Modes
NCV7342 provides two modes of operation as illustrated
in Table 3. These modes are selectable through pin STB.
when there is no supply voltage on Pin V
.
CC
Split Circuit
The V
pin (available on NCV7342−0 version) is
Table 3. OPERATING MODES
SPLIT
operational only in normal mode. In standby mode this pin
is floating. The V can be connected as shown in
Figure 4 or, if it’s not used, can be left floating. Its purpose
Pin RxD
Pin
SPLIT
STB
Low
High
Low
High
Mode
Normal
Standby
Bus dominant
Bus recessive
is to provide a stabilized DC voltage of 0.5 · V to the bus
CC
reducing possible steps in the common−mode signal,
therefore reducing EME. These unwanted steps could be
caused by an unpowered node on the network with excessive
leakage current from the bus that shifts the recessive voltage
Wake−up
request
detected
No wake−up
request detected
Normal Mode
from its nominal 0.5 · V voltage.
CC
In normal mode, the transceiver is able to communicate
via the bus lines. The signals are transmitted and received to
the CAN controller via the pins TxD and RxD. The slopes
on the bus lines outputs are optimized to give extremely low
EME.
Wake−up
When a valid wake−up (dominant state longer than t
is received during the standby mode, the RxD pin is driven
Low after t . The wake−up detection is not latched:
RxD returns to High state after t
is released back to recessive – see Figure 5.
)
Wake
dwakerd
when the bus signal
dwakedr
Standby Mode
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
>t
Wake
<t
Wake
CANH
CANL
STB
RxD
t
t
dwakedr
dwakerd
time
normal
standby
RB20130219
Figure 5. NCV7342 Wake−up behavior
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6
NCV7342
Over−temperature Detection
state. If the dominant state on the bus is kept for longer time
than t , the RxD pin is released to High level. The
timer is reset when CAN bus changes from dominant to
recessive state. This feature prevents generating permanent
wake−up request by the bus clamped to the dominant level.
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 180°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes High. The thermal protection
circuit is particularly needed in case of a bus line failure.
dom(bus)
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by an accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
TxD Dominant Time−out Function
V
CC
supply dropping below V
undervoltage
UVDVCC
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication), if pin TxD is forced
permanently Low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
level will force transceiver to switch into the standby mode.
The logic level on pin STB will be ignored as long as
undervoltage condition is not recovered. (NCV7342−3
version only)
V
IO
supply dropping below V
undervoltage
UVDVIO
detection level will cause the transceiver to disengage from
internal timer value t , the transmitter is disabled,
dom(TxD)
the bus (no bus loading) until the V voltage recovers.
IO
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
(NCV7342−3 version only)
The pins CANH and CANL are protected against
automotive electrical transients (according to ISO 7637; see
Figure 6). Pins TxD and STB are pulled High internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
This TxD dominant time−out time (t
) limits the
dom(TxD)
minimum possible bit rate to 8 kbps.
Bus Dominant Time−out Function
Bus dominant time−out timer is started in the standby
mode when CAN bus changes from recessive to dominant
V
CC
supply be removed.
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NCV7342
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing
into the pin; sourcing current means the current is flowing out of the pin.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min
−0.3
−50
−50
−
Max
6
Unit
V
V
SUP
Supply voltage V , V
CC
IO
V
CANH
DC voltage at pin CANH
DC voltage at pin CANL
0 < V < 5.5 V; no time limit
50
50
58
V
CC
V
0 < V < 5.5 V; no time limit
V
CANL
CANH,Lmax
CC
V
DC voltage at pin CANH and CANL during load dump
condition
0 < V < 5.5 V; less than
one second
V
CC
V
DC voltage at V
pin (On NCV7342−0 version only)
0 < V < 5.5 V; no time limit
−50
−0.3
−4
50
6
V
V
SPLIT
SPLIT
CC
V
IO
DC voltage at pin TxD, RxD, STB
V
Electrostatic discharge voltage at all pins according to
EIA−JESD22
Note 2
4
kV
esd
Standardized charged device model ESD pulses
−750
−8
750
8
V
according to ESD−STM5.3.1−1999
Electrostatic discharge voltage at CANH,CANL, V
pins according to EIA−JESD22
Note 2
Note 3
kV
kV
SPLIT
Electrostatic discharge voltage at CANH, CANL pins
According to IEC 61000−4−2
−15
−150
15
V
schaff
Transient voltage at CANH, CANL pins, See Figure 6
Static latch−up at all pins
Note 4
Note 5
100
150
V
Latch−up
mA
°C
°C
°C
T
stg
Storage temperature
−55
−40
−40
+150
+125
+170
T
amb
Ambient temperature
T
J
Maximum junction temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
3. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 W resistor
referenced to GND. Verified by external test house
4. Pulses 1, 2a,3a and 3b according to ISO 7637 part 3. Verification by external test house.
5. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.
Table 5. THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
Free air
Value
125
75
Unit
K/W
K/W
R
Thermal Resistance Junction−to−Air, 1S0P PCB (Note 6)
Thermal Resistance Junction−to−Air, 2S2P PCB (Note 7)
q
JA_1
R
Free air
q
JA_2
6. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
7. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.
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8
NCV7342
Table 6. CHARACTERISTICS
V
V
= 4.5 V to 5.5 V; V = 2.8V to 5.5 V (Note 8); T = −40 to +150°C; R = 60 W unless specified otherwise. On chip versions without
IO J LT
CC
IO
pin reference voltage for all digital inputs and outputs is V instead of V
.
CC
IO
Symbol
SUPPLY (Pin V
Parameter
Conditions
Min
Typ
Max
Unit
)
CC
I
Supply current
Dominant; V
= 0 V
50
75
10
mA
mA
mA
CC
TxD
Recessive; V
= V
6.8
TxD
IO
I
I
Supply current in standby mode
for NCV7342−0
T v 100°C (Note 9)
J
8
15
0
CCS
Supply current in standby mode
T v 100°C (Note 9)
J
17
CCS3
for NCV7342−3 including current
into V
IO
V
CC
Undervoltage detection voltage on
pin (NCV7342−3 only)
3.5
4.5
V
V
CC
TRANSMITTER DATA INPUT (Pin TxD)
V
High−level input voltage
Low−level input voltage
High−level input current
Low−level input current
Input capacitance
Output recessive
Output dominant
2.0
−0.3
−5
6
0.8
5
V
IH
V
V
IL
I
IH
V
TxD
V
TxD
= V
IO
0
−200
5
mA
mA
pF
I
IL
= 0V
−385
−45
10
C
Not tested
i
TRANSMITTER MODE SELECT (Pin STB)
V
High−level input voltage
Standby mode
Normal mode
2.0
V
+0.3
V
IH
IO
(Note 10)
V
Low−level input voltage
High−level input current
Low−level input current
Input capacitance
−0.3
−5
0.8
5
V
IL
I
IH
V
STB
V
STB
= V
IO
0
−4
5
mA
mA
pF
I
IL
= 0 V
−10
−1
10
C
Not tested
i
RECEIVER DATA OUTPUT (Pin RxD)
I
High−level output current
Normal mode
−1.2
−0.4
−0.1
mA
OH
V
= V – 0.4 V
RxD
IO
I
Low−level output current
High−level output voltage
V
= 0.4 V
1.5
6
12
mA
V
OL
RxD
V
Standby mode
= −100 mA
V
IO
–
V
IO
V
– 0.4
OH
IO
I
1.1
–0.7
RxD
BUS LINES (Pins CANH and CANL)
V
Recessive bus voltage
V
= V ; no load; normal
2.0
−100
−2.5
−2.5
2.5
0
3.0
V
o(reces) (norm)
TxD
IO
on pins CANH and CANL
mode
V
Recessive bus voltage
on pins CANH and CANL
V
= V ; no load; standby
100
2.5
2.5
mV
mA
mA
o(reces) (stby)
TxD
IO
mode
I
Recessive output current at pin
CANH
−30 V < V
0 V < V < 5.5 V
< 35 V;
CANH
CC
o(reces) (CANH)
I
Recessive output current at pin
CANL
−30 V < V
0 V <V < 5.5 V
< 35 V;
o(reces) (CANL)
CANL
CC
I
Input leakage current to pin CANH
Input leakage current to pin CANL
0W < R(V to GND) < 1 MW
−10
−10
3.0
0
0
10
10
mA
mA
V
LI(CANH)
CC
0W < R(V to GND) < 1 MW
IO
CANH
I
V
CANL
= V
= 5 V (Note 8)
LI(CANL)
o(dom) (CANH)
V
Dominant output voltage at pin
CANH
V
TxD
= 0 V
3.6
4.25
8. Only version NCV7342−3 has V supply pin. In NCV7342−0 this supply is provided from V pin.
IO
CC
9. Not tested in production. Guaranteed by design and prototype evaluation.
10.In case V > V , the limit is V + 0.3 V
IO
CC
IO
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NCV7342
Table 6. CHARACTERISTICS
V
V
= 4.5 V to 5.5 V; V = 2.8V to 5.5 V (Note 8); T = −40 to +150°C; R = 60 W unless specified otherwise. On chip versions without
IO J LT
CC
IO
pin reference voltage for all digital inputs and outputs is V instead of V
.
CC
IO
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BUS LINES (Pins CANH and CANL)
V
Dominant output voltage at pin
CANL
V
V
= 0 V
0.5
1.5
1.4
2.25
0
1.75
3.0
50
V
V
o(dom) (CANL)
TxD
V
Differential bus output voltage
= 0 V; dominant;
o(dif) (bus_dom)
TxD
(V
CANH
− V
)
45 W < R < 65 W
CANL
LT
V
Differential bus output voltage
(V − V
V
= V ; recessive;
−120
0.9
mV
o(dif) (bus_rec)
TxD
IO
)
CANL
no load
CANH
V
Bus output voltage symmetry
+ V
V
V
V
= 0 V
1.1
−40
100
0.9
V
CC
o(sym) (bus_dom)
TxD
V
CANH
CANL
I
Short circuit output current at pin
CANH
= 0 V; V = 0 V
TxD
−90
40
−70
70
mA
mA
V
o(sc) (CANH)
CANH
CANL
I
Short circuit output current at pin
CANL
= 36 V; V
= 0 V
o(sc) (CANL)
TxD
V
Differential receiver threshold
voltage
−12 V < V
−12 V < V
< 12 V;
< 12 V;
0.5
0.7
i(dif) (th)
CANL
CANH
= 4.75 V to 5.25 V
V
CC
V
Differential receiver threshold
−30 V < V
−30 V < V
CC
< 35 V;
< 35 V;
0.40
0.4
0.7
0.8
1.0
V
V
ihcm(dif) (th)
CANL
CANH
voltage for high common−mode
V
= 4.75 V to 5.25 V
V
Differential receiver threshold
voltage in standby mode
−12 V < V
−12 V < V
CC
< 12 V;
< 12 V;
1.15
i(dif) (th)_STDBY
CANL
CANH
V
= 4.5 V to 5.5 V
R
Common−mode input resistance
15
15
26
26
0
37
37
kW
kW
%
i(cm) (CANH)
at pin CANH
R
Common−mode input resistance
at pin CANL
i(cm) (CANL)
R
Matching between pin CANH and
pin CANL common mode input
resistance
V
CANH
= V
CANL
−0.8
0.8
i(cm) (m)
R
Differential input resistance
Input capacitance at pin CANH
Input capacitance at pin CANL
Differential input capacitance
25
50
7.5
75
20
20
10
kW
pF
pF
pF
i(dif)
C
V
TxD
V
TxD
V
TxD
= V ; not tested
IO
i(CANH)
C
= V ; not tested
7.5
i(CANL)
IO
C
= V ; not tested
3.75
i(dif)
IO
COMMON−MODE STABILIZATION (Pin V
) Only for NCV7342−0 version
SPLIT
V
SPLIT
Reference output voltage at pin
SPLIT
Normal mode;
−500 mA < I
0.3
0.7
V
CC
V
< 500 mA
SPLIT
V
Reference output voltage at pin
R
> 1 MW
loadVsplit
0.45
0.55
V
SPLITo
CC
V
SPLIT
V
SPLIT
V
SPLIT
I
leakage current
limitation current
Standby mode
Normal mode
−5
5
5
mA
SPLIT(i)
I
1.3
mA
SPLIT(lim)
V
IO
SUPPLY VOLTAGE (Pin V ) Only for NCV7342−3 version
IO
V
Supply voltage on pin V
2.8
5.5
14
V
IO
IO
IO
IO
I
Supply current on pin V
Supply current on pin V
Standby mode
Normal mode
mA
mA
IOS
I
IONM
Dominant; V
= 0 V
0.30
0.29
0.70
0.44
1.10
0.68
TxD
Recessive; V
= V
TxD
IO
8. Only version NCV7342−3 has V supply pin. In NCV7342−0 this supply is provided from V pin.
IO
CC
9. Not tested in production. Guaranteed by design and prototype evaluation.
10.In case V > V , the limit is V + 0.3 V
IO
CC
IO
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10
NCV7342
Table 6. CHARACTERISTICS
V
V
= 4.5 V to 5.5 V; V = 2.8V to 5.5 V (Note 8); T = −40 to +150°C; R = 60 W unless specified otherwise. On chip versions without
IO J LT
CC
IO
pin reference voltage for all digital inputs and outputs is V instead of V
.
CC
IO
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
IO
SUPPLY VOLTAGE (Pin V ) Only for NCV7342−3 version
IO
V
Undervoltage detection voltage on
pin
1.3
2.7
V
UVDVIO
V
IO
THERMAL SHUTDOWN
Shutdown junction temperature
TIMING CHARACTERISTICS (See Figure 7 and 8)
T
J(SD)
junction temperature rising
160
180
200
°C
t
Delay TxD to bus active
C = 100 pF between CANH to
60
30
ns
ns
d(TxD−BUSon)
i
CANL
t
Delay TxD to bus inactive
C = 100 pF between CANH to
d(TxD−BUSoff)
i
CANL
t
t
Delay bus active to RxD
Delay bus inactive to RxD
C
C
= 15 pF
= 15 pF
60
70
ns
ns
ns
d(BUSon−RxD)
RxD
RxD
d(BUSoff−RxD)
t
t
Propagation delay TxD to RxD
dominant to recessive transition
C = 100 pF between CANH to
CANL, C
50
50
100
230
230
47
5
pd_dr
i
= 15 pF
RxD
Propagation delay TxD to RxD
recessive to dominant transition
C = 100 pF between CANH to
CANL, C
120
ns
ms
ms
ms
pd_rd
i
= 15 pF
RxD
t
Delay standby mode to normal
mode
d(stb−nm)
Dominant time for wake−up via
bus
0.5
1
t
Wake
Delay to flag wake event
(recessive to dominant transitions)
See Figure 5
Valid bus wake−up event,
= 15 pF
10
C
t
t
RxD
dwakerd
dwakedr
Delay to flag end of wake event
(dominant to recessive transition)
See Figure 5
Valid bus wake−up event,
C
0.5
5
ms
= 15 pF
RxD
t
TxD dominant time for time out
Bus dominant time out
V
= 0 V
1.3
1.3
3
3
ms
ms
dom(TxD)
TxD
t
Standby mode
dom(bus)
8. Only version NCV7342−3 has V supply pin. In NCV7342−0 this supply is provided from V pin.
IO
CC
9. Not tested in production. Guaranteed by design and prototype evaluation.
10.In case V > V , the limit is V + 0.3 V
IO
CC
IO
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11
NCV7342
MEASUREMENT SET−UPS AND DEFINITIONS
+
5 V
100 nF
V
IO
V
CC
3
5
CANH
7
TxD
RxD
1 nF
1
4
Transient
Generator
1 nF
6
CANL
2
8
STB
RB20121608
15 pF
GND
Figure 6. Test Circuit for Automotive Transients
+5 V
100 nF
V
IO
V
CC
47 uF
5
3
CANH
7
TxD
RxD
100 pF
1
R
L
4
6
CANL
2
8
STB
RB20120816
15 pF
GND
Figure 7. Test Circuit for Timing Characteristics
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12
NCV7342
recessive
TxD
recessive
50%
dominant
50%
CANH
CANL
0.9 V
V
i(dif)
= V
− V
0.5 V
CANH
CANL
0.3 x V
*
0.7 x V
*
CC
CC
RxD
t
t
d(TxD−BUSon)
d(TxD−BUSoff)
d(BUSon−RxD)
t
t
d(BUSoff−RxD)
t
t
pd_dr
pd_rd
*On NCV7342−3 V is replaced by V
RB20130429
CC
IO
Figure 8. Transceiver Timing Diagram
DEVICE ORDERING INFORMATION
Part Number
†
Description
Package
Shipping
High Speed CAN Transceiver
NCV7342D10R2G
NCV7342D13R2G
with Standby and V
pin
SPLIT
SOIC 150 8 GREEN (Matte Sn,
JEDEC MS−012)
3000 / Tape & Reel
High Speed CAN Transceiver
(Pb−Free)
with Standby and V pin
IO
(available in 2014)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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13
NCV7342
PACKAGE DIMENSIONS
SOIC 8
CASE 751AZ
ISSUE O
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14
NCV7342
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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NCV7342/D
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