NCV70516MW0R2G [ONSEMI]
Micro-stepping Motor Driver;
| 型号： | NCV70516MW0R2G |
| 厂家： | 
ONSEMI |
| 描述： | Micro-stepping Motor Driver |
| 文件： | 总24页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV70516
Micro-stepping Motor Driver
Description
The NCV70516 is a micro−stepping stepper motor driver for bipolar
stepper motors. The chip is connected through I/O pins and an SPI
interface with an external microcontroller. The NCV70516 contains
a current−translation table and takes the next micro−step depending on
the clock signal on the “NXT” input pin and the status of the “DIR”
(= direction) register or input pin. The chip provides an error message
if an electrical error, an under−voltage or an elevated junction
temperature is detected. It is using a proprietary PWM algorithm
for reliable current control.
www.onsemi.com
MARKING
DIAGRAMS
1
NCV70516 is fully compatible with the automotive voltage
requirements and is ideally suited for general−purpose stepper motor
applications in the automotive, industrial, medical, and marine
environment.
Due to the technology, the device is especially suited for use
in applications with fluctuating battery supplies.
N70516−0
FAWLYYWW
G
1
24
QFN24
CASE 485CS
Features
24
NV70516−0
1
AWLYYWW
• Dual H−bridge for 2−phase Stepper Motors
• Programmable Peak−current up to 800 mA
• Low Temperature Boost Current up to 1100 mA
• On−chip Current Translator
SSOP24
CASE 940AK
1
N70516−1
FAWLYYWWG
G
• SPI Interface
• 5 Step Modes from Full−step up to 16 Micro−steps
• Fully Integrated Current−sensing and Current−regulation
• PWM Current Control with Automatic Selection of Fast and Slow
Decay
24
1
QFNW24
CASE 484AF
N70516 or NV70516 =
= Specific Device Code
= Fab Indicator
• Fixed PWM Frequency
F
A
• Active Fly−back Diodes
= Assembly Location
= Wafer Lot
• Full Output Protection and Diagnosis
WL
YY
WW
G
= Year
• Thermal Warning and Shutdown
• Compatible with 3.3 V Microcontrollers, 5 V Tolerant Inputs, 5 V
Tolerant Open Drain Outputs
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
• Reset Function
• Overcurrent Protection
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
Compliant
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
June, 2018 − Rev. 1
NCV70516/D
NCV70516
TYPICAL APPLICATION SCHEMATIC
The application schematic below shows typical connections for applications with low axis counts and/or with software SPI
implementation. For applications with many stepper motor drivers, some “minimal wiring” examples are shown at the last
sections of this datasheet.
D1
100 nF
C4
100 nF
C3
100 nF
C2
VBAT
VDD
C1
100 uF
R1 R2
VDD
VBB
VBB
DIR
NXT
DO
R3
R4
R8
R5
R6
MOTXP
DI
NCV70516
C5
C6
CLK
MOTXN
uC
CSB
M
R7
R9
MOTYP
MOTYN
ERRB
C7
C8
GND
Figure 1. Typical Application Schematic
Table 1. EXTERNAL COMPONENTS
Component
C1
Function
Typ. Value
Max Tolerance
20%
Unit
mF
nF
nF
nF
kW
kW
W
V
V
V
buffer capacitor (Note 1)
22 ... 100
BB
BB
DD
C2, C3
C4
decoupling capacitor (Note 2)
decoupling capacitor (Note 3)
100
20%
100
20%
C5, C6, C7, C8
R1, R2
R3 – R7
R8, R9
D1
Optional EMC filtering capacitor (Note 4)
Pull up resistor
1 ... 3.3 max
20%
1..5
10%
Optional resistors
1
10%
Optional resistors (Note 5)
Optional reverse protection diode
100
10%
e.g. MURD530
1. Low ESR < 4 W, mounted as close as possible to the NCV70516. Total decoupling capacitance value has to be chosen properly to reduce
the supply voltage ripple and to avoid EM emission.
2. C2 and C3 must be close to pins VBB and coupled GND directly.
3. C4 must be a ceramic capacitor to assure low ESR.
4. Optional capacitors for improvement of EMC and system ESD performance. The slope times on motor pins can be longer than specified
in the AC table.
5. Value depends on characteristics of mC inputs for DO and ERRB signals.
www.onsemi.com
2
NCV70516
VDD
VBB
Internal voltage
regulator 3.3 V
Timebase
CLK
CSB
DI
EMC
MOTXP
MOTXN
P
W
M
T
TSD
SPI
R
A
N
S
L
A
T
O
R
I−sense
Open/
Short
DO
Logic &
Registers
NXT
DIR
EMC
MOTYP
MOTYN
P
W
M
OTP
POR
ERRB
I−sense
NCV70516
UV
detect
Band−
gap
GND
Figure 2. Block Diagram
www.onsemi.com
3
NCV70516
PACKAGE AND PIN DESCRIPTION
1
DIR
VBB
NC
MXP
1
CSB
MXP
DI
DO
GND
DI
GNDPW
MXN
MXN
MYN
MYN
GNDPW
MYP
MXN
DO
NCV70516
QFN24 5x5
ERRB
NC
MXN
MYN
MYN
GND
ERRB
NC
NCV70516
VDD
GND
CLK
NXT
NC
VDD
GND
MYP
VBB
Figure 3. Pin Connections – QFN24
Table 2. PIN DESCRIPTION
Figure 4. Pin Connections – SSOP24
Pin No.
Pin No.
QFN24 5x5
SSOP24 NB EP
Pin Name
DI
Description
I/O Type
1
2
4
5
SPI data input
Digital Input
Digital Output
Digital Output
DO
SPI data output
3
6
ERRB
NC
Error Output (Open Drain)
Not connected
4, 12, 19
5
2, 7, 12
8
VDD
Internal supply (needs external decoupling capacitor)
Ground
Supply
Supply
6
9
GND
7
10
CLK
SPI clock input
Digital Input
Digital Input
Supply
8
11
NXT
Next micro−step input
Battery voltage supply
Positive end of phase Y coil
Ground
9, 22
10, 11
13, 18
14, 15
16, 17
20, 21
23
13, 24
14, 15
16, 21
17, 18
19, 20
22, 23
1
VBB
MOTYP
GNDPW
MOTYN
MOTXN
MOTXP
DIR
Driver output
Supply
Negative end of phase Y coil
Negative end of phase X coil
Positive end of phase X coil
Direction input
Driver output
Driver output
Driver output
Digital Input
Digital Input
24
3
CSB
SPI chip select input
Table 3. ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Min
−0.3
−0.3
−50
−55
−2
Max
+40
+6.0
+175
+160
+2
Unit
V
Supply voltage (Note 6)
V
BB
Digital input/outputs voltage
V
IO
V
Junction temperature range (Note 7)
Storage Temperature (Note 8)
T
j
°C
°C
kV
kV
T
strg
HBM Electrostatic discharge voltage (Note 9)
System Electrostatic discharge voltage (Note 10)
V
esd_hbm
V
−8
+8
syst_esd
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
6. V Max is +43 V for limited time <0.5 s.
BB
7. The circuit functionality is not guaranteed.
8. For limited time up to 100 hours. Otherwise the max storage temperature is 85°C.
9. HBM according to AEC−Q100: EIA−JESD22−A114−B (100 pF via 1.5 kW).
10.System ESD, 150 pF, 330 W, contact discharge on the connector pin (VBB, MXN, MXP, MYN and MYP), unpowered.
www.onsemi.com
4
NCV70516
Operating ranges define the limits for functional
operation and parametric characteristics of the device. A
mission profile (Note 11) is a substantial part of the
operation conditions; hence the Customer must contact
ON Semiconductor in order to mutually agree in writing on
the allowed missions profile(s) in the application.
Table 4. RECOMMENDED OPERATING RANGES
Characteristic
Symbol
Min
+6
Typ
Max
+29
Unit
V
Battery Supply voltage
V
BB
Digital input/outputs voltage
V
0
+5.5
+145
+160
V
IO
Parametric operating junction temperature range (Note 12)
Functional operating junction temperature range (Note 13)
T
−40
−40
°C
°C
jp
T
jf
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
11. A mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time,
the system power dissipation, the system’s environmental conditions, the thermal design of the customer’s system, the modes, in which the
device is operated by the customer, etc. No more than 100 cumulated hours in life time above T .
tw
12.The parametric characteristics of the circuit are not guaranteed outside the Parametric operating junction temperature range.
13.The maximum functional operating temperature range can be limited by thermal shutdown T
.
tsd
PACKAGE THERMAL CHARACTERISTIC
The major thermal resistances of the device are the Rth
from the junction to the ambient (Rthja) and the Rth from the
junction to the exposed pad (Rthjp).
Using an exposed die pad on the bottom surface of the
package is mainly contributing to this performance. In order
to take full advantage of the exposed pad, it is most
important that the PCB has features to conduct heat away
from the package. In the table below, one can find the values
for the Rthja and Rthjp:
The NCV70516 is available in a thermally optimized
SSOP24 and QFN24 5x5 packages. For the optimizations,
the package has an exposed thermal pad which has to be
soldered to the PCB ground plane. The ground plane needs
thermal vias to conduct the heat to the bottom layer.
For precise thermal cooling calculations the major
thermal resistances of the devices are given. The thermal
media to which the power of the devices has to be given are:
• Static environmental air (via the case)
• PCB board copper area (via the device pins and
exposed pad)
Table 5. THERMAL RESISTANCE
Package
SSOP24 NB EP
QFN24 5x5 0.65
Rth, Junction−to−Exposed Pad, Rthjp
Rth, Junction−to−Ambient, Rthja (Note 14)
8.5 K/W
5.9 K/W
33.0 K/W
32.2 K/W
14.The Rthja for 2S2P simulated for worst case power and following conditions:
•
•
•
A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used
Board thickness is 1.46 mm (FR4 PCB material)
2
All four layers: 30 mm thick copper with an area of 2500 mm where:
− top signal layer has a conductivity of 40% = 64.5 W/mK
− bottom signal layer has a conductivity of 90% = 355.5 W/mK
− top plane has a conductivity of 70% = 276.5 W/mK
− bottom plane has a conductivity of 90% = 355.5 W/mK
•
•
•
The 9 vias in Exposed Pad area, via diameter 0.45 mm for SSOP24 NB EP package
The 16 vias in Exposed Pad area, via diameter 0.25 mm for QFN24 5x5 package
Gap*filler max 400 mm between PCB and heat sink non conductive with worst case thermal conductivity of 1.5 W/mK
www.onsemi.com
5
NCV70516
EQUIVALENT SCHEMATICS
The following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified
representations of the circuits used.
DIGITAL
OUT
DIGITAL
IN
DI, CLK,
NXT, DIR
ERRB
Ipd
VDD
Ipu
MOT
OUT
DIGITAL
IN
CSB
MOTXP,
MOTXN,
MOTYN,
MOTYP
VDD
VBB
DIGITAL
OUT
DO
Figure 5. Input and Output Equivalent Diagrams
www.onsemi.com
6
NCV70516
ELECTRICAL CHARACTERISTICS
DC PARAMETERS
The DC parameters are guaranteed over junction temperature from −40 to 145°C and VBB in the operating range from 6
to 29 V, unless otherwise specified. Convention: currents flowing into the circuit are defined as positive.
Table 6. DC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
MOTORDRIVER
I
-
MOTXP
MOTXN
MOTYP
MOTYN
Max current through motor coil in normal
operation
V
= 14 V
800
mA
mA
%
MS
max,Peak
BB
I
-
Max current during booster function
V
V
= 14 V, T = −45°C
1100
MS
boost,Peak
BB
j
I
Absolute error on coil current
= 14 V, T = 145°C
−10
−7
10
7
MSabs
BB
j
I
= 800 mA
MSmax,Peak
and 100 mA
I
Matching of X & Y coil currents
V
= 14 V
%
MSrel
BB
MSmax,Peak
I
= 800 mA
and 100 mA
R
On resistance of High side + Low side
Driver at the highest current range
T = 145°C
j
2.4
W
DS(on)
LOGIC INPUTS
V
CSB
Logic low input level, max
Logic high input level, min
T = 145°C
0.8
V
V
inL
j
V
inH
T = 145°C
j
2.4
I
Input pull up current for logic low level
(Notes 15 and 16)
T = 145°C
j
−50
−25
−10
mA
inL_pu
I
Input leakage current for logic high level
T = 145°C
j
1
mA
inH_pu
V
DI, CLK
Logic low input level, max
Logic high input level, min
T = 145°C
0.8
V
V
inL
j
V
inH
inH_pd
T = 145°C
j
2.4
1
I
Input pull down current for logic high level
(Note 16)
T = 145°C
j
2
3
5
mA
I
Input leakage current for logic low level
T = 145°C
j
−1
mA
V
inL_pd
V
inL
NXT, DIR Logic low input level, max
Logic high input level, min
T = 145°C
j
0.8
5
V
inH
T = 145°C
j
2.4
1
V
I
Input pull down current for logic high level
(Note 16)
T = 145°C
j
mA
inH_pd
I
Input leakage current for logic low level
T = 145°C
j
−1
mA
inL_pd
OPEN DRAIN LOGIC OUTPUT
V
ERRB
Output voltage
8 mA sink current
0.4
5.5
12
V
V
OLmax
OHmax
OLmax
V
Maximum drain voltage
I
Maximum allowed drain current (Note 24)
mA
15.The CSB has a higher pull up current. It is expected that CSB is pulled high anyway in sleep mode, making this pull up current disappear.
16.All Pull−up and pull down currents stay activated during sleep to avoid floating input pins. Placing the pin in wrong state during sleep results
in higher sleep currents in the application.
17.Thermal warning and low temperature level are derived from thermal shutdown (T = T – 20°C, T
= T – 137°C).
tw
tsd
low
tsd
18.No more than 100 cumulated hours in life time above T .
tw
19.Parameter guaranteed by trimming relevant OTPs in production test at 160°C and VBB = 14 V.
20.Dynamic current is with oscillator running, all analogue cells active. Coil currents 0 mA, SPI active, ERRB inactive, no floating inputs.
21.All analog cells in power down. Logic powered, no clocks running. All outputs unloaded, no floating inputs.
22.Pin VDD must not be used for any external supply.
23.The SPI registers content will not be altered above this voltage.
24.Maximum allowed drain current that the output can withstand without getting damaged. Not tested in production.
www.onsemi.com
7
NCV70516
Table 6. DC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
PUSH−PULL LOGIC OUTPUT WHEN CSB = 0 (Figure 5)
V
DO
Output voltage low
8 mA sink current
0.4
V
V
OLmax
V
Output voltage high without pull−up
Maximum pin voltage
4 mA source current
V
DD
− 1.3
OHmin
OHmax
OLmax
V
5.5
12
V
I
Maximum allowed pin current (Note 24)
mA
THERMAL WARNING & SHUTDOWN
T
T
Thermal warning (Notes 17 and 18)
135
155
12
145
165
28
155
175
44
°C
°C
°C
tw
Thermal shutdown (Note 19)
tsd
T
low
Low temperature level (Note17)
SUPPLY AND VOLTAGE REGULATOR
UV
UV
V
BB
H−Bridge off voltage low threshold
Under voltage hysteresis
5.7
6.0
250
4
6.3
600
15
V
100
mV
mA
_HYST
I
Total current consumption (Note 20)
Unloaded outputs
bat
V
= 29 V
BB
I
Sleep mode current consumption (Note 21)
Regulated internal supply (Note 22)
V
= 5.5 V & 18 V
30
60
120
3.6
mA
bat_s
BB
V
V
DD
5.5 V < V < 29 V
Load = 0 mA, 15 mA
3.0
3.3
V
DD
BB
V
Digital supply reset level @ power down
(Note 23)
3.0
80
V
ddReset
I
Current limitation
Pin shorted to ground
mA
ddLim
V
= 14 V
BB
15.The CSB has a higher pull up current. It is expected that CSB is pulled high anyway in sleep mode, making this pull up current disappear.
16.All Pull−up and pull down currents stay activated during sleep to avoid floating input pins. Placing the pin in wrong state during sleep results
in higher sleep currents in the application.
17.Thermal warning and low temperature level are derived from thermal shutdown (T = T – 20°C, T
= T – 137°C).
tw
tsd
low
tsd
18.No more than 100 cumulated hours in life time above T .
tw
19.Parameter guaranteed by trimming relevant OTPs in production test at 160°C and VBB = 14 V.
20.Dynamic current is with oscillator running, all analogue cells active. Coil currents 0 mA, SPI active, ERRB inactive, no floating inputs.
21.All analog cells in power down. Logic powered, no clocks running. All outputs unloaded, no floating inputs.
22.Pin VDD must not be used for any external supply.
23.The SPI registers content will not be altered above this voltage.
24.Maximum allowed drain current that the output can withstand without getting damaged. Not tested in production.
Figure 6. ON Resistance of High Side + Low Side Driver at the Highest Current Range
www.onsemi.com
8
NCV70516
AC PARAMETERS
The AC parameters are guaranteed over junction temperature from −40 to 145°C and VBB in the operating range from 6
to 29 V, unless otherwise specified.
Table 7. AC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
10
Max
Unit
INTERNAL OSCILLATOR
f
Frequency of internal oscillator
V
BB
= 14 V
9
11
MHz
osc
MOTORDRIVER
f
MOTxx
PWM frequency
(Note 25)
28.4
kHz
%
pwm
f
PWM jitter modulation depth
SPI bit PWMJen = 1
(Note 25)
20
jit_depth
t
Open coil detection with
PWM=100% (Note 25)
SPI bit OpenDet[1:0] = 00
SPI bit OpenDet [1:0] = 01
SPI bit OpenDet [1:0] = 10
SPI bit OpenDet [1:0] = 11
5
ms
OCdet
25
50
200
300
t
Turn−on transient time, between
ns
ns
brise
10% and 90%, I
BB
= 200 mA,
MD
V
= 14 V, 1 nF at motor pins
t
Turn−off transient time, between
10% and 90%, I = 200 mA,
300
bfall
MD
V
BB
= 14 V, 1 nF at motor pins
DIGITAL OUTPUTS
t
DO,
ERRB
Output fall−time (90% to 10%)
from V to V
Capacitive load 200 pF
and pull−up 1.5 kW
50
ns
H2L
InH
InL
HARD RESET FUNCTION
t
DIR
Hard reset trigger time (Note 25)
Hard reset DIR pulse width
NXT set−up time
See hard reset function
(Note 25)
20
2.5
2.5
ms
ms
ms
ms
ms
ms
hr_trig
t
hr_dir
hr_set
t
NXT
ERRB
CSB
(Note 25)
t
Hard reset error indication
CSB wake−up low pulse width
Wake−up time
(Note 25)
50
hr_err
t
(Note 25)
2
150
csb_width
t
wu
See Sleep Mode
250
NXT/DIR INPUTS
t
NXT
NXT minimum, high pulse width
NXT minimum, low pulse width
NXT max repetition rate
2
2
ms
ms
NXT_HI
t
NXT_LO
f
f
/2
kHz
ms
NXT
CSB_LO_WIDTH
PWM
t
NXT pin trigger after SPI NXT
command
1
t
NXT,
DIR
NXT set time, following change of
DIR
25
25
ms
ms
DIR_SET
t
NXT hold time, before change of
DIR
DIR_HOLD
25.Derived from the internal oscillator
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
9
NCV70516
Table 8. SPI INTERFACE
Symbol
Parameter
Min
0.5
Typ
Max
Unit
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
t
CSB setup time (Note 26)
CSB hold time
CSS
CSH
t
0.5
t
CSB high time
1
CS
WL
t
CLK low time
0.5
t
CLK high time
0.5
WH
t
DI set up time, valid data before rising edge of CLK
DI hold time, hold data after rising edge of CLK
CSB low to DO valid
0.25
0.275
SU
t
H
t
0.23
0.32
CSDO
t
Output (DO) disable time (Note 27)
Output (DO) valid (Note 27)
0.08
DIS
t
0.32
→
V1
V0
0
1
t
Output (DO) valid (Note 28)
0.32 + t(RC)
→
26.After leaving sleep mode an additional wait time of 250 ms is needed before pulling CSB low.
27.SDO low–side switch activation time.
28.Time depends on the SDO load and pull–up resistor.
tCS
V
IH
CSB
V
IL
tCSH
tCSS
tWH
tWL
V
IH
CLK
V
IL
tSU tH
V
IH
DI
DI13
DI15
DI14
DI1
DI0
V
IL
tDIS
tV
tCSDO
V
IH
DO
HI−Z
HI−Z
DO15
DO14
DO13
DO1
DO0
V
IL
Figure 7. SPI Timing
www.onsemi.com
10
NCV70516
DETAILED OPERATING DESCRIPTION
H−Bridge Drivers with PWM Control
In order to reduce the radiated/conducted emission,
voltage slope control is implemented in the output switches.
A protection against shorts on motor lines is implemented.
When excessive voltage is sensed across a MOSFET for a
time longer than the required transition time, then the
MOSFET is switched−off.
Two H−bridges are integrated to drive a bipolar stepper
motor. Each H−bridge consists of two low−side N−type
MOSFET switches and two high−side P−type MOSFET
switches. One PWM current control loop with on−chip
current sensing is implemented for each H−bridge.
Depending on the desired current range and the micro−step
Motor Enable−Disable
position at hand, the R
of the low−side transistors will
DS(on)
The H−bridges and PWM control can be disabled
(high−impedance state) by means of a bit <MOTEN> in the
SPI control registers. <MOTEN>=0 will only disable the
drivers and will not impact the functions of NXT, DIR, SPI
bus, etc. The H−bridges will resume normal PWM operation
by writing <MOTEN>=1 in the SPI register. PWM current
control is then enabled again and will regulate current in
both coils corresponding with the position given by the
current translator.
be adapted to maintain current−sense accuracy. A
comparator compares continuously the actual winding
current with the requested current and feeds back the
information to generate a PWM signal, which turns on/off
the H−bridge switches. The switching points of the PWM
duty−cycle are synchronized to the on−chip PWM clock.
The PWM frequency will not vary with changes in the
supply voltage. Also variations in motor−speed or load−
conditions of the motor have no effect. There are no external
components required to adjust the PWM frequency. In order
to avoid large currents through the H−bridge switches, it is
guaranteed that the top− and bottom−switches of the same
half−bridge are never conductive simultaneously (interlock
delay).
Automatic Forward and Slow−Fast Decay
The PWM generation is in steady−state using a
combination of forward and slow−decay. For transition to
lower current levels, fast−decay is automatically activated to
allow high−speed response. The selection of fast or slow
decay is completely transparent for the user and no
additional parameters are required for operation.
Icoil
Set value
Actual value
t
0
t
pwm
Forward& Slow Decay
Forward& Slow Decay
Fast Decay & Forward
Figure 8. Forward and Slow/Fast Decay PWM
Automatic Duty Cycle Adaptation
completely automatic and requires no additional parameters
for operation. The state of the duty cycle adaptation mode is
represented in the internal T/B bits for both motor windings
X and Y. Figure 9 gives a representation of the duty cycle
adaptation.
If during regulation the set point current is not reached
before 75% of t , the duty cycle of the PWM is adapted
pwm
automatically to > 50% (top regulation) to maintain the
requested average current in the coils. This process is
www.onsemi.com
11
NCV70516
|Icoil|
Duty Cycle
< 50%
Duty Cycle < 50%
Set value
Duty Cycle > 50%
Actual value
0
t
pwm
Bit T/B
Bottom reg. Bit T/B = 0
Bottom reg. Bit T/B = 0
Top reg. Bit T/B = 1
Figure 9. Automatic Duty Cycle Adaptation
Active Break
When the micro−step resolution is reduced, then the
corresponding least−significant bits of the translator
position are set to “0”. This means that the position in the
current table moves to the right and in the case that
micro−step position of desired new resolution does not
overlap the micro−step position of current resolution, the
closest value up or down in required column is set depending
on the direction of rotation.
When the micro−step resolution is increased, then the
corresponding least−significant bits of the translator
position are added as “0”: the micro−step position moves to
the left on the same row.
In general any change of <SM[2:0]> SPI bits have no
effect on current micro−step position without consequent
occurrence of NXT pulse or <NXTP> SPI command (see
NXT input timing below). When NXT pulse or <NXTP>
SPI command arrives, the motor moves into next micro−step
position according to the current <SM[2:0]> SPI bits value.
Besides the micro−step modes, also full step mode is
implemented. Full step mode activates always only one coil
at a time.
Whenever active break is activated (<ACTBR> bit is set),
both bottom drivers of active H−bridge (based on actual
MSP position) are switched on.
By this mean the position is frozen and current starts
recirculating through the bottom drivers, causing faster
stopping of the motor.
Step Translator
Step Mode
The step translator provides the control of the motor
by means of step mode SPI register SM[2:0], SPI bits DIRP,
NXTP and input pins DIR (direction of rotation) and NXT
(next pulse). It is translating consecutive steps
into corresponding currents in both motor coils for a given
step mode.
One out of five possible stepping modes can be selected
through SPI−bits SM[2:0]. After power−on or hard reset, the
coil−current translator is set to the default to 1/16
micro−stepping at position ‘8*’. When remaining in the
default step mode, subsequent translator positions are all in
the same column and increased or decreased with 1. Table 9
lists the output current versus the translator position.
www.onsemi.com
12
NCV70516
Table 9. TRANSLATOR TABLE
MSP[5:0]
Step mode SM[2:0]
% of Imax
MSP[5:0]
Step mode SM[2:0]
% of Imax
000
1/16
0
001
1/8
0
010
1/4
0
011
1/2
0
100
FS
0
000
1/16
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
001
1/8
16
−
010
1/4
8
011
1/2
4
100
FS
2
MSP[5:0]
00 0000
00 0001
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
00 1000
00 1001
00 1010
00 1011
00 1100
00 1101
00 1110
00 1111
01 0000
01 0001
01 0010
01 0011
01 0100
01 0101
01 0110
01 0111
01 1000
01 1001
01 1010
01 1011
01 1100
01 1101
01 1110
01 1111
Coil Y Coil X MSP[5:0]
Coil Y Coil X
0
100
99,5
98,1
95,7
92,4
88,2
83,1
77,3
70,7
63,4
55,6
47,1
38,3
29
10 0000
10 0001
10 0010
10 0011
10 0100
10 0101
10 0110
10 0111
10 1000
10 1001
10 1010
10 1011
10 1100
10 1101
10 1110
10 1111
11 0000
11 0001
11 0010
11 0011
11 0100
11 0101
11 0110
11 0111
11 1000
11 1001
11 1010
11 1011
11 1100
11 1101
11 1110
11 1111
0
−100
1
−
−
−
−
1
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
9,8
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
−9,8
−99,5
2
1
19,5
29
17
−
−
−19,5 −98,1
−29 −95,7
3
−
−
4
2
38,3
47,1
55,6
63,4
70,7
77,3
83,1
88,2
92,4
95,7
98,1
99,5
100
99,5
18
−
9
−38,3 −92,4
−47,1 −88,2
−55,6 −83,1
−63,4 −77,3
−70,7 −70,7
−77,3 −63,4
−83,1 −55,6
−88,2 −47,1
−92,4 −38,3
5
−
−
−
−
2
−
6
3
19
−
−
7
−
−
8(*)
9
4
20
−
10
−
−
−
−
−
3
−
−
−
−
−
−
−
2
−
−
−
−
−
−
−
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
5
21
−
−
−
−
6
22
−
11
−
−
−
−
−
4
−95,7
−29
7
19,5
9,8
23
−
−
−98,1 −19,5
−
−
−99,5
−100
−99,5
−98,1
−95,7
−92,4
−88,2
−83,1
−77,3
−70,7
−63,4
−55,6
−47,1
−38,3
−29
−9,8
0
8
0
24
−
12
−
−
−
−
−
5
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−9,8
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
9,8
9
98,1 −19,5
95,7 −29
25
−
−
19,5
29
−
−
10
−
92,4 −38,3
88,2 −47,1
83,1 −55,6
77,3 −63,4
70,7 −70,7
63,4 −77,3
55,6 −83,1
47,1 −88,2
38,3 −92,4
26
−
13
−
38,3
47,1
55,6
63,4
70,7
77,3
83,1
88,2
92,4
95,7
98,1
99,5
−
−
−
6
11
−
27
−
−
−
12
−
28
−
14
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
13
−
29
−
−
−
14
−
30
−
15
−
−
−
−
29
19,5 −98,1
9,8 −99,5
−95,7
15
−
31
−
−
−19,5
−9,8
−
*Default position after reset of the translator position.
www.onsemi.com
13
NCV70516
Translator Position
The translator position can be read and set by the SPI
0.8 VCC
register <MSP[5:0]>. This is a 6−bit number equivalent to
CSB
NXT
th
the 1/16 micro−step from Table 9: Translator Table. The
tCSB_LO_WIDTH
translator position is updated immediately following a next
micro−step trigger (see below).
0.2 VCC
NXT
Figure 11. NXT Input Non Overlapping Zone with
the <NXTP> SPI Command
Update
Translator Position
Update
Translator Position
For control by means of I/O’s, the NXT pin operation with
respect to DIR pin should be in a non−overlapped way. See
also the timing diagram below (refer to the AC table for the
timing values). The <SM[2:0]> SPI bits setting, when
changed, is accepted upon the consequent either NXT pin
rising edge or <NXTP> SPI command write only. On the
other hand, the SPI bits <DIRP>, <SM[2:0]> and <NXTP>
can change state at the same time in the same SPI command:
the next micro−step will be applied with the new settings.
Writing to the SPI register <MSP[5:0]> is accepted and
applied to translator table immediately, does not taking
actual step mode into account.
Figure 10. Translator Position Timing Diagram
Direction
The direction of rotation is selected by means of input pin
DIR and its “polarity bit” <DIRP> (SPI register). The
polarity bit <DIRP> allows changing the direction of
rotation by means of only SPI commands instead of the
dedicated input pin.
Direction = DIR−pin EXOR <DIRP>
Positive direction of rotation means counter−clockwise
rotation of electrical vector Ix + Iy. Also when the motor is
disabled (<MOTEN>=0), both the DIR pin and <DIRP>
will have an effect on the positioner. The logic state of the
DIR pin is visible as a flag in SPI status register.
tNXT_HI
tNXT_LO
Next Micro−Step Trigger
0,5 VCC
NXT
DIR
Positive edges on the NXT input − or activation of the
“NXT pushbutton” <NXTP> in the SPI input register − will
move the motor current one step up/down in the translator
table. The <NXTP> bit in SPI is used to move positioner one
(micro−)step by means of only SPI commands. If the bit is
set to “1”, it is reset automatically to “0” after having
advanced the positioner with one micro−step.
tDIR_SET tDIR_HOLD
VALID
Trigger “Next micro−step” = (positive edge on NXT−pin)
OR (<NXTP>=1)
Figure 12. NXT input Timing Diagram
Motor Current
On cold temperatures below T
Parameters) the current can be boosted to higher values by
SPI bit <IBOOST>. After reaching temperature of thermal
• Also when the motor is disabled (<MOTEN>=0),
NXT/DIR functions will move the positioner according
to the logic.
(see Table 6 − DC
low
• In order to be sure that both the NXT pin and the
<NXTP> SPI command are individually attended, the
following non overlapping zone has to be respected.
In this case it is guaranteed that both triggers will have
effect (2 steps are taken).
warning T , current is automatically decreased to
tw
unboosted level. Status of the boost function can be read in
SPI <IBOOST> bit. The motor current settings correspond
to the following current levels:
www.onsemi.com
14
NCV70516
When in normal mode, the device will continuously check
Table 10. IMOT VALUES (4BIT)
upon errors with respect to the expected behavior.
The open load condition is determined by the fact that the
PWM duty cycle keeps 100% value for a time longer than set
by <OpenDet[1:0]> register. This is valid of course only for
the X/Y coil where the current is supposed to circulate,
meaning that in full step positions (MSP[5:0] = {0; 16; 32;
48} (dec)) the open load can be detected only for one of the
coil at a time (respectively {X; Y; X; Y}). The same
reasoning applies for the short circuits detection.
Due to the timeout value set by <OpenDet[1:0]>, the open
coil detection is dependent on the motor speed. In more
detail, there is a maximum speed at which it can be done.
Table 11 specifies these maxima for the different step
modes. For practical reasons, all values are given in full
steps per second.
Register
Value
Peak Motor
Current IMOT (mA)
Peak Boost Motor
Current IMOT (mA)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
59
81
98
71
84
116
138
164
194
231
275
327
389
462
550
655
778
925
1100
100
119
141
168
200
238
283
336
400
476
566
673
800
Table 11. MAXIMUM VELOCITIES FOR OPEN COIL
DETECTION
Step Mode
Speed [FS/s] for given <OpenDet[1:0]>
00
200
300
350
375
387.5
01
40
10
20
11
5
Full Step
1/2
60
30
7.5
8.8
9.4
9.7
Whenever <IMOT[3:0]> is changed, the new coil currents
will be updated immediately at the next PWM period.
In case the motor is disabled (<MOTEN>=0), the logic is
functional and will have effect on NXT/DIR operation (not
on the H−bridges). When the chip is in sleep mode, the logic
is not functional and as a result, the NXT pin and DIR pin
will have no effect.
1/4
70
35
1/8
75
37.5
38.8
1/16
77.5
When Open coil condition is detected, the appropriate bit
(<OPENX> or <OPENY>) together with <ELDEF> bit in
the SPI status register are set. Reaction of the H−bridge to
Open coil condition depends on the settings of <OpenHiZ>
and <OpenDis> bits.
When both <OpenHiZ> and <OpenDis> bits are 0,
<MOTEN> bit stays in 1 and only H−bridge where open coil
is detected is disabled. When <OpenHiZ> bit is set, both
H−bridges are disabled (<MOTEN>=0) in case of Open coil
detection. When <OpenDis> bit is set, drivers remain active
for both coils independently of <OpenHiZ> bit.
Note: The hard−reset function is embedded by means of a
special sequence on the DIR pin and NXT pin, see also
Hard−Reset Function chapter.
Under−voltage Detection
The NCV70516 has one undervoltage threshold level UV
(see Table 6 − DC Parameters).
UV level has its own flag readable via SPI. When supply
voltage VBB drops under undervoltage level, this flag is set
and ERRB pin is pulled down.
Only if the <UV>=0 the motor can be enabled again
by writing <MOTEN>=1 in the control register.
The short circuit detection monitors the load current in
each activated output stage. The current is measured in terms
of voltage drop over the MOSFETS’ R
. If the load
DS(ON)
current exceeds the over−current detection threshold, the
appropriate over−current flag <SHRTij> together with
<ELDEF> bit are set and the drivers are switched off
to protect the integrated circuit. Each driver stage has
an individual detection bit for the N side and the P side.
When short circuit is detected, <MOTEN> is set to 0. The
positioner, the NXT and DIR stay operational. The flag
<ELDEF> (result of OR−ing the latched flags:
<SHRTXPT> OR <SHRTXPB> OR <SHRTXNT> OR
<SHRTYXNB> OR <SHRTYPT> OR <SHRTYPB> OR
<SHRTYNT> OR <SHRTYNB> OR <OPENX> OR
<OPENY>) is reset when the microcontroller reads out the
short circuit or open coil status flags in status registers.
Note: When Next pulse is applied (by means of NXT pin or
<NXTP> bit via SPI) during undervoltage condition, the
step loss bit <SL> is set.
Warning, Error Detection and Diagnostics
Feedback
Open & Short Circuit Diagnostic
The NCV70516 stepper driver features an enhanced
diagnostic detection and feedback, to be read by the external
microcontroller unit (MCU). Among the main items of
interest for the application and typical failures, are open coil
and the short circuit condition, which may be to ground
(chassis), or to supply (battery line).
www.onsemi.com
15
NCV70516
To enable the motor again after reading out of the status
Note (*) reset state: After a power−on or a hard−reset, the
flags, <MOTEN>=1 has to be written.
ERRB is pulled low during t
(Table 7 − AC
hr_err
Parameters).
Notes:
1. Successive reading of the <SHRTij> flags and
re−enabling the motor in case of a short circuit
condition may lead to damage of the drivers.
2. Example: SHRTXPT means: Short at X coil,
Positive output pin, Top transistor.
3. In case of the short from any stepper motor pin
to the top side during switching event from bottom
to top on motor pin, the flag “short to bottom side”
is set instead of the expected “short to top side”
flag.
Note (**) sleep mode: In sleep mode the ERRB is always
inactive (high).
Sleep Mode
The motor driver can be put in a low−power consumption
mode (sleep mode). The sleep mode is entered automatically
after a power−on or hard reset and can also be activated by
means of SPI bit <SLP>. In sleep−mode, all analog circuits
are suspended in low−power. SPI communication stays
active. The motor driver is disabled (even if <MOTEN>=1),
the content of all registers is maintained (including
<MOTEN>, <TSD> and <TW>), logic output pin ERRB is
disabled (ERRB has no function) and none of the input pins
is functional with the exception of pin CSB and SPI pins.
Only CSB pin can wake−up the chip to normal mode (i.e.
clear bit <SLP>) by means of a low pulse with a specified
Step Loss Detection
When Next pulse is applied (by means of NXT pin or
<NXTP> bit via SPI) or <MSP> register is written during
error condition, the step loss bit <SL> is set.
<SL> = (<UV> OR <TSD> OR <ELDEF>) AND ((NXT
OR <NXTP>) OR <MSP> write)
width within t
time. After wake−up, time t (see AC
csb_with
wu
Table) is needed to restore all analog and digital circuits.
Step loss bit <SL> is cleared after read out.
Notes:
Thermal Warning and Shutdown
When junction temperature is above T , the thermal
warning bit <TW> is set (SPI register) and the ERRB pin is
pulled down (*). If junction temperature increases
above thermal shutdown level, then also the <TSD> flag is
set, the ERRB pin is pulled down, the motor is disabled
• The hard−reset function is disabled in sleep mode.
tw
• The thermal shutdown function will be “frozen” during
sleep mode and re−activated at wake−up. This is
important in case that bit <TSD>=1 was cleared already
and <TW> was not “0” yet.
• The CSB low pulse width has to be within t
,
csb_with
(<MOTEN> = 0) and the hardware reset is disabled. If T <
j
(see AC Table) to guarantee a correct wake−up.
T
level and <TSD> bit has been read−out, the status
tw
of <TSD> is cleared and the ERRB pin is released.
Only if the <TSD>=<TW>=0, the motor can be enabled
again by writing <MOTEN>=1 in the control register 1.
During the over temperature condition the hardware reset
Power−on Reset, Hard−Reset Function
After a power−on or a hard−reset, a flag <HR> in the SPI
status register is set and the ERRB is pulled low. The ERRB
stays low during this reset state. The typical power−on reset
will not work until T < T and the <TSD> readout is done.
j
tw
time is given by t
(Table 7 − AC Parameters). After the
hr_err
In this way it is guaranteed that after a <TSD>=1 event,
the die−temperature decreases back to the level of <TW>.
reset state the device enters sleep mode and the ERRB pin
goes high to indicate the motor controller is ready for
operation.
After reaching temperature of thermal warning T , motor
tw
current is automatically decreased to unboosted level.
By means of a specific pattern on the DIR pin and NXT
pin, the complete digital part of driver can be reset without
a power−cycle. This hard−reset function is activated when
the input pin DIR changes logic state “0 → 1 → 0 → 1” in
five consecutive patterns during NXT pin being at high
level. See figure below and Table 7 − AC Parameters.
The operation of all analog circuits is suspended during
the reset state of the digital. Similar as for a normal
power−on, the flag <HR> is set in the SPI register after a
Note (*): During the <TW> situation the motor is not
disabled while the ERRB is pulled down. To be informed
about other error situations it is recommended to poll the
status registers on a regular base (time base driven
by application software in the millisecond domain).
Error Output
This is an open drain output to flag a problem to the
external microcontroller. The signal on this output is active
low and the logic combination of:
hard−reset and the ERRB pin is pulled low during t
(Table 7 − AC Parameters).
hr_err
NOT(ERRB) = (<SPI> OR <ELDEF> OR <TSD> OR
<TW> OR <UV> OR (*)reset state) AND not (**)sleep
mode
www.onsemi.com
16
NCV70516
thr_trig
DIR
NXT
thr_set
thr_dir
thr_err
ERRB
Figure 13. Hard Reset Timing Diagram
SPI INTERFACE
General
A slave or chip select line (CSB) allows individual
selection of a slave SPI device in a time multiplexed
multiple−slave system.
The serial peripheral interface (SPI) is used to allow
an external microcontroller (MCU) to communicate
with the device. NCV70516 acts always as a slave and it
cannot initiate any transmission. The operation of the device
is configured and controlled by means of SPI registers,
which are observable for read and/or write from the master.
The NCV70516 SPI transfer size is 16 bits.
During an SPI transfer, the data is simultaneously
transmitted (shifted out serially) and received (shifted in
serially). A serial clock line (CLK) synchronizes shifting
and sampling of the information on the two serial data lines:
DO and DI. The DO signal is the output from the Slave
(NCV70516), and the DI signal is the output from the
Master.
The CSB line is active low. If an NCV70516 is not
selected, DO is in high impedance state and it does not
interfere with SPI bus activities. Since the NCV70516
always clocks data out on the falling edge and samples data
in on rising edge of clock, the MCU SPI port must be
configured to match this operation.
The implemented SPI allows connection to multiple
slaves by means of star connection (CSB per slave) or by
means of daisy chain.
An SPI star connection requires a bus = (3 + N) total lines,
where N is the number of Slaves used, the SPI frame length
is 16 bits per communication.
NCV70516 dev#1
(SPI Slave)
CSB1
MOSI
MCU
(SPI Master )
NCV70516 dev#1
MISO
SDO1
(SPI Slave)
SDI2
CSB2
MCU
(SPI Master)
NCV70516 dev#2
NCV70516 dev#2
(SPI Slave)
SDO2
(SPI Slave)
CSBN
SDIN
NCV70516 dev#N
NCV70516 dev#N
(SPI Slave)
SDON
(SPI Slave)
Figure 14. SPI Star vs. Daisy Chain Connection
SPI Daisy chain mode
A diagram showing the data transfer between devices in
daisy chain connection is given further: CMDx represents
the 16−bit command frame on the data input line transmitted
by the Master, shifting via the chips’ shift registers through
the daisy chain. The chips interpret the command once the
chip select line rises.
SPI daisy chain connection bus width is always four lines
independently on the number of slaves. However, the SPI
transfer frame length will be a multiple of the base frame
length so N x 16 bits per communication: the data will be
interpreted and read in by the devices at the moment the CSB
rises.
www.onsemi.com
17
NCV70516
• Bits[9:0]: 10 bit DATA to write
Device in the same time replies to the master (on the DO):
• If the previous command was a write and no SPI error
had occurred, a copy of the command, address and data
written fields,
• If the previous command was a read, the response
frame summarizes the address used and an overall
diagnostic check (copy of the main detected errors, see
Figure and Figure for details),
• In case of previous SPI error or after power−on−reset,
only the MSB bit will be 1, followed by zeros.
If parity bit in the frame is wrong, device will not perform
command and <SPI> flag will be set.
The frame protocol for the read operation:
Figure 15. SPI Daisy Chain Data Shift Between
Slaves. The symbol ‘x’ represents the previous
content of the SPI shift register buffer.
Read; CMD = ‘0’
The NCV70516 default power up communication mode
is “star”. In order to enable daisy chain mode, a multiple of
16 bits clock cycles must be sent to the devices, while the
SDI line is left to zero.
High
TW, TSD, ELDEF, UV:
Low
immediate value of STATUS BITS
;
dedicated SPI READ Command of STATUS
Register has to be performed to clear
the value of read −by−clear STATUS bits
C
M
D
A
4
A
3
A
2
A
1
A
0
DI
P
Note: to come back to star mode the NOP register (address
0x0000) must be written with all ones, with the proper data
parity bit and parity framing bit: see SPI protocol for details
about parity and write operation.
Low
Low
S
P
I
E
R
R
E
L
D
E
F
Data from address A [4:0]
shall be returned
T
S
D
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
U
V
T
W
0
DO
HIGH−Z
SPI Transfer Format
Two types of SPI commands (to DI pin of NCV70516)
from the micro controller can be distinguished: “Write to a
control register” and “Read from register (control or
status)”.
CLK
Low
P
=
not(CMD xor A4 xor A3 xor A2 xor A1 xor A0)
Figure 17. SPI Read Frame
The frame protocol for the write operation:
Referring to the previous picture, the read frame coming
from the master (into the DI) is composed from the
following fields:
• Bit[15] (MSB): CMD bit = 0 for read operation,
Write; CMD = ‘1’
High
Low
• Bits[14:10]: 5 bits READ ADDRESS field,
• Bit[10]: frame parity bit. It is ODD parity formed by
the negated XOR of all other bits in the frame,
• Bits [8:0]: 9 bits zeroes field.
Device in the same frame provides to the master (on the DO)
data from the required address (in frame response), thus
achieving the lowest communication latency.
C
M
D
A
3
A
2
A
1
A
0
D D D D D D D D D D
DI
P
9
8 7 6 5 4 3 2 1 0
Low
Previous SPI WRITE command
resp. “SPIERR + 0x000hex”
after POR or SPI Command
S
P
I
E
R
R
C
M
D
A
3
A
2
A
1
A
0
D D D D D D D D D D
DO
9
8
7
6
5
4
3
2
1
0
PARITY/FRAMING Error
HIGH−Z
S
P
I
E
R
R
E
L
D
E
F
Previous SPI READ command
& NCV70516 status bits resp.
“SPIERR + 0x000hex” after
POR or SPI Command
C
M
D
T
S
D
A
4
A
3
A
2
A
1
A
0
U
V
T
W
P
1
1
1
0
PARITY/FRAMING Error
CLK
Low
SPI Framing and Parity Error
SPI communication framing error is detected by the
NCV70516 in the following situations:
P
=
not(CMD xor A3 xor A2 xor A1 xor A0 xor D9 xor D8 xor D7 xor
D6 xor D5 xor D4 xor D3 xor D2 xor D1 xor D0)
• Not an integer multiple of 16 CLK pulses are received
during the active−low CSB signal;
• LSB bits (8..0) of a read command are not all zero;
• SPI parity errors, either on write or read operation.
Figure 16. SPI Write Frame
Referring to the previous picture, the write frame coming
from the master (into the DI) is composed from the
following fields:
Once an SPI error occurs, the <SPI> flag can be reset only
by reading the status register in which it is contained (using
in the read frame the right communication parity bit). This
request will reset the SPI error bit and release the ERRB pin
(high).
• Bit[15] (MSB): CMD bit = 1 for write operation,
• Bits[14:11]: 4 bits WRITE ADDRESS field,
• Bit[10]: frame parity bit. It is ODD parity formed by
the negated XOR of all other bits in the frame,
www.onsemi.com
18
NCV70516
SPI Control Registers (CR)
All SPI control registers have Read/Write access.
Table 12. SPI CONTROL REGISTERS (CR)
5−bit
Default
Address
after Res.
Bit 9
NOP
Bit 8
NOP
Bit 7
NOP
Bit 6
NOP
DIRP
Bit 5
NOP
Bit 4
NOP
Bit 3
NOP
Bit 2
NOP
Bit 1
NOP
Bit 0
NOP
00h
00 0000 0000
00 0000 0000
00 1000 1000
01h (CR1)
02h (CR2)
03h (CR3)
04h (CR4)
NotUsed
NotUsed
NotUsed
NotUsed
NXTP
MOTEN
IBOOST
OpenDis
NotUsed
MSP5
ACTBR
OpenHiZ
NotUsed
MSP4
IMOT3
SLP
IMOT2
SM2
IMOT1
SM1
IMOT0
SM0
PWMJen
NotUsed
NotUsed
OpenDet1 OpenDet0
NotUsed
NotUsed
NotUsed
NotUsed
NotUsed NotUsed NotUsed NotUsed 00 0000 0000
MSP3 MSP2 MSP1 MSP0 00 0000 1000
Table 13. BIT DEFINITION
Symbol
NOP
MAP position
Description
NOP register (read/write operation ignored)
Bits [9:0] – ADDR_0x00
Bit 8 – ADDR_0x01 (CR1)
Bit 7 – ADDR_0x01 (CR1)
Bit 6 – ADDR_0x01 (CR1)
NXTP
MOTEN
DIRP
Push button pin, generating next step in position table
Enables the H−bridges (motor activated)
Polarity of DIR pin, which controls direction status; DIRP = 1 inverts the logic
polarity of the DIR pin)
IBOOST
ACTBR
Bit 5 – ADDR_0x01 (CR1)
Bit 4 – ADDR_0x01 (CR1)
Bits [3:0] – ADDR_0x01 (CR1)
Bit 8 – ADDR_0x02 (CR2)
Bits [7:6] – ADDR_0x02 (CR2)
Bit 5 – ADDR_0x02 (CR2)
Current boost function activation and status
Active break
IMOT[3:0]
PWMJen
OpenDet[1:0]
OpenDis
Current amplitude
Enable PWM jittering function to spread spectrum of PWM modulation
Open Coil detection time setting bits (see Table 7 − AC Parameters)
When bit is set, Open Coil detection status is flagged, but drivers control remain
active for both coils, <OpenDis> bit setting has higher priority than <OpenHiZ> bit
OpenHiZ
Bit 4 – ADDR_0x02 (CR2)
When bit is set, during Open Coil detection both drivers are deactivated
(MOTEN=0)
SLP
Bit 3 – ADDR_0x02 (CR2)
Bits [2:0] – ADDR_0x02 (CR2)
Bit [5:0] – ADDR_0x04 (CR4)
Places device in sleep mode with low current consumption (when 1)
Step mode selection
SM[2:0]
MSP[5:0]
Setting or status of translator micro−step position
www.onsemi.com
19
NCV70516
SPI Status Registers (SR)
All SPI status registers have Read Only Access, with the odd parity on Bit8. Parity bit makes the numbers of 1 in the byte odd.
Table 14. SPI STATUS REGISTERS (SR)
Default
after
Res.
5−bit
Address
Bit 9
Bit 8
PAR
PAR
PAR
Bit 7
SL, L
0x0
Bit 6
SPI,L
0x0
Bit 5
ELDEF, R* TAMB, R
HR,L
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h (SR1) 0x0
06h (SR2) 0x0
07h (SR3) 0x0
08h (SR4) 0x0
TSD,L
TW,R
UV, L
0x0
OPENX,L SHRTXPB,L SHRTXNB,L SHRTXPT,L SHRTXNT,L
0x0
NXTpin, R DIRpin, R OPENY,L SHRTYPB,L SHRTYNB,L SHRTYPT,L SHRTYNT,L
DEVID2 DEVID1 DEVID0 REVID2 REVID1 REVID0
PAR DEVID4 DEVID3
Flags have “,L” for latched information or “,R” for real time information. All latched flags are “cleared upon read”.
X = value after reset is defined during reset phase (diagnostics)
R* = real time read out of values of other latches. Reading out this R* value does not reset the bit, and does not reset the values of the
latches this bit reads out.
Table 15. BIT DEFINITION
Symbol
PAR
SL
MAP Position
Description
Bit 8 – ADDR_0x05 (SR1)
Bit 7 – ADDR_0x05 (SR1)
Bit 6 – ADDR_0x05 (SR1)
Parity bit for SR1
Step loss register
SPI
SPI error: no multiple of 16 rising clock edges between falling and rising
edge of CSB line
ELDEF
Bit 5 – ADDR_0x05 (SR1)
Eletrical defect: Short circuit was detected (at least one of the SHORTij
individual bits is set) or Open Coil X or Y was detected
TAMB
TSD
Bit 4 – ADDR_0x05 (SR1)
Bit 3 – ADDR_0x05 (SR1)
Bit 2 – ADDR_0x05 (SR1)
Bit 1 – ADDR_0x05 (SR1)
Bit 8 – ADDR_0x06 (SR2)
Bit 0 – ADDR_0x05 (SR1)
Bit 4 – ADDR_0x06 (SR2)
Bit 3 – ADDR_0x06 (SR2)
Bit 2 – ADDR_0x06 (SR2)
Bit 1 – ADDR_0x06 (SR2)
Bit 0 – ADDR_0x06 (SR2)
Bit 8 – ADDR_0x07 (SR3)
Bit 6 – ADDR_0x07 (SR3)
Bit 5 – ADDR_0x07 (SR3)
Bit 4 – ADDR_0x07 (SR3)
Bit 3 – ADDR_0x07 (SR3)
Bit 2 – ADDR_0x07 (SR3)
Bit 1 – ADDR_0x07 (SR3)
Bit 0 – ADDR_0x07 (SR3)
Bit 8 – ADDR_0x08 (SR4)
Bits [7:3] – ADDR_0x08 (SR4)
Bits [2:0] – ADDR_0x08 (SR4)
Temperature below T level − Iboost function can be activated
low
Thermal shutdown
TW
Thermal warning
UV
Under voltage detection
PAR
Parity bit for SR2
HR
Hard reset flag: 1 indicates a hard reset has occurred
Open Coil X detected
OPENX
SHRTXPB
SHRTXNB
SHRTXPT
SHRTXNT
PAR
Short circuit detected at XP pin towards ground (Bottom)
Short circuit detected at XN pin towards ground (Bottom)
Short circuit detected at XP pin towards supply (Top)
Short circuit detected at XN pin towards supply (Top)
Parity bit for SR3
NXTpin
DIRpin
Read out of NXT pin logic status
Read out of DIR pin logic status
Open Coil Y detected
OPENY
SHRTYPB
SHRTYNB
SHRTYPT
SHRTYNT
PAR
Short circuit detected at YP pin towards ground (Bottom)
Short circuit detected at YN pin towards ground (Bottom)
Short circuit detected at YP pin towards supply (Top)
Short circuit detected at YN pin towards supply (Top)
Parity bit for SR4
DEVID[4:0]
REVID[2:0]
Device ID
Revision ID
For C516 device the DEVID [4:0] is (16) . For N(V)70516−0 and N70516−1 versions the REVID[2:0] is (1)
.
dec
dec
www.onsemi.com
20
NCV70516
APPLICATION EXAMPLES FOR MULTI−AXIS CONTROL
The wiring diagrams below show possible connections of
Further I/O reduction is accomplished in case the ERRB
is not connected. This would mean that the microcontroller
operates while polling the error flags of the slaves.
Ultimately, one can operate multiple slaves by means of only
4 SPI connections: even the NXT pin can be avoided if the
microcontroller operates the motors by means of the
“NXTP” bit.
multiple slaves to one microcontroller. In these examples,
all movements of the motors are synchronized by means of
a common NXT wire. The direction and Run/Hold
activation is controlled by means of an SPI bus.
Microcontroller
IC1 NCV70516
NXT
CSB
NXT
CSB1
DI/DO/CLK
ERRB
3
DI/DO/CLK
ERRB
3
IC2 NCV70516
NXT
CSB
CSB2
DI/DO/CLK
ERRB
“Multiplexed SPI”
3
IC3 NCV70516
NXT
CSB
CSB3
DI/DO/CLK
ERRB
Rpu
vcc
Figure 18. Examples of Wiring Diagrams for Multi−axis Control
ELECTRO MAGNETIC COMPATIBILITY
The NCV70516 has been developed using
Special care has to be taken into account with long wiring
to motors and inductors. A modern methodology to regulate
the current in inductors and motor windings is based on
controlling the motor voltage by PWM. This low frequency
switching of the battery voltage is present at the wiring
towards the motor or windings. To reduce possible radiated
transmission, it is advised to use twisted pair cable and/or
shielded cable.
state−of−the−art design techniques for EMC. The overall
system performance depends on multiple aspects of the
system (IC design & lay−out, PCB design and layout...) of
which some are not solely under control of the IC
manufacturer. Therefore, meeting system EMC
requirements can only happen in collaboration with all
involved parties.
ORDERING INFORMATION
†
Device
Peak Current
End Market/Version
Package*
Shipping
NCV70516MW0R2G
QFN24 5x5 with wettable flank
5000 / Tape & Reel
(Pb−Free)
Automotive
High Temperature
Version
NCV70516DQ0R2G
SSOP24 NB EP
3000 / Tape & Reel
5000 / Tape & Reel
800/1100 mA
(Note 29)
(Pb−Free)
NCV70516MW1AR2G**
QFNW24 5x5 with step−cut
wettable flank (Pb−Free)
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
** NCV70516MW1AR2G is Dual Fab OPN. Please contact ON Semiconductor for technical details.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
29.The device boost current. This applies for operation under the thermal warning level only.
www.onsemi.com
21
NCV70516
PACKAGE DIMENSIONS
SSOP24 NB EP
CASE 940AK
ISSUE O
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
0.20 C A-B
NOTE 4
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE
FOOT. DIMENSION b APPLIES TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 TO 0.25
FROM THE LEAD TIP.
NOTE 6
D
L1
A
24
13
2X
H
L2
0.20 C
GAUGE
PLANE
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 PER SIDE. DIMENSION D IS
DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE. DIMENSION E1 IS DETERMINED AT DA-
TUM PLANE H.
E1
E
L
A1
NOTE 5
PIN 1
SEATING
PLANE
DETAIL A
C
NOTE 7
REFERENCE
1
12
0.20 C
e
2X 12 TIPS
24X b
B
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
NOTE 6
M
0.12
C A-B D
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
8. CONTOURS OF THE THERMAL PAD ARE UN-
CONTROLLED WITHIN THE REGION DEFINED
BY DIMENSIONS D2 AND E2.
TOP VIEW
DETAIL A
A
A2
h
h
0.10 C
0.10 C
M
MILLIMETERS
DIM MIN
MAX
1.70
0.10
1.65
0.30
0.20
c
A
A1
A2
b
---
0.00
1.10
0.19
0.09
A1
SEATING
PLANE
END VIEW
24X
C
SIDE VIEW
c
M
0.15
C A-B D
D
8.64 BSC
NOTE 8
D2
E
5.28
5.58
D2
6.00 BSC
3.90 BSC
2.44 2.64
0.65 BSC
0.25 0.50
0.40 0.85
1.00 REF
0.25 BSC
E1
E2
e
M
0.15
C A-B
D
h
L
E2
L1
L2
M
NOTE 8
0
8
_
_
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT
5.63
24X
1.15
2.84
6.40
1
24X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
www.onsemi.com
22
NCV70516
PACKAGE DIMENSIONS
QFN24 5x5, 0.65P
CASE 485CS
ISSUE O
NOTES:
L
L
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A B
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
MILLIMETERS
DIM MIN
MAX
0.90
0.05
2X
0.15
0.15
C
A
A1
A3
b
0.80
−−−
0.20 REF
0.25
EXPOSED Cu
2X
C
MOLD CMPD
TOP VIEW
0.35
3.60
3.60
D
5.00 BSC
A
D2 3.40
DETAIL B
E
5.00 BSC
(A3)
A1
0.10
C
C
E2 3.40
e
K
L
0.65 BSC
0.20 MIN
0.30
A3
A1
DETAIL B
0.08
0.50
0.15
ALTERNATE
CONSTRUCTION
L1
−−−
SEATING
PLANE
NOTE 4
C
SIDE VIEW
D2
M
0.10
C A B
SOLDERING FOOTPRINT*
DETAIL A
K
13
7
5.30
M
0.10
C A B
24X
0.62
3.66
E2
1
24
3.66
24X
5.30
b
0.10
24X
L
e
M
C A B
e/2
M
NOTE 3
0.05
C
BOTTOM VIEW
24X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
23
NCV70516
PACKAGE DIMENSIONS
QFNW24 5x5, 0.65P
CASE 484AF
ISSUE O
D
A
B
NOTES:
L3
L3
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
LOCATION
L
L
ALTERNATE
CONSTRUCTION
E
DETAIL A
MILLIMETERS
DIM MIN
NOM
0.85
−−−
0.20 REF
0.10 REF
0.30
5.00
3.50
5.00
3.50
MAX
0.90
0.05
A
A1
A3
A4
b
D
D2
E
0.80
−−−
EXPOSED
COPPER
TOP VIEW
A4
A1
DETAIL B
0.25
4.90
3.40
4.90
3.40
0.35
5.10
3.60
5.10
3.60
0.10
0.08
C
PLATING
A1
A4
C
C
ALTERNATE
A
CONSTRUCTION
DETAIL B
E2
e
C
A3
0.65 BSC
0.35 REF
0.40
SEATING
PLANE
A1
C
K
L
NOTE 4
SIDE VIEW
0.30
0.50
L3
0.05 REF
M
0.10
C A B
A4
D2
DETAIL A
24X
L
RECOMMENDED
7
L3
SOLDERING FOOTPRINT
M
PLATED
0.10
C A B
SURFACES
13
5.30
3.66
SECTION C−C
24X
0.62
E2
K
1
1
24
e
e/2
19
24X b
M
0.10
C A B
3.66
5.30
M
0.05
C
NOTE 3
BOTTOM VIEW
24X
0.65
PITCH
0.40
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
◊
NCV70516/D
相关型号：
©2020 ICPDF网 联系我们和版权申明