NCV68261MTWAITBG [ONSEMI]
Ideal Diode and High Side Switch NMOS Controller;
| 型号： | NCV68261MTWAITBG |
| 厂家： | 
ONSEMI |
| 描述： | Ideal Diode and High Side Switch NMOS Controller |
| 文件： | 总17页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Ideal Diode and High Side
Switch NMOS Controller
WDFNW6
CASE 511DW
NCV68261
The NCV68261 is a Reverse Polarity Protection and Ideal Diode
NMOS Controller with optional High Side Switch function, intended
as a lower loss and lower forward voltage replacement for power
rectifier diodes and mechanical power switches. The controller
operates in conjunction with one or two N−channel MOSFETs and
sets the ON/OFF state of the transistors based on the state of the
Enable pin and the Input−to−Drain differential voltage polarity.
Depending on the Drain pin connection, both Ideal Diode and High
Side Switch applications can operate in two different modes. With the
Drain pin connected to the load, the applications are in Ideal Diode
mode, whereas with the Drain pin connected to ground, the
applications are merely in Reverse Polarity Protection mode.
PIN ASSIGNMENT
1
2
6
5
IN
S
GND
G
4 EN
3
D
WDFNW6
(Top View)
MARKING DIAGRAMS
Features
V6MG
• Operating Voltage Range: up to 32 V
• Immune to 60 V Load Dump Pulse
• Immune to −40 V Negative Transient
• Overvoltage Protection
G
V6 = Specific Device Code
M
G
= Month Code
= Pb−Free Package
♦ Disconnects the load from battery at V = 35.6 V typ
IN
(Note: Microdot may be in either location)
• Enable Function (3.3 V Logic Compatible Thresholds)
• Ideal Diode Function
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of
this data sheet.
♦ Protecting against Reverse Current Flow (from Output to Input)
• Reverse Polarity Protection (RPP) Function
♦ Protecting against Negative Supply
Typical Applications
• High Side Switch with Ideal Diode
• Automotive Battery Regulation
• High Side Switch with Reverse Polarity Protection
• Industrial Power Supply
• Rectifier
• NCV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Grade 1 Qualified and
PPAP Capable
• High Side Switch
• Vehicle Control Module
• These Devices are Pb−Free and are RoHS Compliant
Battery
Protected Battery
Battery
Protected Battery
G
G
S
D
S
D
+
+
CIN
CIN
Cbulk
Cbulk
IN
NCV68261
NCV68261
IN
EN
EN
GND
GND
Figure 1. NCV68261 Application Schematic
(Ideal Diode)
Figure 2. NCV68261 Application Schematic
(Ideal Diode + High Side Switch)
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
May, 2022 − Rev. 1
NCV68261/D
NCV68261
Battery
Protected Battery
Battery
Protected Battery
G
G
S
D
S
D
+
+
CIN
CIN
Cbulk
Cbulk
IN
NCV68261
NCV68261
IN
EN
EN
GND
GND
Figure 3. NCV68261 Application Schematic
(Reverse Polarity Protection)
Figure 4. NCV68261 Application Schematic
(Reverse Polarity Protection + High Side Switch)
S
G
1 MW
Pull-down
Bulk
Discharge
Switch
IN
D
Prereg.
Logic
References
Input/
Enable
EN
Drain
+
&
CP_OUT-
1
DISCH
CP_EN
-
DISCH_OUT
OSC+CP
UVLO
+
CP_OUT+
-
OVLO
+
-
GND
Figure 5. NCV68261 Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
WDFNW6
Pin Name
Description
6
IN
Supply voltage input, Anode of the diode and Non−inverting input of the internal comparator. Bypass directly
to GND with a ceramic capacitor. Connect to the Drain of the High Side Switch NMOS or to the Source pin
(see the application schematics).
5
4
3
GND
EN
D
Ground potential.
Enable Input. High Level enables the chip. Connect to IN if enable function is not required.
Cathode of the diode and Inverting input of the internal comparator. Bypass directly to GND with a ceramic
capacitor. Connect to the Drain of the Diode NMOS or to the GND (see the application schematics).
2
1
G
S
Charge pump output with discharge function. Connect to the Gate of the external NMOS (see application
schematics).
Reference for the Charge pump output. Connect to the Source of the external NMOS (see application
schematics).
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NCV68261
Table 2. MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
V
Input and Source Voltage DC (Note 1)
V
S
−18
45
Input, Source, Drain, Gate and Enable Voltage (Note 2)
Load Dump − Suppressed
U
V
s*
−
60
Input, Source, Gate and Enable Voltage (Note 3)
Test Pulse 1
U
V
s
−40
−18
−0.3
−5
−
45
19
45
45
−
Gate Voltage
V
G
V
V
Gate−to−Source Voltage
V
GS
Drain Voltage
V
D
V
Input and Source−to−Drain Voltage DC
Input and Source−to−Drain Voltage transient (Test Pulse 1)
Enable Voltage
V
SD
V
SD
V
EN
−45
−60
−18
−40
−55
V
V
45
150
150
V
Operating Junction Temperature
Storage Temperature
T
J
°C
°C
T
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. Load Dump Test B (with centralized load dump suppression) according to ISO 16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class A according to ISO 16750−1.
3. Test Pulse 1 according to ISO 7637−2 standard. Guaranteed by design. Not tested in production. Passed Class A according to ISO 16750−1.
More ISO 7637−2: 2011(E) PULSE TEST RESULTS are in Table 8.
Table 3. ESD CAPABILITY (Note 4)
Rating
ESD Capability, Human Body Model
ESD Capability, Charged Device Model
Symbol
Min
−2
Max
2
Unit
kV
ESD
ESD
HBM
CDM
−1
1
kV
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2017)
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes smaller than
2 × 2 mm due to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current
waveform characteristic defined in JEDEC JS−002−2018.
Table 4. LEAD SOLDERING TEMPERATURE AND MSL (Note 5)
Rating
Symbol
Min
Max
Unit
Moisture Sensitivity Level
MSL
1
−
5. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 5. THERMAL CHARACTERISTICS (Note 6)
Rating
Symbol
Value
Unit
Thermal Characteristics, WDFNW−6
Thermal Resistance, Junction−to−Ambient
Thermal Reference, Junction−to−Case Top
°C/W
R
Ψ
157.8
37.4
q
JA
JT
q
6. Mounted onto a 80 x 80 x 1.6 mm single layer FR4 board (645 sq mm, 1 oz. Cu, steady state).
Table 6. RECOMMENDED OPERATING RANGES
Rating
Symbol
Min
3
Max
32
Unit
V
Input Voltage
V
IN
Junction Temperature
T
J
−40
150
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCV68261
Table 7. ELECTRICAL CHARACTERISTICS
V
= 13.5 V, V = 5 V, C = 0.1 mF, C
= 1 mF, Min and Max values are valid for temperature range −40°C ≤ T ≤ +150°C unless
IN
EN
IN
b
u
l
k
J
noted otherwise and are guaranteed by test, design or statistical correlation. Typical values are referenced to T = 25°C
J
Parameter
CHARGE PUMP OPERATION
Undervoltage Lockout
Test Conditions
Symbol
Min
Typ
Max
Unit
V
V
rising
V
−
3
3.4
3.25
3.65
−
V
V
IN
IN
IN_UVLO
falling (Gate Discharge)
Overvoltage Lockout
V
IN
rising
V
32
−
35.6
0.8
42
−
IN_OVLO
Hysteresis (V falling)
IN
Gate−to−Source Charged Voltage
V
IN
V
IN
= 4 V
≥ 8 V
V
GS
3
9
4
11.3
−
15
V
Input−to−Drain Voltage Threshold
Gate Charge
Gate Discharge
V
mV
th(IN−D)
V
IN−D
V
IN−D
rising
falling
100
−40
140
−10
220
0
Gate Charge Current
V
= 0 V, V
= 220 mV
I
mA
GS
V
V
IN−D
G_Charge
= 4 V
70
170
100
320
−
−
IN
IN
= 13.5 V
Gate Discharge Peak Current
V
V
= 10 V, V
≤ −100 mV
I
G_Disch
−
1.65
2.4
−
A
W
GS
GS
IN−D
Discharge Switch R
= 100 mV, V
≤ −100 mV
R
1
5
DS(ON)
IN−D
DS(on)
rt_OFF
Response Time (Time from Reverse
V
V
= 10 V, V = 13.5 V,
t
ms
GS
IN−D
IN
Voltage Condition to V = 9 V)
= step from 250 mV to −150 mV
−
−
0.2
1.1
0.6
GS
Gate−to−Source Static Resistance
−
MW
DISABLE AND QUIESCENT CURRENTS
Disable Current
V
= 0 V
I
−
−
−
5
mA
mA
EN
DIS
Quiescent Current
I
= 0 mA, V
= 220 mV
I
q
210
295
GS
IN−D
(CP active)
ENABLE
Enable Input Threshold Voltage
Logic Low
Logic High
V
th(EN)
V
V
GS
V
GS
≤ 0.1 V
≥ 4.9 V
0.99
−
1.7
1.8
−
2.31
Enable Input Current
Logic High
mA
V
EN
V
EN
V
EN
= 13.5 V
= 5 V
= 0 V
I
I
−
−
−
11
3.2
0.010
−
5
1
EN_ON
EN_ON
Logic High
Logic Low
I
EN_OFF
Response Time (Time from EN High−
V
GS
V
EN
= 10 V, V = 13.5 V,
t
rt_EN_OFF
ms
IN
to−Low to V = 9 V)
= step from 5 V to 0 V
−
0.9
4
GS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCV68261
TYPICAL CHARACTERISTICS
12.5
11.5
10.5
9.5
400
T = −40°C
J
T = 150°C
T = 25°C
J
J
350
300
250
200
150
100
50
T = −40°C T = 25°C
T = 125°C
J
J
J
T = 125°C
J
8.5
7.5
T = 150°C
J
6.5
5.5
4.5
3.5
2.5
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
, INPUT VOLTAGE (V)
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
, INPUT VOLTAGE (V)
V
IN
V
IN
Figure 6. Gate−to−Source Charged Voltage vs.
Figure 7. Gate Charge Current vs. Input
Voltage
Input Voltage
0.4
0.35
0.3
4.0
3.5
3.0
2.5
2.0
V
IN
= 4 V
V
0.25
0.2
V
IN
= 8 V to 32 V
= 8 V to 32 V
IN
0.15
0.1
1.5
1.0
V
V
= −100 mV
= 100 mV
IN−D
0.05
GS
0
−50 −30 −10 10 30 50 70 90 110 130 150
−50 −30 −10 10 30 50 70 90 110 130 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 8. Discharge Switch On Resistance vs.
Temperature
Figure 9. Charge Pump Output Response Time in
Reverse Condition (from VIN−D = 0 V to VGS = 9 V)
vs. Temperature
200
180
160
140
120
100
80
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T = 25°C
J
V
IN
= 13.5 V
V
IN−D
rising
V
IN
= 13.5 V
V
IN
= 32 V
60
40
V
= 4 V
IN
20
0
V
IN−D
falling
−20
−40
0
20
40
60
80
100
−50 −30 −10 10 30 50 70 90 110 130 150
C
, GATE−SOURCE CAPACITANCE (nF)
T , JUNCTION TEMPERATURE (°C)
J
GS
Figure 10. Discharge Time (from VIN−D = 0 V to
GS = 0 V) vs. Gate−Source Capacitance
Figure 11. Input−to−Drain Voltage Thresholds
V
vs. Temperature
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NCV68261
TYPICAL CHARACTERISTICS
300
280
260
240
220
200
180
160
140
300
V
IN
= 13.5 V
T = 25°C
J
280
260
240
220
200
180
160
140
Charge pump ON
Charge pump ON
Charge pump OFF
Charge pump OFF
120
100
120
100
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
, INPUT VOLTAGE (V)
−50 −30 −10 10 30 50 70 90 110 130 150
V
IN
T , JUNCTION TEMPERATURE (°C)
J
Figure 12. Quiescent Current vs. Input Voltage
Figure 13. Quiescent Current vs. Temperature
0.35
0.3
V
= 13.5 V
IN
2.2
2.0
1.8
1.6
1.4
1.2
1.0
V
IN
= 32 V
0.25
0.2
Logic high
Logic low
0.15
0.1
V
= 13.5 V
IN
V
IN
= 4 V
0.05
0
−50 −30 −10 10 30 50 70 90 110 130 150
−50 −30 −10 10 30 50 70 90 110 130 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 14. Disable Current vs. Temperature
Figure 15. Enable Voltage Thresholds vs.
Temperature
35
30
25
20
15
10
5
1
0.95
0.9
V
IN
= 8 V to 32 V
T = 150°C
J
T = 125°C
J
0.85
0.8
T = 25°C
J
T = −40°C
J
0.75
0
0.7
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
, ENABLE VOLTAGE (V)
−50 −30 −10 10 30 50 70 90 110 130 150
V
EN
T , JUNCTION TEMPERATURE (°C)
J
Figure 16. Enable Input Current vs. Enable
Voltage
Figure 17. Enable Response Time (from EN
High−to−Low to VGS = 9 V) vs. Temperature
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NCV68261
TYPICAL CHARACTERISTICS
36
35.5
35
3.5
3.4
V
IN
rising
V
IN
rising
V
IN
falling
3.3
3.2
V
IN
falling
34.5
−50 −30 −10 10 30 50 70 90 110 130 150
−50 −30 −10 10 30 50 70 90 110 130 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 18. Undervoltage Lockout (UVLO)
Thresholds vs. Temperature
Figure 19. Overvoltage Lockout (OVLO)
Thresholds vs. Temperature
50
45
40
35
30
25
20
15
10
5
25
20
T = 25°C
EN
T = 25°C
J
EN
J
V
= 5 V
V
= 0 V
V
D
= V − 220 mV
IN
Charge pump OFF
15
10
5
Charge pump ON
0
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
, INPUT VOLTAGE (V)
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
, INPUT VOLTAGE (V)
V
IN
V
IN
Figure 20. Drain Input Current vs. Input
Voltage
Figure 21. Drain Input Current vs. Input
Voltage
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NCV68261
TYPICAL CHARACTERISTICS
Table 8. ISO 7637−2: 2011(E) PULSE TEST RESULTS
Test Severity Levels, 12 V System
ISO 7637−2:2011(E)
Delays and Im-
pedance
# of Pulses or
Test Time
Pulse / Burst
Rep. Time
Test Pulse
I / II
−75
+37
−112
+75
III
IV
1
−112
+55
−150
+112
−220
+150
2 ms, 10 W
0.05 ms, 2 W
0.1 ms, 50 W
0.1 ms, 50 W
500 pulses
500 pulses
1 h
0.5 s
0.5 s
2a
3a
3b
−165
+112
100 ms
100 ms
1 h
Test Results
ISO 7637−2:2011(E)
Test Pulse
I / II
III
E
A
E
A
IV
E
1
A
2a
3a
3b
A
E
Class
Functional Status
All functions of a device perform as designed during and after exposure to disturbance.
A
B
All functions of a device perform as designed during exposure. However,one or more of them can go beyond speci-
fied tolerance. All functions return automatically to within normal limits after exposure is removed. Memory functions
shall remain class A.
C
D
E
One or more functions of a device do not perform as designed during exposure but return automatically to normal
operation after exposure is removed.
One or more functions of a device do not perform as designed during exposure and do not return to normal opera-
tion until exposure is removed and the device is reset by simple ”operator/use” action.
One or more functions of a device do not perform as designed during and after exposure and cannot be returned to
proper operation without replacing the device.
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NCV68261
APPLICATION INFORMATION
INTEGRATED CIRCUIT AND BLOCK DIAGRAM
UVLO Comparator
DESCRIPTION
The undervoltage lockout (UVLO) comparator compares
the Input voltage level with an internal reference voltage
level. When the Input voltage falls below the UVLO
threshold, the output of the UVLO comparator is set to low
resulting in turning OFF the charge pump and switching
OFF the external NMOS transistors.
Integrated Circuit Description
The NCV68261 can operate in conjunction with one or
two external NMOS transistors. Two basic applications can
be configured: an Ideal diode application or a Reverse
Polarity Protection application defined by the Drain pin
connection as shown in the Table 9. The applications with
single NMOS are always forward conductive. The
applications with two NMOS transistors provide a High
Side Switch function to control the power supplied to the
application.
OVLO Comparator
The overvoltage lockout (OVLO) comparator compares
the Input voltage level with an internal reference voltage
level. When the Input voltage rises above the OVLO
threshold, the output of the OVLO comparator is set to high
resulting in turning OFF the charge pump and switching
OFF the external NMOS transistors.
Enable
The Enable block turns the controller ON and OFF. If the
Enable function is not needed, then the Enable pin can be
connected to the Input pin for permanent operation.
Logic
The Logic block controls the Charge Pump block
according to the inputs from the Input/Drain, UVLO and
OVLO comparators. The truth table of the logic function is
shown in Table 10.
References
The References block provides voltage references and
voltage supply for other internal circuitry. This block is
supplied from the Input and controlled by the Enable block.
Pre−regulator
The pre−regulator provides a stable voltage supply for the
Charge Pump block.
Input/Drain Comparator
This comparator compares voltage levels at the Input and
Drain pins. Based on the Drain pin connection, the
applications can be designed with both Reverse Current
Protection and Reverse Polarity Protection features active
(Figures 22 and 23) or with Reverse Polarity Protection
only (Figures 24 and 25).
Oscillator and Charge Pump
The oscillator generates an approximately 2 MHz clock
signal that drives the charge pump. The charge pump
generates the Gate−Source voltage from the voltage
provided by the pre−regulator. The OSC+CP block drives
the discharge switch as well.
Table 9. AVAILABLE PROTECTION FEATURES
Protection Features
Drain Pin Connection
Load Side (Protected Battery) (see Figures 22 and 23)
GND (see Figures 24 and 25)
Reverse Current Protection
Reverse Polarity Protection
Yes
No
Yes
Yes
Table 10. TRUTH TABLE OF THE LOGIC BLOCK (@ EN = HIGH)
Input/Drain Comparator
UVLO Comparator
OVLO Comparator
Disch
TRUE
TRUE
TRUE
TRUE
FALSE
TRUE
CP_EN
NMOS
OFF
OFF
OFF
OFF
ON
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
< V
< V
< V
> V
> V
> V
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
< V
> V
> V
< V
> V
> V
X
FALSE
FALSE
FALSE
FALSE
TRUE
D
D
D
D
D
D
IN_UVLO
IN_UVLO
IN_UVLO
IN_UVLO
IN_UVLO
IN_UVLO
V
V
< V
IN
IN_OVLO
IN_OVLO
> V
IN
X
V
V
< V
IN
IN_OVLO
IN_OVLO
> V
FALSE
OFF
IN
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NCV68261
Operation
the charge pump and the NMOS transistor are disabled. As
the Input voltage becomes greater than the Drain voltage,
forward current flows through the body diode of the NMOS
transistor. Once this forward voltage drop exceeds the
Input−to−Drain Gate Charge Voltage Threshold level (typ.
140 mV), the charge pump is turned ON and the NMOS
transistor becomes fully conductive.
Reverse Current Blocking: When the Input voltage
becomes less than the Drain voltage, a reverse current
initially flows through the conductive channel of the NMOS
transistor. This current creates a voltage drop across the
conductive channel of the NMOS transistor which is
The main function of the NCV68261 is to control the
ON/OFF state of one or two external NMOS transistors
depending on the state of the Enable pin and the difference
between the voltages at the Input and Drain pins − as shown
in Figures 22 to 25. Figure 5 illustrates the internal
connections between the functional blocks described above.
OFF state: When the Enable input is low, the IC is in
disable mode. All the internal blocks are turned OFF, and the
current consumption is reduced − typically down to tens of
nano−amps. In this state, the external transistors are kept
OFF by an integrated 1 MW resistor between the Gate and
Source pins.
proportional to its R
resistance. When this voltage
DS(ON)
ON state: When the Enable input is high, the IC is active.
Further operation depends on the output state of the UVLO,
OVLO and Input/Drain comparators. Table 10 shows the
charge pump, gate discharge, and NMOS transistor states
based on the output states of these comparators. The charge
pump is turned ON only when the Input voltage level is
between the UVLO and OVLO thresholds and above the
Drain voltage level.
Undervoltage Lockout: When the Input voltage falls
below the UVLO thresholds (typ. 3.25 V), the charge pump
is disabled and the external NMOS transistors are turned
OFF by an internal PMOS transistor. By decreasing the
Input voltage further, the chip is insufficiently powered, and
the external NMOSs are kept in OFF state by the integrated
1 MW resistor (see Figure 5).
crosses below the Input−to−Drain Gate Discharge Voltage
Threshold (typ. −10 mV), the charge pump is disabled and
the external NMOS transistor is turned OFF by an internal
PMOS transistor (see Figure 5).
Reverse Polarity Protection (RPP)
By connecting the Drain pin to the GND potential
(Figure 24), the NCV68261 does not allow a falling input
voltage to discharge the output below GND potential, but it
does allow the output to follow any positive input voltage
between the UVLO and OVLO thresholds. When the Input
voltage is between the UVLO (typ. 3.4 V) and OVLO (typ.
34.8 V) thresholds, the Input/Drain, UVLO and OVLO
comparators enable the charge pump to provide
Gate−Source voltage to the external NMOS transistor,
which is fully conductive. For Input voltage below the
UVLO (typ. 3.25 V) or above the OVLO (typ. 35.6 V)
thresholds, the charge pump and the NMOS transistor are
disabled, and any load current flows through the body diode
of the NMOS transistor.
Overvoltage Lockout: When the Input voltage rises
above the OVLO thresholds (typ. 35.6 V), the charge pump
is disabled and the external NMOS transistors are turned
OFF by an internal PMOS transistor.
APPLICATION CONFIGURATIONS
High Side Switch (HSS)
Ideal Diode
The applications with two NMOS transistors provide
High Side Switch function to control the power supply of the
application. The first transistor operates as a switch, while
the second operates as an Ideal Diode and/or Reverse
polarity protection.
In the Ideal Diode configuration (Figure 22), the input
voltage is not allowed to discharge the output.
Conduction Mode: Prior to entering the conduction
mode, the Input voltage is lower than the Drain voltage, and
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10
NCV68261
The Ideal Diode application in Figure 22 has rectifying
low, the application behaves as an Ideal Switch and the
protected battery line is disconnected from the battery line.
The Reverse Polarity Protection (RPP) application in
Figure 24 protects the load from negative voltages at the
battery line.
properties as a common diode application, while reducing
the forward voltage drop on the diode. Th application is in
reverse mode as long as the Input voltage is lower than the
Drain voltage.
The Ideal Diode + High Side Switch (HSS) application
in Figure 23 combines the features of the Ideal Diode and an
Ideal Switch depending on the Enable (EN) state. If the EN
is high the application is in Ideal Diode mode. If the EN is
The Reverse Polarity Protection + High Side Switch
application in Figure 25 combines the features of the RPP
and HSS, similarly to the Ideal Diode + HSS.
Battery
Protected Battery
Battery
Protected Battery
G
S
D
+
G
NCV68261
GND
Cbulk
S
D
CIN
+
IN
CIN
NCV68261
Cbulk
IN
EN
GND
EN
Figure 22. Ideal Diode
Figure 23. Ideal Diode + High Side Switch
Battery
Protected Battery
Battery
Protected Battery
G
S
D
+
G
S
D
CIN
Cbulk
+
IN
CIN
NCV68261
Cbulk
NCV68261
IN
EN
GND
EN
GND
Figure 24. Reverse Polarity Protection
Figure 25. Reverse Polarity Protection + High Side Switch
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11
NCV68261
Figure 26. Application Response to 13 V + 6 Vpp Sine Wave on the Input (VIN) – Ideal Diode + High Side Switch
Application (see Figure 23)
Figure 27. Application Response to 11 V to 0 V Transient on the Input (VIN) − Ideal Diode + High Side Switch
Application (see Figure 23)
Figure 28. Application response to 11 V to −18 V transient on the Input (VIN) – Reverse Polarity Protection + High
Side Switch Application (see Figure 25)
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12
NCV68261
CIN Capacitor Considerations
n
– the number of external transistors used in the
application (n = 1 for Ideal Diode or RPP
applications, n = 2 for Ideal Diode +HSS or
RPP +HSS)
– ON resistance of the external NMOS
transistor
For proper device performance, it is recommended that a
0.1 mF ceramic capacitor be placed as close as possible to the
NCV68261 and connected with the shortest possible traces.
If the device is used in High Side Switch configuration, the
R
DS(ON)
C
IN
capacitor should be large enough to cover the inrush
currents flowing into the application during the startup
event.
t
– the expected duration of the battery voltage
drop
drop
DU
– the maximum allowed drop of the output
voltage
out
Cbulk (Output) Capacitor Considerations
Besides presenting a sufficiently low impedance for the
load input rail, in an Ideal Diode application the C
NMOS Transistor Considerations
bulk
capacitance should be high enough to maintain adequate
voltage while providing load current for the duration of
battery sag plus the charge from reverse current spike before
the NMOS transistor turns off. Capacitor ESR is also limited
In general, any NMOS can be connected to the
NCV68261. There are no special requirements for the
transistor. From the NCV68261 perspective, the Gate to
Source maximum voltage of the transistor should be rated
above a 15 V level (see Table 7 with electrical
characteristics) unless an external voltage protection is
applied to protect the Gate−Source structure from a
breakdown.
by the R
of the NMOS, as high ESR can reduce
DS(ON)
reverse current flow below that needed to create sufficient
NMOS reverse voltage drop (see Figure 26). The value of
the C
capacitor can be calculated according to the
bulk
Equation 1:
EMC and Dynamic Performance Considerations
To improve the EMC immunity to Direct Power Injection,
it is recommended to use the application example and PCB
layout shown in Figures 29 and 30. The recommended
application contains additional capacitor connected to the
Gate and GND pins respectively. The recommended
component values are listed in the Table 11.
DUin
n@RDS(ON)
tDisch
@
) Iload @ tdrop
(eq. 1)
Cbulk
+
DUout
where:
t
– discharge time for the given Gate−Source
capacity of the external NMOS
(see Figure 10)
Disch
The C capacitance limits inrush current as well. The
G
typical measurements are shown in Figures 31 to 33. The
DU
– expected battery voltage drop
R
G_Q1
and R mitigate potential oscillations of the output
in
S
voltage during start up.
Q1
Q2
Protected Battery
Battery
RG_Q1
CG
RS
10 W
CIN
Cbulk
10 W
1 nF
10 mF
10 mF
G
S
D
IN
NCV68261
EN
GND
Figure 29. Application Example for Optimized
EMC Performance and Inrush Current Control
Figure 30. PCB Layout Example
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13
NCV68261
Table 11. RECOMMENDED COMPONENTS FOR OPTIMAL EMC PERFORMANCE (Note 7)
C
(mF)
C
(mF)
C
(nF)
R
(W)
R
(W)
G_Q1
IN
bulk
G
S
0.1
1
0.1
4.7
10
10
10
10
10
1
10
10
10
4.7
7. Global pins: up to 33 dBm
Local pins: up to 17 dBm
Table 12. RECOMMENDED EXTERNAL COMPONENT PART NUMBERS
Component
Value/Rating
1 nF/100 V
4.7 nF/100 V
100 nF/100 V
1 mF/50 V
Part Number
C
C
GCM1885C2A102JA16
GCM188R72A472KA37
GRM188R72A104KA64
G
G
C
IN
C
GCM21BR71H105KA03
GCM32ER71H475KA55
GCM32EC71H106KA03
MC0063W0603110R
bulk
C
4.7 mF/50 V
10 mF/50 V
10 W
IN
C
, C
bulk
IN
R , R
S
G_Q1
Figure 31. Startup with EN − No Inrush Current Reduction
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14
NCV68261
Figure 32. Startup with EN − CG = 1 nF Inrush Current Reduction
Figure 33. Startup with EN − CG = 4.7 nF Inrush Current Reduction
Thermal Considerations
PCB Layout Considerations
The NCV68261 has no thermal protection function as it is
not designed to handle large currents itself. Regarding the
application, the most heated elements are the external
NMOS transistors. In case an SMD transistors are used,
maximum power dissipation, thermal resistance of the
NMOSs and cooling area of the PCB should be considered
to keep the junction temperature of the controller below
150°C.
For optimal performance, place the transistors and the
input and output capacitors as close as possible to the
NCV68261. Tracks carrying high load current − Input
(Battery), Source, Drain (Protected Battery) and GND are
recommended to connect using power planes on the PCB.
An example PCB Layout with inrush current reduction
circuitry is shown in Figure 30.
ORDERING INFORMATION
†
Device
Application
Marking
Package
Shipping
NCV68261MTWAITBG
Ideal Diode and High
Side Switch
V6
WDFNW6
(Pb−Free)
3,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW6 2x2, 0.65P
CASE 511DW
ISSUE B
DATE 15 JUN 2018
SCALE 4:1
GENERIC
MARKING DIAGRAM*
XXMG
G
M
= Month Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON79327G
WDFNW6 2x2, 0.65P
PAGE 1 OF 1
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